A semiconductor device and a manufacturing method thereof

Abstract

The embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a source electrode and a drain electrode arranged in a substrate; a gate oxide layer located above the substrate; a gate electrode formed above the gate oxide layer, and the gate electrode is located between the source electrode and the drain electrode; the gate electrode comprises a floating gate located above the gate oxide layer and a first control gate, and a second control gate located above the floating gate and the first control gate; wherein the first control gate has a first threshold voltage; the second control gate has a second threshold voltage; the first threshold voltage and the second threshold voltage are different; and a dielectric layer is arranged between the floating gate, the first control gate and the second control gate.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor manufacturing, and in particular, to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Non-volatile memory devices can maintain their stored data even when power is disconnected. Non-volatile memory devices include floating gate flash (FGF), SONOS-type memory, and TANOS-type memory.

[0003] The basic storage unit of a floating gate flash is a floating gate transistor. The floating gate transistor includes a tunneling layer and a floating gate (i.e., polysilicon) formed in sequence on a silicon substrate provided with a source and a drain, and a barrier layer and a control gate formed in sequence on the floating gate. A write operation is performed by applying a positive voltage to the control gate, so that electrons are injected into the floating gate through the tunneling layer; and an erase operation is performed by applying a positive voltage to the substrate, so that the electrons are pulled out of the floating gate. In a storage unit of a SONOS-type memory, a source and a drain are provided in a silicon substrate (S), and a silicon oxide (O) and a silicon nitride (N) are formed in sequence on the silicon substrate as a tunneling layer and a charge storage layer, respectively, and a silicon oxide (O) and polysilicon (S) are formed in sequence on the charge storage layer as a barrier layer and a gate, respectively. In a storage unit of a TANOS-type memory, a tantalum nitride (T), an aluminum oxide (A), a silicon nitride (N), a silicon oxide (O), and silicon (S) are used in sequence as a gate, a barrier layer, a charge storage layer, a tunneling layer, and a substrate, respectively.

[0004] Although the floating gate flash described above has good interference resistance, the process of the floating gate flash is complex and the working voltage is high, and as the number of times that electrons pass through the tunneling layer increases, the quality requirement for the tunneling layer is also higher. The SONOS-type memory and the TANOS-type memory described above have simple structures, a small number of masks, low manufacturing costs, and low working voltages, but the SONOS-type memory and the TANOS-type memory have poor interference resistance and poor thermal stability. SUMMARY

[0005] Therefore, embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof to solve at least one of the above technical problems.

[0006] To achieve the above object, the technical scheme of the present disclosure is as follows:

[0007] In a first aspect, embodiments of the present disclosure provide a semiconductor device, which comprises:

[0008] a source and a drain provided in a substrate;

[0009] a gate oxide layer located above the substrate;

[0010] a gate formed on the gate oxide layer, and the gate is between the source and the drain;

[0011] the gate includes a floating gate and a first control gate on the gate oxide layer, and a second control gate on the floating gate and the first control gate; wherein the first control gate has a first threshold voltage; the second control gate has a second threshold voltage; the first threshold voltage and the second threshold voltage are different;

[0012] a dielectric layer disposed between the floating gate and the first control gate, and the second control gate.

[0013] In some embodiments, the first threshold voltage is greater than the second threshold voltage.

[0014] In some embodiments, the material of the first control gate and the second control gate includes a doped metal material or an undoped metal material.

[0015] In some embodiments, in the case that the material of the first control gate and the second control gate includes a doped metal material, the doping concentrations of the first control gate and the second control gate are different.

[0016] In the case that the material of the first control gate and the second control gate includes an undoped metal material, the thicknesses of the first control gate and the second control gate in a direction perpendicular to the substrate are different or the materials of the first control gate and the second control gate are different.

[0017] In some embodiments, the material of the floating gate includes at least one of silicon carbide or silicon germanium carbide.

[0018] In some embodiments, the semiconductor device further includes:

[0019] an isolation layer covering the sidewalls of the gate and the top surface away from the substrate; wherein the material of the isolation layer includes a low dielectric constant material.

[0020] In some embodiments, the sum of the width of the floating gate in the extension direction of the bit line and the thickness of the first control gate in the direction perpendicular to the substrate is greater than the width of the second control gate in the extension direction of the bit line.

[0021] In some embodiments, the semiconductor device further includes:

[0022] a word line, the word line is connected with the first control gate and the second control gate;

[0023] a bit line, the bit line is connected with the drain.

[0024] In a second aspect, the embodiments of the present disclosure provide a method for manufacturing a semiconductor device, the method comprising:

[0025] providing a substrate;

[0026] forming a gate oxide layer on the substrate;

[0027] forming a floating gate on the gate oxide layer;

[0028] forming a dielectric layer on a sidewall of the floating gate and a top surface away from the substrate;

[0029] forming a first control gate on the gate oxide layer, the first control gate having a sidewall directly contacting the dielectric layer on the sidewall of the floating gate;

[0030] forming a second control gate on the first control gate and the dielectric layer on the top surface away from the substrate; wherein the floating gate, the first control gate, and the second control gate form a gate electrode; the first control gate has a first threshold voltage; the second control gate has a second threshold voltage; the first threshold voltage and the second threshold voltage are different;

[0031] forming a source and a drain in the substrate on both sides of the gate electrode.

[0032] In some embodiments, the first threshold voltage is greater than the second threshold voltage.

[0033] In some embodiments, the first control gate and the second control gate comprise a doped metal material or an undoped metal material.

[0034] In some embodiments, where the material of the first control gate and the second control gate comprises a doped metal material, the first control gate and the second control gate have different doping concentrations.

[0035] where the material of the first control gate and the second control gate comprises an undoped metal material, the first control gate and the second control gate have different thicknesses in a direction perpendicular to the substrate or the material of the first control gate and the second control gate are different.

[0036] In some embodiments, the material of the floating gate comprises at least one of silicon carbide or silicon germanium carbide.

[0037] In some embodiments, the method further comprises:

[0038] forming an isolation layer covering the sidewall of the gate electrode and the top surface away from the substrate; wherein the material of the isolation layer comprises a low dielectric constant material.

[0039] In some embodiments, the sum of the width of the floating gate along the extension direction of the bit line and the thickness of the first control gate along the direction perpendicular to the substrate is greater than the width of the second control gate along the extension direction of the bit line.

[0040] In some embodiments, the manufacturing method further includes:

[0041] A word line is formed, and the word line is connected to the first control gate and the second control gate;

[0042] A bit line is formed, and the bit line is connected to the drain.

[0043] This disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes: a source and a drain disposed within a substrate; a gate oxide layer located on the substrate; a gate formed on the gate oxide layer, with the gate located between the source and the drain; the gate includes a floating gate and a first control gate located on the gate oxide layer, and a second control gate located on the floating gate and the first control gate; wherein the first control gate has a first threshold voltage; the second control gate has a second threshold voltage; the first threshold voltage and the second threshold voltage are different; and a dielectric layer is disposed between the floating gate and the first and second control gates. In this disclosure, a first control gate is disposed on the sidewall of the floating gate, and a second control gate is disposed on the floating gate and the first control gate. By simultaneously controlling the floating gate using the first and second control gates with different threshold voltages, the write potential of the semiconductor device is increased, thereby improving the programming efficiency of the semiconductor device. Attached Figure Description

[0044] FIG. 1A A top-view perspective view of a floating-gate flash memory;

[0045] FIG. 1B for FIG. 1A A partial cross-sectional view of a floating-gate flash memory along the XX direction is shown.

[0046] FIG. 1C for FIG. 1A A partial cross-sectional view of a floating-gate flash memory along the YY direction is shown.

[0047] FIG. 2A A top-view perspective view of a semiconductor device provided in an embodiment of this disclosure;

[0048] FIG. 2B for FIG. 2A A partial cross-sectional view of the semiconductor device shown along XX;

[0049] FIG. 2C for FIG. 2A A partial cross-sectional view of the semiconductor device along the YY direction is shown.

[0050] FIG. 3A A schematic diagram of a semiconductor device according to an embodiment of the present disclosure is provided;

[0051] FIG. 3B A band diagram of the first control gate and the second control gate according to an embodiment of the present disclosure is provided;

[0052] FIG. 4 A schematic diagram of a partial cross-sectional structure of a semiconductor device and an equivalent circuit diagram thereof according to an embodiment of the present disclosure are provided;

[0053] FIG. 5 A flowchart of a manufacturing method of a semiconductor device according to an embodiment of the present disclosure is provided;

[0054] FIG. 6A A top view during the manufacturing process of a semiconductor device according to an embodiment of the present disclosure is provided;

[0055] FIG. 6B A cross-sectional view of a semiconductor device along X-X according to an embodiment of the present disclosure is provided; FIG. 6A

[0056] A cross-sectional view of a semiconductor device along Y-Y according to an embodiment of the present disclosure is provided; FIG. 6C FIG. 6A A cross-sectional view along X-X during the manufacturing process of a semiconductor device according to an embodiment of the present disclosure is provided;

[0057] FIG. 6D A cross-sectional view along Y-Y during the manufacturing process of a semiconductor device according to an embodiment of the present disclosure is provided;

[0058] FIG. 6E A cross-sectional view along X-X during the manufacturing process of a semiconductor device according to an embodiment of the present disclosure is provided;

[0059] FIG. 6F A cross-sectional view along Y-Y during the manufacturing process of a semiconductor device according to an embodiment of the present disclosure is provided;

[0060] FIG. 6G A cross-sectional view along X-X during the manufacturing process of a semiconductor device according to an embodiment of the present disclosure is provided;

[0061] FIG. 6H A cross-sectional view along Y-Y during the manufacturing process of a semiconductor device according to an embodiment of the present disclosure is provided;

[0062] FIG. 6I A perspective view from a top view angle during the manufacturing process of a semiconductor device according to an embodiment of the present disclosure is provided;

[0063] FIG. 6J A perspective view from a bottom view angle during the manufacturing process of a semiconductor device according to an embodiment of the present disclosure is provided;

[0064] FIG. 6K A perspective view from a bottom view angle during the manufacturing process of a semiconductor device according to an embodiment of the present disclosure is provided; FIG. 6JA sectional view of the semiconductor device along X-X is shown.

[0065] FIG. 6L For FIG. 6J A sectional view of the semiconductor device along Y-Y is shown.

[0066] The figures include: 101, 201, 301, active region; 102, 202, 302, source; 103, 203, 303, drain; 104, 204, 304, gate oxide layer; 105, 205, 305, first isolation layer; 106, 206, 306, floating gate; 107, 207, 307, dielectric layer; 307', dielectric material layer; 108, control gate; 208a, 308a, first control gate; 208b, 308b, second control gate; 308a', first control gate material layer; 109, 209, 309, second isolation layer; 110, 210, 310, cover layer; 111, 211, 311, word line; 112, 212, 312, bit line; 313, trench. DETAILED DESCRIPTION

[0067] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in combination with the embodiments of the present disclosure and the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0068] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid obscuring the present disclosure, some technical features known in the art are not described; that is, not all features of the actual embodiments are described here, and well-known functions and structures are not described in detail.

[0069] In the drawings, the sizes of layers, regions, elements and their relative sizes can be exaggerated for clarity. The same reference signs represent the same elements throughout.

[0070] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0071] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0072] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0073] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description in order to explain the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail as follows, however, in addition to these detailed descriptions, the present disclosure can also have other implementations.

[0074] Hereinafter, the thickness direction of the substrate is defined as the Z direction, and the X direction and the Y direction which intersect with each other are defined in the top surface or the bottom surface of the substrate perpendicular to the Z direction, and the top surface or the bottom surface of the substrate perpendicular to the Z direction can be determined based on the X direction and the Y direction. For example, the X direction and the Y direction can have a certain included angle. For another example, the X direction and the Y direction are perpendicular to each other, and thus the X direction, the Y direction and the Z direction are perpendicular to each other in pairs.

[0075] The floating gate type flash memory belongs to a non-volatile memory device, that is, the stored data will not be lost even in the case of power failure. The structure of the floating gate type flash memory will be described in detail below in combination with FIG. 1A , FIG. 1B and FIG. 1C .

[0076] As shown in FIG. 1B and FIG. 1C , the floating gate type flash memory includes a plurality of active regions 101 parallel to the X direction formed on the substrate, and the active regions 101 are further provided with a source 102 and a drain 103, a gate oxide layer 104 is formed on the side wall of the active region 101 and the top surface away from the substrate, and a first isolation layer 105 is provided between adjacent active regions 101.

[0077] It should be noted that the substrate is etched to form the active region and the groove between the active regions, and the depth of the groove is less than the thickness of the substrate, that is, the groove formed by etching the substrate does not penetrate the substrate. FIG. 1C Only the partial cross-sectional structure of the floating gate type flash memory is shown.

[0078] In one specific example, the material of the substrate can be poly (poly).

[0079] Here, the substrate can be P-type doped, that is, a P-type doped active region is formed. The substrate can also be N-type doped, that is, an N-type doped source and drain are formed.

[0080] As shown in FIG. 1B and FIG. 1C , the floating gate type flash memory further includes a plurality of floating gates 106 on the gate oxide layer 104, the plurality of floating gates 106 are arranged in an array along the X direction and the Y direction, a dielectric layer 107 on the floating gate 106, a control gate 108 on the dielectric layer 107, and a second isolation layer 109 covering the side wall of the floating gate 106 and the control gate 108 and the top surface of the control gate 108 away from the substrate.

[0081] In one specific example, the material of the second isolation layer is silicon nitride (Si3N4), and the dielectric constant of the silicon nitride is 9.4 to 9.5.

[0082] Still as shown in FIG. 1B and FIG. 1C , the floating gate type flash memory further includes a cover layer 110 covering the second isolation layer 109.

[0083] As shown in FIG. 1A , the floating gate type flash memory further includes a word line 111 connected with the control gate 108, and a bit line 112 connected with the drain electrode. Wherein, the floating gate type flash memory includes a plurality of word lines parallel to the Y direction and a plurality of bit lines parallel to the X direction, that is, the extension direction of the word line is parallel to the Y direction, and the extension direction of the bit line is parallel to the X direction.

[0084] Here, the control gate (CG) is located on the surface of the floating gate (FG) away from the substrate, the control gate and the floating gate are isolated by a dielectric layer, and the orthogonal projection of the floating gate on the substrate is located within the orthogonal projection of the control gate on the substrate.

[0085] In one specific example, the materials of the control gate and the floating gate can both be polysilicon. Here, the control gate and the floating gate can also be N-type doped, that is, to form an N-type doped control gate and floating gate.

[0086] For the floating gate type flash memory, during the programming operation, a positive voltage is applied to the control gate to activate the channel between the source electrode and the drain electrode, a high voltage is applied to the source electrode to generate a voltage difference between the source electrode and the drain electrode to generate channel hot electrons, when the electrons flow from the drain electrode to the source electrode and obtain kinetic energy, these electrons will accelerate from the channel to the floating gate through the gate oxide layer, and be captured on the floating gate. While during the erasing operation, a high voltage can be applied to the control gate, so that the electrons in the floating gate are transferred to the control gate through the dielectric layer.

[0087] However, as the number of programming and erasing operations increases, the electrons frequently inject into the floating gate through the gate oxide layer and are pulled out of the floating gate and through the gate oxide layer, which can have an adverse effect on the material of the gate oxide layer, thereby possibly causing the floating gate type flash memory to have a reliability defect.

[0088] Therefore, the embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof.

[0089] The structure of the semiconductor device provided by the embodiments of the present disclosure will be described in detail below in combination with FIG. 2A , FIG. 2B and FIG. 2C .

[0090] As shown in FIG. 2B and FIG. 2CAs shown, the semiconductor device provided in this embodiment includes: a source 202 and a drain 203 disposed in an active region 201 of a substrate; a gate oxide layer 204 located on the active region 201; a gate formed on the gate oxide layer 204, and the gate is located between the source 202 and the drain 203; the gate includes a floating gate 206 and a first control gate 208a located on the gate oxide layer 204, and a second control gate 208b located on the floating gate 206 and the first control gate 208a; wherein the first control gate 208a has a first threshold voltage; the second control gate 208b has a second threshold voltage; the first threshold voltage and the second threshold voltage are different; and a dielectric layer 207 disposed between the floating gate 206 and the first control gate 208a and the second control gate 208b.

[0091] Formation as FIG. 2B and FIG. 2C The process for creating the active region is as follows: The substrate is etched to form multiple active regions 201 parallel to the X-direction and multiple grooves parallel to the X-direction; a gate oxide layer 204 is formed on the sidewalls of the active regions 201 parallel to the X-direction and on the top surface away from the substrate; the grooves are filled to form a first isolation layer 205; the active regions 201 are doped to form source electrodes 202 and drain electrodes 203. Any two adjacent active regions 201 are separated by the first isolation layer 205, and the surface of the first isolation layer 205 is flush with the surface of the gate oxide layer 204.

[0092] It should be noted that the active region is formed by etching the substrate and the groove located between the active region. The depth of the groove is less than the thickness of the substrate, that is, the groove formed by etching the substrate does not penetrate the substrate. FIG. 2C Only a partial cross-sectional structure of the semiconductor device is shown.

[0093] Here, the substrate material may include at least one of single-crystal silicon (Si), single-crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. In a specific example, the substrate material may be polycrystalline silicon.

[0094] Here, the substrate can be P-type doped, i.e., a P-type doped active region can be formed. Alternatively, the substrate can be N-type doped, i.e., N-type doped source and drain electrodes can be formed. This disclosure does not impose any limitations on the doping types of the substrate, source, and drain electrodes.

[0095] Here, the material of the gate oxide layer may include silicon oxide.

[0096] In the embodiments of the present disclosure, the semiconductor device can be a certain transistor in a peripheral circuit of a NAND memory device; the semiconductor device can also be a transistor of a dynamic random access memory (DRAM), which, together with a storage capacitor, forms a storage unit of the DRAM; and the semiconductor device can also be a transistor array, in which each transistor realizes a storage function by using a floating gate.

[0097] As shown in FIG. 2A , the semiconductor device further includes a word line 211 connected with the first control gate 208a and the second control gate 208b, and a bit line 212 connected with the drain. FIG. 2A The storage unit of the semiconductor device shown in

[0098] In the embodiments of the present disclosure, the first control gate is arranged on the sidewall of the floating gate, the second control gate is arranged on the floating gate and the first control gate, the floating gate is controlled by the first control gate and the second control gate with different threshold voltages at the same time, so as to increase the write potential of the semiconductor device and improve the programming efficiency of the semiconductor device.

[0099] As shown in FIG. 2B , the floating gate 206 is located above the gate oxide layer 204, the dielectric layer 207 is formed on the sidewall of the floating gate 204 and the top surface away from the substrate, and the first control gate 208a is also located above the gate oxide layer 204. The first control gate 208a and the floating gate 206 are isolated by the dielectric layer 207. The second control gate 208b is formed on the dielectric layer 207 on the top surface of the first control gate 208a and the floating gate 206. Among them, the top surface of the first control gate 208a away from the substrate is directly in contact with the bottom surface of the second control gate 208b close to the substrate; the sidewall of the first control gate 208a and the sidewall of the floating gate 206 are isolated by the dielectric layer 207; and the bottom surface of the second control gate 208b close to the substrate and the top surface of the floating gate 206 away from the substrate are isolated by the dielectric layer 207.

[0100] In the embodiments of the present disclosure, the material of the floating gate includes at least one of silicon carbide or silicon germanium carbide.

[0101] Here, the band gap of silicon carbide (SiC) is 2 eV to 3.3 eV, and the band gap of silicon germanium carbide (SiGeC) is 3.2 eV. The use of silicon carbide or silicon germanium carbide having a larger band gap forms a floating gate having a smaller grain size, better thermal conductivity, higher electron speed, and high frequency switching.

[0102] In the embodiments of the present disclosure, the first control gate has a first threshold voltage and the second control gate has a second threshold voltage. In the preferred embodiments of the present disclosure, the first threshold voltage of the first control gate is greater than the second threshold voltage of the second control gate.

[0103] In the embodiments of the present disclosure, the first control gate with a high threshold voltage can reduce the electric field from the first control gate to the substrate, and the second control gate with a low threshold voltage can increase the electric field from the second control gate to the floating gate. Since the first control gate contacts the active region of the substrate through the gate oxide layer in the direction perpendicular to the substrate, the distance between the first control gate and the substrate is closer, and reducing the electric field from the first control gate to the substrate can avoid the injection of electrons into the first control gate during programming.

[0104] In the embodiments of the present disclosure, the materials of the first control gate and the second control gate include doped metal materials or undoped metal materials. Here, the first control gate and the second control gate can include the same or different metal materials.

[0105] In the embodiments of the present disclosure, in the case where the materials of the first control gate and the second control gate include doped metal materials, the doping concentrations of the first control gate and the second control gate are different; in the case where the materials of the first control gate and the second control gate include undoped metal materials, the thicknesses of the first control gate and the second control gate in the direction perpendicular to the substrate are different or the materials of the first control gate and the second control gate are different.

[0106] Here, in the case where the materials of the first control gate and the second control gate include doped metal materials, the threshold voltages of the first control gate and the second control gate can be adjusted by adjusting the doping concentrations of the first control gate and the second control gate. For example, the doping concentration of the first control gate is adjusted to be greater than the doping concentration of the second control gate, so that the first threshold voltage of the first control gate is greater than the second threshold voltage of the second control gate. Here, in the case where the materials of the first control gate and the second control gate include doped metal materials, the threshold voltages of the first control gate and the second control gate can also be adjusted by simultaneously adjusting the doping concentrations and the thicknesses of the first control gate and the second control gate. For example, the doping concentration and the thickness of the first control gate are adjusted to be greater than the doping concentration and the thickness of the second control gate, respectively, so that the first threshold voltage of the first control gate is greater than the second threshold voltage of the second control gate.

[0107] Here, in the case that the materials of the first control gate and the second control gate include undoped metal materials, the threshold voltages of the first control gate and the second control gate can be adjusted by adjusting the thicknesses of the first control gate and the second control gate.

[0108] Here, considering that the threshold voltages of the first control gate and the second control gate are adjusted by adjusting the thicknesses of the first control gate and the second control gate, the size of the semiconductor device can be affected, therefore, it is preferred that the threshold voltages of the first control gate and the second control gate are adjusted by adjusting the doping concentrations of the first control gate and the second control gate.

[0109] In one specific example, the materials of the first control gate and the second control gate are titanium nitride (TiN). In this way, the materials of the first control gate and the second control gate are both metal titanium doped with nitrogen element, and the threshold voltages of the first control gate and the second control gate can be adjusted by adjusting the doping concentrations of the first control gate and the second control gate.

[0110] Still as FIG. 2B shown, the semiconductor device further includes: a second isolation layer 209 covering the sidewalls of the gate and away from the top surface of the substrate. More specifically, the second isolation layer 209 covers the sidewalls of the floating gate 206, the sidewalls of the first control gate 208a, the sidewalls of the second control gate 208b, and the top surface of the second control gate 208b away from the top surface of the substrate.

[0111] Here, the floating gate is located above the gate oxide layer, a dielectric layer is formed on one sidewall of the floating gate, a second isolation layer is formed on the other sidewall of the floating gate opposite to the one sidewall, and a dielectric layer is formed on the top surface of the floating gate away from the substrate. The first control gate is located above the gate oxide layer, one sidewall of the first control gate is in contact with the dielectric layer on the sidewall of the floating gate, and a second isolation layer is formed on the other sidewall of the first control gate opposite to the one sidewall. The second control gate is located above the dielectric layer on the top surface of the floating gate and the first control gate, and a second isolation layer is formed on the sidewalls of the second control gate and the top surface away from the substrate.

[0112] In the embodiments of the present disclosure, the material of the second isolation layer includes a low dielectric constant material. Here, the low dielectric constant material can refer to a material with a dielectric constant less than 4.

[0113] In one specific example, the material of the second isolation layer is silicon carbon nitride (SiCN).

[0114] Here, as the second isolation layer, silicon carbon nitride has a small dielectric constant, which can reduce the coupling effect and reduce the parasitic capacitance.

[0115] Still as FIG. 2B and FIG. 2C shown, the floating gate type flash memory further includes: a cover layer 210 covering the second isolation layer 209.

[0116] refer to FIG. 3A , FIG. 3A This is a schematic diagram of a semiconductor device provided in an embodiment of this disclosure. FIG. 3A Show FIG. 2B The memory cell shown in the dashed box, in a direction perpendicular to the substrate, includes a substrate, a gate oxide layer, a floating gate, a dielectric layer, and a second control gate. A programming voltage (V = PGM) is applied to the dielectric layer through the second control gate, generating an electric field between the substrate and the second control gate. Negatively charged electrons in the substrate are affected by the electric field, and the energy band of the gate oxide layer between the substrate and the floating gate bends. When the energy gained by the electrons under the influence of the electric field is large enough, electrons in the substrate will pass through the gate oxide layer and move into the floating gate to perform programming operations.

[0117] refer to FIG. 3B , FIG. 3B Energy band diagrams of the first and second control gates provided for embodiments of this disclosure. FIG. 3B As shown, M1 corresponds to the first control gate, M3 corresponds to the second control gate, and the work function Φ of the first control gate is... m1 The work function Φ is greater than that of the second control gate. m3 Therefore, Φ m1 >Φ m3 .

[0118]

[0119]

[0120] Φ ms =Φ m -Φ s (Equation 3)

[0121] Among them, V T Threshold voltage, measured in volts (V); V FB Φ is the flat-band voltage across the gate oxide layer, measured in volts (V); F The surface potential required to generate strong inversion is expressed in volts (V); q is the electron charge, expressed in coulombs (C); N A The doping concentration of the substrate is expressed in particles per cubic centimeter (particles / cm³). 3 );ε Si C is the relative permittivity of silicon, expressed in farads per meter (F / m); OX The capacitance per unit area of ​​the gate oxide layer, expressed in farads per square centimeter (F / cm²). 2 );Φ ms Q represents the difference in work function between a metal and a semiconductor, measured in volts (V). F The amount of surface charge per unit area, expressed in coulombs per square centimeter (C / cm²).2 ) ; Φ m is a work function of the metal, in volts (V) ; Φ S is a work function of the semiconductor, in volts (V).

[0122] Since the work function Φ m1 of the first control gate is greater than the work function Φ m3 of the second control gate, according to equation 3, the work function difference between the first control gate and the semiconductor (i.e., the substrate) is greater than the work function difference between the second control gate and the semiconductor (i.e., the substrate). According to equations 1 and 2, the first threshold voltage of the first control gate is greater than the second threshold voltage of the second control gate. Therefore, the first control gate M1 corresponds to a high threshold voltage, and the second control gate M3 corresponds to a low threshold voltage.

[0123] Referring to FIG. 4 , FIG. 4 is a partial cross-sectional structure schematic diagram of a semiconductor device provided by an embodiment of the present disclosure and an equivalent circuit diagram thereof. As shown in FIG. 4 (a), a memory cell of a floating gate type flash memory includes an active region 101 provided with a source 102 and a drain 103; a gate oxide layer 104 located on the active region 101, a floating gate 106 located on the gate oxide layer 104, a dielectric layer 107 located on the floating gate 106, a control gate 108 located on the dielectric layer 207, and a second isolation layer 109 covering the sidewalls of the floating gate 106 and the control gate 108 and the top surface of the control gate 108 away from the substrate.

[0124] FIG. 4 (a) shows the size L1 of the control gate 108 in the X direction, that is, the width of the control gate 108 in the extension direction of the bit line is L1; the size L2 of the floating gate 106 in the X direction, that is, the width of the floating gate 106 in the extension direction of the bit line is L2. In one specific example, L1 = L2.

[0125]

[0126]

[0127]

[0128]

[0129] Wherein, C1 is the capacitance formed by the control gate 108 and the floating gate 106, in farads (F); ε1 is the relative permittivity of the dielectric layer 107, in farads per meter (F / m); L1 is the width of the control gate 108 along the X direction, in meters (m); W is the dimension of the floating gate 106 along the Y direction, in meters (m); d is the distance between the control gate 108 and the floating gate 106 in a direction perpendicular to the substrate, or d is the distance between the floating gate 106 and the active region 101 of the substrate in a direction perpendicular to the substrate, in meters (m); C2 ε1 is the capacitance formed by the floating gate 106 and the active region 101 of the substrate, in farads (F); ε2 is the relative permittivity of the gate oxide layer 104, in farads per meter (F / m); L2 is the width of the floating gate 106 along the X direction, in meters (m); U1 is the potential difference between the control gate 108 and the floating gate 106, in volts (V); U2 is the potential difference between the floating gate 106 and the active region 101 of the substrate, in volts (V); U is the potential difference between the control gate 108 and the active region 101 of the substrate, in volts (V).

[0130] According to Equations 4 and 5, if the dielectric layer 107 and the gate oxide layer 104 are made of the same material, i.e., ε1 = ε2, then C1 = C2. According to Equations 6 and 7, if C1 = C2, then U1 = U2 = 0.5U.

[0131] like FIG. 4 As shown in (b), the semiconductor device provided in this embodiment includes: an active region 201 having a source 202 and a drain 203; a gate oxide layer 204 located on the active region 201; a floating gate 206 located on the gate oxide layer 204; a dielectric layer 207 formed on one sidewall and the top surface away from the substrate of the floating gate 206; a first control gate 208a located on the gate oxide layer 204, the sidewall of the first control gate 208a being in direct contact with the dielectric layer 207 on the sidewall of the floating gate 206; and a second control gate 208b located on the dielectric layer 207 and the first control gate 208a.

[0132] FIG. 4 (b) shows the dimension L3 of the portion of the floating gate 206 away from the substrate along the X direction, i.e., the width of the portion of the floating gate 206 away from the substrate along the extension direction of the bit line is L3; the dimension L4 of the portion of the floating gate 206 near the substrate along the X direction, i.e., the width of the portion of the floating gate 206 near the substrate along the extension direction of the bit line is L4; the dimension L1 of the second control gate 208b along the X direction, i.e., the width of the second control gate 208b along the extension direction of the bit line is L1; and the dimension H of the first control gate 208a along the Z direction, i.e., the thickness of the first control gate 208a in the direction perpendicular to the substrate is H. In a specific example, L3 = L4, L3 <L1,L4<L1。

[0133]

[0134]

[0135]

[0136]

[0137] C3= ε3L3W / d, C4= ε4L4W / d, U3= U1- U2, U4= U1- U, L1= L3+ L4, where C3 is a capacitance formed by the first control gate 208a, the second control gate 208b and the floating gate 206, in Farad (F); ε3 is a relative permittivity of the dielectric layer 207, in Farad per meter (F / m); L3 is a width of the floating gate 206 away from the substrate along the X direction, in meter (m); W is a dimension of the floating gate 206 along the Y direction, in meter (m); d is a distance between the first control gate 208b and the floating gate 206 along a direction perpendicular to the substrate or d is a distance between the first control gate 208a and the floating gate 206 along the X direction or d is a distance between the floating gate 206 and the active region 201 of the substrate along a direction perpendicular to the substrate, in meter (m); C4 is a capacitance formed by the floating gate 206 and the active region 201 of the substrate, in Farad (F); ε4 is a relative permittivity of the gate oxide layer 204, in Farad per meter (F / m); L4 is a width of the floating gate 206 close to the substrate along the X direction, in meter (m); U1 is a potential difference between the first control gate 208a, the second control gate 208b and the floating gate 206, in volt (V); U2 is a potential difference between the floating gate 206 and the active region 201 of the substrate, in volt (V); U is a potential difference between the first control gate 208a, the second control gate 208b and the active region 201 of the substrate, in volt (V); L1 is a width of the second control gate 208b along the X direction, in meter (m).

[0138] According to the formula 8 and the formula 9, if the material of the dielectric layer 207 and the gate oxide layer 204 is the same as the material of the dielectric layer 107 and the gate oxide layer 104, i.e. ε1= ε2= ε3= ε4, then C3> C4. According to the formula 10 and the formula 11, if C3> C4, then U3< U4.

[0139] In the embodiments of the present disclosure, the sum of the width L3 of the floating gate 206 along the extension direction of the bit line and the thickness H of the first control gate 208a along the direction perpendicular to the substrate is greater than the width L1 of the second control gate 208b along the extension direction of the bit line, i.e. (L3+ H) > L1. According to the formula 4 and the formula 8, C3> C1.

[0140] In combination with FIG. 4 (a) and FIG. 4(b) As can be seen, the first control gate is arranged on the sidewall of the floating gate, and the second control gate is arranged on the floating gate and the first control gate. The capacitance formed by the control gates (including the first control gate and the second control gate) and the floating gate is increased from C1 to C3, and the potential difference between the control gates (including the first control gate and the second control gate) and the floating gate is reduced from U1 to U3. The capacitance formed by the floating gate and the active region of the substrate is reduced from C2 to C4, and the potential difference between the floating gate and the active region of the substrate is increased from U2 to U4.

[0141] As FIG. 4 (c) shown, when the write potential Vcg is applied to the control gate, the floating gate potential Vfg is determined by the capacitive coupling. The voltage division U3 of the capacitance C3 is (Vcg-Vfg), and the voltage division U4 of the capacitance C4 is Vfg. As the voltage division U4 of the capacitance C4 increases, that is, the floating gate potential Vfg increases, the electric field acting on the gate oxide layer increases, which is beneficial to injecting electrons into the floating gate. In addition, according to formula 11, when U (or Vcg) is constant, the floating gate potential Vfg increases in proportion to the capacitive coupling ratio [C3 / (C3+C4)]. That is, when the capacitive coupling ratio is large, even if the write potential Vcg decreases, the floating gate potential Vfg sufficient to move electrons can be obtained. Therefore, the operating voltage can be reduced, the power consumption can be reduced, and the programming efficiency of the semiconductor device can be improved.

[0142] Referring to FIG. 5 , FIG. 5 A flowchart of a manufacturing method of a semiconductor device provided by the embodiment of the present disclosure is shown. As FIG. 5 shown, the manufacturing method of the semiconductor device provided by the embodiment of the present disclosure includes the following steps:

[0143] Step S501: providing a substrate;

[0144] Step S502: forming a gate oxide layer on the substrate;

[0145] Step S503: forming a floating gate on the gate oxide layer;

[0146] Step S504: forming a dielectric layer on one sidewall of the floating gate and the top surface away from the substrate;

[0147] Step S505: forming a first control gate on the gate oxide layer, and the dielectric layer on the sidewall of the floating gate directly contacts the sidewall of the first control gate;

[0148] Step S506: forming a second control gate on the dielectric layer on the top surface of the first control gate and the floating gate; wherein the floating gate, the first control gate and the second control gate constitute a gate electrode; the first control gate has a first threshold voltage; the second control gate has a second threshold voltage; and the first threshold voltage and the second threshold voltage are different;

[0149] Step S507: forming a source and a drain in the substrate on both sides of the gate.

[0150] The manufacturing process of the semiconductor device provided by the embodiments of the present disclosure will be described in detail below. FIG. 6A to FIG. 6K The embodiments of the present disclosure do not specially limit the semiconductor device to be a transistor or a transistor array, and the following will be described by taking the semiconductor device to be a transistor array as an example.

[0151] In the embodiments of the present disclosure, in step S501, a substrate is provided; and in step S502, a gate oxide layer is formed on the substrate.

[0152] Referring to FIG. 6A , FIG. 6B and FIG. 6C , FIG. 6A the top view of the manufacturing process of the semiconductor device provided by the embodiments of the present disclosure, FIG. 6B the sectional view of the semiconductor device shown in FIG. 4 along the X-X direction, FIG. 6A the sectional view of the semiconductor device shown in FIG. 4 along the Y-Y direction. FIG. 6C FIG. 6A The process of forming the gate oxide layer 304 shown in and

[0153] is as follows: etching the substrate to form a plurality of active regions 301 parallel to the X direction and a plurality of grooves (not shown in the figure) parallel to the X direction; forming the gate oxide layer 304 on the side walls of the active regions 301 parallel to the X direction and the top surface away from the substrate, and filling the grooves to form a first isolation layer 305. Among them, any two adjacent active regions 301 are isolated by the first isolation layer 305. FIG. 6B FIG. 6C Here, the in-situ steam generation (ISSG) process can be used to form the gate oxide layer covering the side walls of the active region and the top surface away from the substrate. In one specific example, the ISSG process can be used to form an ultra-thin silicon oxide film as the gate oxide layer.

[0154] Here, the chemical mechanical polishing (CMP) process can be used to make the surface of the first isolation layer and the surface of the gate oxide layer flush.

[0155] Here, the chemical mechanical polishing (CMP) process can be used to make the surface of the first isolation layer and the surface of the gate oxide layer flush.

[0156] In the embodiments of the present disclosure, in step S503, a floating gate is formed on the gate oxide layer.

[0157] As shown in FIG. 6D and FIG. 6E ​As shown, the manufacturing method provided by the embodiment of the present disclosure includes: forming a floating gate material layer on the gate oxide layer 304, and etching the floating gate material layer to form a plurality of floating gates 306 arranged in an array along the X direction and the Y direction.

[0158] Here, the orthographic projection of the floating gate on the substrate is located within the active region of the substrate. In other words, the floating gate is in contact with the active region of the substrate through the gate oxide layer and the surface of the substrate.

[0159] In the embodiment of the present disclosure, the material of the floating gate includes at least one of silicon carbide or silicon germanium carbide.

[0160] Here, the band gap of silicon carbide (SiC) is 2eV to 3.3eV, and the band gap of silicon germanium carbide (SiGeC) is 3.2eV. The floating gate is formed by using silicon carbide or silicon germanium carbide with a larger band gap, and the grain size is smaller, the thermal conductivity is better, the electron speed is higher, and the high-frequency switching is better.

[0161] In the embodiment of the present disclosure, in step S504, a dielectric layer is formed on the side wall of the floating gate and the top surface away from the substrate.

[0162] As shown in FIG. 6D and FIG. 6E As shown, the manufacturing method provided by the embodiment of the present disclosure includes: forming a dielectric material layer 307' covering the side wall of the floating gate 306 and the top surface away from the substrate, and the dielectric material layer 307' covers the exposed gate oxide layer 304 between any two adjacent floating gates 306.

[0163] As shown in FIG. 6F and FIG. 6G As shown, the manufacturing method provided by the embodiment of the present disclosure includes: removing the dielectric material layer covering the side wall of the floating gate 306, and removing the dielectric material layer covering the gate oxide layer 304, to form the dielectric layer 307.

[0164] Here, the dielectric layer covers the side wall of each floating gate and the top surface away from the substrate.

[0165] Here, the dielectric layer can be a single-layer structure or a multi-layer structure. For example, the dielectric layer can be a three-layer structure, that is, an oxide-nitride-oxide (ONO) structure.

[0166] In the embodiment of the present disclosure, in step S505, a first control gate is formed on the gate oxide layer, and the side wall of the first control gate is in direct contact with the dielectric layer on the side wall of the floating gate.

[0167] As shown in FIG. 6F and FIG. 6GAs shown, the manufacturing method provided in this embodiment includes: forming a first control gate material layer 308a' on a gate oxide layer 304, wherein a sidewall of the first control gate material layer 308a' is in direct contact with a dielectric layer 307 on a sidewall of a floating gate 306, and another sidewall of the first control gate material layer 308a' opposite to the sidewall is in direct contact with a sidewall of another floating gate 306.

[0168] Here, a chemical mechanical polishing process can be used to make the surface of the first floating gate material layer flush with the surface of the dielectric layer.

[0169] In this embodiment of the present disclosure, in step S506, a second control gate is formed on the dielectric layer on the top surface of the first control gate and the floating gate; wherein, the floating gate, the first control gate and the second control gate constitute a gate; the first control gate has a first threshold voltage; the second control gate has a second threshold voltage; the first threshold voltage and the second threshold voltage are different.

[0170] like FIG. 6H and FIG. 6I As shown, the manufacturing method provided in this embodiment includes: forming a second control gate material layer on a first floating gate material layer and a dielectric layer 307; sequentially etching away a portion of the second control gate material layer and a portion of the first control gate material layer until a trench 313 is formed exposing the gate oxide layer 304. The remaining portion of the second control gate material layer forms a second control gate 308b, and the remaining portion of the first control gate material layer forms a first control gate 308a. Simultaneously, the trench 313 formed in the above etching step exposes the sidewalls of the first control gate 308a and the second control gate 308b.

[0171] In this embodiment of the disclosure, the first threshold voltage is greater than the second threshold voltage.

[0172] In this embodiment, a first control gate with a high threshold voltage can reduce the electric field from the first control gate to the substrate, while a second control gate with a low threshold voltage can increase the electric field from the second control gate to the floating gate. Since the distance between the first control gate and the substrate is closer along the direction perpendicular to the substrate, reducing the electric field from the first control gate to the substrate can prevent electrons from being injected into the first control gate during programming.

[0173] In this embodiment of the disclosure, the materials of the first control gate and the second control gate include doped metal materials or undoped metal materials. When the materials of the first control gate and the second control gate include doped metal materials, the doping concentrations of the first control gate and the second control gate are different; when the materials of the first control gate and the second control gate include undoped metal materials, the thicknesses of the first control gate and the second control gate along the direction perpendicular to the substrate are different, or the materials of the first control gate and the second control gate are different.

[0174] In one specific example, the first control gate and the second control gate are both titanium nitride (TiN). Here, the first control gate and the second control gate have different doping concentrations of nitrogen element, and / or, the first control gate and the second control gate have different thicknesses along the direction perpendicular to the substrate.

[0175] Here, the threshold voltages of the first control gate and the second control gate can be adjusted by adjusting the doping concentrations of the first control gate and the second control gate. The threshold voltages of the first control gate and the second control gate can also be adjusted by adjusting the thicknesses of the first control gate and the second control gate.

[0176] In the embodiments of the present disclosure, in step S507, the source and the drain are formed in the substrate on both sides of the gate.

[0177] Still as FIG. 6H and FIG. 6I shown, the manufacturing method provided by the embodiments of the present disclosure includes: performing ion implantation on the active region 301 of the substrate through the trench 313 to form the source 302 and the drain 303 in the substrate on both sides of the gate.

[0178] Here, an annealing process can also be performed to promote ion diffusion.

[0179] Referring to FIG. 6J , FIG. 6K and FIG. 6L , FIG. 6J the top view of the semiconductor device in the manufacturing process provided by the embodiments of the present disclosure, FIG. 6K is shown, FIG. 6J the sectional view of the semiconductor device along X-X, FIG. 6L is shown, FIG. 6J the sectional view of the semiconductor device along Y-Y.

[0180] As FIG. 6K and FIG. 6L shown, the manufacturing method provided by the embodiments of the present disclosure includes: forming a second isolation layer 309 covering the side wall of the gate and away from the top surface of the substrate; and forming a cover layer 310 covering the second isolation layer 309.

[0181] In the embodiments of the present disclosure, the material of the second isolation layer includes a low dielectric constant material. Here, the low dielectric constant material can refer to a material with a dielectric constant less than 4.

[0182] In one specific example, the material of the second isolation layer is silicon carbon nitride (SiCN).

[0183] Here, as the second isolation layer, silicon carbon nitride has a small dielectric constant, which can reduce the coupling effect and reduce the parasitic capacitance.

[0184] As FIG. 6JAs shown, the manufacturing method provided by the embodiment of the present disclosure includes: forming a word line 311, the word line 311 being connected with the first control gate 308a and the second control gate 308b; and forming a bit line 312, the bit line 312 being connected with the drain.

[0185] In the embodiment of the present disclosure, the sum of the width of the floating gate along the extension direction of the bit line and the thickness of the first control gate along the direction perpendicular to the substrate is greater than the width of the second control gate along the extension direction of the bit line.

[0186] Here, the capacitance formed by the control gate and the floating gate increases, the potential difference between the control gate and the floating gate decreases, the capacitance formed by the floating gate and the active region of the substrate decreases, and the potential difference between the floating gate and the active region of the substrate increases, so that the floating gate potential Vfg increases, the working voltage can be reduced, the power consumption can be reduced, and the programming efficiency of the semiconductor device can be improved.

[0187] The embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a source and a drain arranged in a substrate; a gate oxide layer located above the substrate; a gate formed above the gate oxide layer and located between the source and the drain; the gate comprises a floating gate and a first control gate located above the gate oxide layer, and a second control gate located above the floating gate and the first control gate; the first control gate has a first threshold voltage; the second control gate has a second threshold voltage; the first threshold voltage and the second threshold voltage are different; and a dielectric layer is arranged between the floating gate, the first control gate and the second control gate. In the embodiment of the present disclosure, the first control gate is arranged on the sidewall of the floating gate, the second control gate is arranged on the floating gate and the first control gate, the first control gate and the second control gate with different threshold voltages are used to control the floating gate at the same time, so as to increase the write potential of the semiconductor device, thereby improving the programming efficiency of the semiconductor device.

[0188] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that the size of the sequence number of each process in various embodiments of the present disclosure does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiment of the present disclosure. The sequence number of the above-mentioned embodiment of the present disclosure is only for description, not representing the advantages and disadvantages of the embodiment.

[0189] The above merely describes the preferred embodiments of the present disclosure, and is not intended to limit the patent scope of the present disclosure. Any equivalent structural changes made according to the disclosure, or direct / indirect application in other related technical fields, are included in the patent protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Source and drain electrodes located within the substrate; A gate oxide layer located on the substrate; A gate electrode is formed on the gate oxide layer, and the gate electrode is located between the source electrode and the drain electrode; The gate includes a floating gate and a first control gate located above the gate oxide layer, and a second control gate located on the floating gate and the first control gate; wherein the first control gate has a first threshold voltage; the second control gate has a second threshold voltage; the first threshold voltage and the second threshold voltage are different; A dielectric layer disposed between the floating gate and the first control gate and the second control gate; The materials of the first control gate and the second control gate include nitrogen-doped metal materials or undoped metal materials; When the materials of the first control gate and the second control gate include nitrogen-doped metal materials, the doping concentrations of the first control gate and the second control gate are different; When the materials of the first control gate and the second control gate include undoped metal materials, the thickness of the first control gate and the second control gate is different along the direction perpendicular to the substrate, or the materials of the first control gate and the second control gate are different.

2. The semiconductor device according to claim 1, characterized in that, The first threshold voltage is greater than the second threshold voltage.

3. The semiconductor device according to claim 1, characterized in that, The material of the floating gate includes at least one of the following: silicon carbide or silicon carbide germanium.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: An isolation layer covering the sidewalls of the gate and the top surface away from the substrate; wherein the material of the isolation layer includes a low dielectric constant material.

5. The semiconductor device according to claim 1, characterized in that, The sum of the width of the floating gate along the extension direction of the bit line and the thickness of the first control gate along the direction perpendicular to the substrate is greater than the width of the second control gate along the extension direction of the bit line.

6. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: The word line is connected to the first control gate and the second control gate; Bit line, which is connected to the drain.

7. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: Provide substrate; A gate oxide layer is formed on the substrate; A floating gate is formed on the gate oxide layer; A dielectric layer is formed on one sidewall of the floating gate and on the top surface away from the substrate; A first control gate is formed on the gate oxide layer, and the sidewall of the first control gate is in direct contact with the dielectric layer on the sidewall of the floating gate. A second control gate is formed on a dielectric layer on the top surface of the first control gate and the floating gate; wherein the floating gate, the first control gate, and the second control gate constitute a gate; the first control gate has a first threshold voltage; the second control gate has a second threshold voltage; the first threshold voltage and the second threshold voltage are different. The source and drain are formed in the substrate on both sides of the gate; The first control gate and the second control gate comprise nitrogen-doped metal materials or undoped metal materials; When the materials of the first control gate and the second control gate include nitrogen-doped metal materials, the doping concentrations of the first control gate and the second control gate are different; When the materials of the first control gate and the second control gate include undoped metal materials, the thickness of the first control gate and the second control gate is different along the direction perpendicular to the substrate, or the materials of the first control gate and the second control gate are different.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The first threshold voltage is greater than the second threshold voltage.

9. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The material of the floating gate includes at least one of the following: silicon carbide or silicon carbide germanium.

10. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The manufacturing method further includes: An isolation layer is formed covering the sidewalls of the gate and the top surface away from the substrate; wherein the material of the isolation layer includes a low dielectric constant material.

11. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The sum of the width of the floating gate along the extension direction of the bit line and the thickness of the first control gate along the direction perpendicular to the substrate is greater than the width of the second control gate along the extension direction of the bit line.

12. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The manufacturing method further includes: A word line is formed, and the word line is connected to the first control gate and the second control gate; A bit line is formed, and the bit line is connected to the drain.

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