Storage systems, three-dimensional memories and their programming methods

Abstract

Embodiments of this disclosure relate to a three-dimensional memory and a programming method thereof. Embodiments of this disclosure also relate to a three-dimensional memory system. According to the programming method of a three-dimensional memory according to an embodiment of this disclosure, the three-dimensional memory includes a first storage string, the first storage string including a plurality of storage cells, the programming method including: applying a first programming voltage to the first end storage cell in response to data to be stored in the first end storage cell and a first adjacent storage cell adjacent to the first end storage cell being vacant; and applying the first programming voltage to the first adjacent storage cell.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically to memory systems, three-dimensional memories, and programming methods thereof. Background Technology

[0002] Three-dimensional storage structures consist of multiple layers of storage cells, offering significantly greater storage capacity in the same area compared to two-dimensional storage structures. Therefore, mainstream memory devices on the market have largely adopted three-dimensional storage structures.

[0003] Three-dimensional NAND-type memory structures utilize charge trapping layers to store electrons, thereby enabling information storage. However, electrons can migrate laterally within the charge trapping layer, reducing the storage reliability of the memory cells. Summary of the Invention

[0004] Embodiments of this disclosure provide a programming method for a three-dimensional memory. The three-dimensional memory includes a first storage string, each storage string including a plurality of storage cells. The programming method includes: applying a first programming voltage to the first end storage cell in response to data to be stored in the first end storage cell and a first adjacent storage cell adjacent to the first end storage cell being vacant; and applying the first programming voltage to the first adjacent storage cell.

[0005] In some implementations, a first programming voltage is applied simultaneously to the first end memory cell and the first adjacent memory cell.

[0006] In some implementations, the programming method further includes applying a first verification voltage to the first end memory cell and the first adjacent memory cell.

[0007] In some embodiments, the three-dimensional memory further includes a second memory string arranged alongside the first memory string to form a memory cell array. The programming method further includes: applying a second programming voltage to the second end memory string in response to data to be stored in the second end memory string and a second adjacent memory string adjacent to the second end memory string being vacant; and applying a second programming voltage to the second adjacent memory string, wherein the second end memory string and the first end memory string are located in different rows in the memory cell array.

[0008] In some implementations, the programming method further includes applying a second verification voltage to the second end memory cell and the second adjacent memory cell.

[0009] In some implementations, the memory cells of the memory array are programmed in a manner that follows the column-wise programming order of the memory cell array.

[0010] Secondly, embodiments of this disclosure provide a three-dimensional memory, the three-dimensional memory comprising: a first storage string, the first storage string including a plurality of storage cells; and peripheral circuitry configured to: apply a first programming voltage to the first end storage cell in response to data to be stored in the first end storage cell of the plurality of storage cells and a first adjacent storage cell adjacent to the first end storage cell being vacant; and apply the first programming voltage to the first adjacent storage cell.

[0011] In some implementations, the peripheral circuitry is configured to synchronously apply a first programming voltage to the first end memory cell and the first adjacent memory cell.

[0012] In some implementations, the peripheral circuitry is also configured to apply a first verification voltage to the first adjacent memory cell and the first end memory cell.

[0013] In some embodiments, the three-dimensional memory further includes a second memory string arranged in parallel with the first memory string to form a memory cell array, and the peripheral circuitry is further configured to: apply a second programming voltage to the second end memory string in response to data to be stored in the second end memory string and a second adjacent memory string adjacent to the second end memory string being vacant; and apply a second programming voltage to the second adjacent memory string, wherein the second end memory string and the first end memory string are located in different rows in the memory cell array.

[0014] In some implementations, the peripheral circuitry is further configured to apply a second verification voltage to the second adjacent memory cell and the second end memory cell.

[0015] In some implementations, the peripheral circuitry is also configured to continuously program the memory cells of the memory array in a manner that follows the column-wise programming sequence of the memory cell array.

[0016] In some embodiments, the three-dimensional memory further includes a second memory string arranged in parallel with the first memory string to form a memory cell array, the three-dimensional memory including a three-dimensional NAND memory structure; and wherein the first memory string and the second memory string each include a channel layer, a tunneling layer, a charge trapping layer and a blocking layer arranged sequentially, and word lines connected to each row of memory cells in the memory cell array are disposed outside the blocking layer.

[0017] A third aspect of this disclosure provides a storage system comprising: the aforementioned three-dimensional memory; and a controller electrically connected to the three-dimensional memory and used to control the three-dimensional memory.

[0018] This disclosure provides a programming method for a three-dimensional memory. This method utilizes adjacent memory cells to limit the last memory cell, reducing electron migration in the last memory cell, thereby improving the reliability of the stored data and minimizing its impact on the stored data. Furthermore, this programming method does not increase programming time and has high programming efficiency. The three-dimensional memory provided by this disclosure has a highly reliable data storage capability. Attached Figure Description

[0019] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0020] Figure 1 This is a schematic circuit diagram of a memory cell array according to an embodiment of the present disclosure;

[0021] Figure 2 This is a schematic diagram of the storage state of the storage string according to the comparative implementation method;

[0022] Figure 3 This is a schematic diagram of the storage state of the storage string after a period of time, based on the comparative implementation method.

[0023] Figure 4 This is a flowchart of a programming method for a three-dimensional memory according to an embodiment of the present disclosure;

[0024] Figure 5 This is a schematic diagram of the storage state of a storage string according to an embodiment of the present disclosure;

[0025] Figure 6 This is a schematic diagram of a storage state of a storage cell array according to an embodiment of the present disclosure;

[0026] Figure 7 This is a schematic diagram of another storage state of the storage string according to an embodiment of the present disclosure;

[0027] Figure 8 This is a schematic diagram of another storage state of the storage cell array according to an embodiment of the present disclosure;

[0028] Figure 9 This is a schematic diagram of the structure of a three-dimensional memory according to an embodiment of the present disclosure; and

[0029] Figure 10 This is a schematic diagram of the structure of a storage system according to an embodiment of the present disclosure. Detailed Implementation

[0030] To better understand this disclosure, various aspects of this disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this disclosure and are not intended to limit the scope of this disclosure in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features. Therefore, without departing from the teachings of this disclosure, the first storage string discussed below may also be referred to as the second storage string, and vice versa.

[0032] In the accompanying drawings, the thickness, dimensions, and shapes of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the length and diameter of the storage string are not to scale in actual production. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0033] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when a statement such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.

[0034] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0035] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0036] Figure 1 This is a circuit diagram of a storage array. (For example...) Figure 1 As shown, the three-dimensional memory 1 may include multiple memory strings 101-104 and multiple word lines 107-108. It is understood that the structure of the three-dimensional memory 1 is not limited to this, and the parallel arrangement of the multiple memory strings 101-104 is not limited to the following. Figure 1 As shown.

[0037] The multiple storage strings 101 to 104 may include a first storage string 101, a second storage string 102, a third storage string 103, and a fourth storage string 104 arranged in parallel, such as... Figure 1 The dashed line type of word lines 107-108 indicates that the three-dimensional memory 1 includes more than just these four. The first storage string 101 includes multiple storage units 120, and the remaining storage strings 102-104 may each include the same number of storage units 120 as the first storage string 101.

[0038] The three-dimensional memory 1 may include a memory cell array based on a stack of three-dimensional NAND-type memory cells. The source and drain of each memory cell 120 are connected in series in its memory string 101-104, and the gate of the memory cell 120 is electrically connected to the corresponding word line 107 / 108. Exemplarily, at least these memory strings 101-104 are arranged in parallel to form a memory cell array. In the memory cell array, memory cells 120 located at the same position along the string direction (column direction) of the memory cells 120 may be controlled by the same word line 107 / 108. Memory cells in the same memory string can be regarded as a column in the memory cell array, and memory cells controlled by the same word line can be regarded as a row in the memory cell array.

[0039] For example, the first memory string 101 includes a top select unit 110 and a bottom select unit 109, and the remaining memory strings 102-104 are similar. The three-dimensional memory 1 includes a top select line 105 and a bottom select line 106. The gates of the plurality of top select units 110 in the three-dimensional memory 1 can be electrically connected to the top select line 105, and the gates of the plurality of bottom select units 109 can be electrically connected to the bottom select line 106.

[0040] The bottom ends of the first storage string 101, the second storage string 102, the third storage string 103, and the fourth storage string 104 can be connected to the common source, and the top ends of the first storage string 101, the second storage string 102, the third storage string 103, and the fourth storage string 104 are electrically connected to different bit lines.

[0041] The top select line 105 and the bottom select line 106 can be used to control the opening or closing of multiple memory strings 101 to 104 electrically connected to them. With the cooperation of common source, bit line and word line, various programming operations such as writing, reading and erasing can be performed on the memory cells 120 at each location in the three-dimensional memory 1.

[0042] When the amount of data stored in a three-dimensional memory 1 is less than the capacity of the three-dimensional memory 1, some idle storage units that do not store data can be reserved in the three-dimensional memory 1. For example... Figure 2 As shown, when data is stored in the three-dimensional memory 1 in a sequential programming manner, the storage cells in the first storage string 101 may include a third storage cell 123, a first storage cell 121, and a second storage cell 122 arranged sequentially from bottom to top. For data storage, the first storage cell 121 and the third storage cell 123 are used, while the second storage cell 122, which is adjacent to the first storage cell 121, is not used. In this storage state, the first storage cell 121 stores data and is adjacent to the second storage cell 122, which does not store data. Therefore, the first storage cell 121 is an open storage cell and can be used as the first end storage cell, the second storage cell 122 is used as the first adjacent storage cell, and the third storage cell 123 is a closed storage cell and can be used as the first closed storage cell.

[0043] Specifically, the first memory string 101 includes a channel layer 141, a tunneling layer 142, a charge trapping layer 143, and a barrier layer 144 arranged sequentially. The portion of the memory string corresponding to each word line 107 / 108 / 111 is considered as a memory cell 121-123, wherein each word line 107 / 108 / 111 and the gate of the memory cell 121-123 are considered as one unit, or in other words, the word line 107 / 108 / 111 is used as the gate. The portion of the charge trapping layer 143 located in each memory cell 121-123 serves as the floating gate of that memory cell 121-123 in the circuit.

[0044] For example, refer to Figure 2The three-dimensional NAND flash memory cell operates by utilizing the electrons stored in the charge trapping layer 143, for example, by reducing the electric field strength at the channel layer 141 of the first word line 108 after a positive voltage is applied. The second memory cell 122, which does not store data, may contain no electrons or only a small number of electrons. The voltage applied to the first word line 108 needs to exceed a threshold to create a sufficient electric field to generate a channel in the channel layer 141 for conduction, while the voltage applied to the second word line 111 only needs to be lower to create a channel in the channel layer 141.

[0045] After data is stored in the memory cell array, electrons in the charge trapping layer 143 may undergo lateral migration after a period of time, specifically as follows: Figure 3 As shown, electrons in the floating gate of the first memory cell 121 may migrate to the floating gate of the second memory cell 122. With a reduced number of electrons in the floating gate of the first memory cell 121, a lower voltage can be applied through the first word line 108 to create a channel in the channel layer 141 for conduction. This results in a decrease in the reliability of the stored data in the first memory cell 121. Lateral electron migration has a greater impact on multi-cell 3D memories because the peripheral circuitry of a 3D memory uses the voltage level to determine the data being read. Specifically, this type of 3D memory uses a single memory cell 120 to represent one of more threshold levels to store more data, based on the principle that the number of electrons that can be stored in the floating gate of the memory cell 120 can be subdivided into multiple levels. Multi-cell 3D memories, such as three-cell (TLC), four-cell (QLC), and even eight-cell 3D memories, are more susceptible to decreased data reliability due to lateral electron migration.

[0046] Figure 4 This is a flowchart of a programming method for a three-dimensional memory according to an embodiment of the present disclosure. (See reference) Figure 4 The programming method 1000 for a three-dimensional memory provided in this disclosure includes the following steps.

[0047] Step S101 involves applying a first programming voltage to the first end memory cell. Specifically, the first programming voltage can be applied to the word line connected to the first end memory cell to store data in the first end memory cell. If all memory cells in the first memory string are used to store data, subsequent steps may not be necessary, and step S101 may be performed in response to the first end memory cell in the plurality of memory cells having data to be stored, and a first adjacent memory cell adjacent to the first end memory cell being vacant.

[0048] There are no significant functional differences between the storage units in the first storage string; they are simply arranged in a column orientation. Therefore, by way of example, before step S101, the first end storage unit and the first adjacent storage unit that does not store data can be determined based on the amount of data to be stored, i.e., step S100. In other embodiments, step S100 may be a step in programming method 1000.

[0049] Step S102: Apply a first programming voltage to the first adjacent memory cell. Specifically, the first programming voltage can be applied to the word line connected to the first adjacent memory cell.

[0050] Exemplarily, the programming method 1000 further includes step S103: applying a first verification voltage to the word line connected to the first adjacent memory cell. Exemplarily, the programming method 1000 further includes the step of applying a first verification voltage to the word line connected to the first end memory cell.

[0051] The programming method for a three-dimensional memory provided in this disclosure enables a first adjacent memory cell to have the same programming state as the first last memory cell. Essentially, this means that the number of electrons in the floating gate of the first adjacent memory cell is comparable to the number of electrons in the floating gate of the first last memory cell, i.e., at the same level. An electric field is formed around the floating gate of the first adjacent memory cell, which to some extent repels electrons in the floating gate of the first last memory cell. This helps to reduce the tendency of electrons to migrate laterally in the first last memory cell, protecting it and improving the data reliability of the first last memory cell.

[0052] In an exemplary implementation, such as Figure 5 As shown, each ellipse in the first storage string 101 represents a storage unit, and these storage units are arranged along the column direction. Data is to be stored in the first storage string 101 and programmed sequentially from bottom to top. It can then be determined that the first storage unit 121 and the storage units below it will store data, and the first storage unit 121 will be used as the first end storage unit to store data. The second storage unit 122, the thirteenth storage unit 133, etc., above the first storage unit are all empty storage units.

[0053] In an exemplary implementation, such as Figure 6 As shown, each ellipse represents a storage unit, which can be used to store data. Figure 6 Considered as Figure 1The illustrated storage cell array topology is a planar structure. These storage cells form a vertical column and a horizontal row. In an exemplary embodiment, all the last storage cells in the three-dimensional memory 1 are located at the same height. Specifically, data will be stored in the three-dimensional memory 1, which includes four storage strings 101-104, using a sequential programming method, for example, starting data storage from the fourth storage cell 124. Below the fourth storage cell 124, for example, a bottom selection cell (not shown) may be provided, or other storage cells containing stored data may be provided below the fourth storage cell 124; therefore, the fourth storage cell 124 is also a closed storage cell.

[0054] The amount of data that each storage unit can store is determined according to the type of the three-dimensional memory 1. For example, a three-level cell type can store three bits of data. Then, based on the amount of data to be stored in the three-dimensional memory 1, such as 120 bits, it can be determined before actual programming that the storage unit in the tenth level is the end storage unit. Specifically, the first storage unit 121 of the first storage string 101 located in the tenth level is used as the first end storage unit. If storing other amounts of data, other storage units can be used as the corresponding first end storage units. For example, as... Figure 6 As shown, the top six rows of storage cells are empty and not used to store the data to be stored this time. After storing data, the storage cell array included in the three-dimensional memory 1 can be regarded as an open storage cell array.

[0055] When storing data, programming can begin from the first storage cell in the lower layer. This is done by applying a programming voltage to the word lines connecting the storage cells in that layer and a bias voltage to the unprogrammed storage strings. This allows electrons in the channel layer 141 corresponding to the currently being programmed, such as the fourth storage cell 124, to tunnel through the tunneling layer 142 and enter the charge trapping layer 143 (floating gate) using quantum tunneling. The storage cells in the second to ninth layers used for data storage are programmed sequentially, with each layer allowing data to be stored according to... Figure 6 Programming in a left-to-right direction.

[0056] For example, at least one layer of virtual storage units 125 / 128 may be provided between storage units used for storing data. Virtual storage units 125 / 128 are not used for storing data, and the storage units in the layer below them are not considered open storage units, but closed storage units.

[0057] After programming all the storage cells of the ninth layer, including the third storage cell 123, the first storage cell 121 and the second storage cell 122 can be programmed. The first storage string 101 also includes a sixth storage cell 126 and a thirteenth storage cell 133 located at higher positions. The sixth storage cell 126 and the thirteenth storage cell 133 located at higher positions are not used to store the data and can be idle storage cells.

[0058] For example, the second storage unit 122 can be programmed simultaneously with the first storage unit 121. The first storage unit 121 serves as the first end storage unit in the first storage string 101, while the second storage unit 122 does not normally require programming. In this embodiment, the second storage unit 122, which serves as the first adjacent storage unit, is programmed to have the same programming state as the first storage unit 121. This allows the second storage unit 122 to suppress the lateral electron migration phenomenon of the first storage unit 121, thereby improving the data reliability of the first storage unit 121.

[0059] The operation on the last and adjacent storage cells in the third storage string 103, the fourth storage string 104, and the second storage string 102 is similar. For example, as... Figure 6 As shown, the storage cell array of the three-dimensional memory 1 uses exactly ten layers of storage cells to store data. In the second storage string 102, the seventh storage cell 127 and the ninth storage cell 129 are both closed storage cells. The eleventh storage cell 131, which is located on the same layer as the first storage cell 121, is the second end storage cell in the second storage string 102. The twelfth storage cell 132, which is located on the same layer as the second storage cell 122, is the second adjacent storage cell in the second storage string 102. Several storage cells, including the tenth storage cell 130 and the fourteenth storage cell 134, are idle. The eleventh storage cell 131 and the twelfth storage cell 132 have the same programming state.

[0060] In an exemplary embodiment, a first programming voltage is applied to the word line connecting the first end memory cell and the word line connecting the first adjacent memory cell. Exemplarily, the first programming voltage is applied simultaneously to both the word line connecting the first end memory cell and the word line connecting the first adjacent memory cell. With this configuration, the programming method for the three-dimensional memory provided by this disclosure has fewer steps and can simultaneously set the first adjacent memory cell to a desired state while storing data in the first end memory cell.

[0061] In an exemplary embodiment, the programming steps further include: applying a first verification voltage to a word line connected to a first adjacent memory cell, and applying a first verification voltage to a word line connected to a first end memory cell.

[0062] Under the action of the first programming voltage, the first storage cell 121 and the second storage cell 122 have the same programming state. Then, a first verification voltage can be applied to the word line connected to the second storage cell 122 to verify that the second storage cell 122, as the first adjacent storage cell, indeed has the desired storage state. In the aforementioned embodiment, after each storage cell 121 / 123 / 124 used for storing data is programmed, it can be verified to ensure correct data storage. The second storage cell 122 and the first storage cell 121 have the same storage level after programming. For example, in an eight-level cell type three-dimensional memory, both the second storage cell 122 and the first storage cell 121 can be in the seventh-level storage state. The second storage cell 122 helps protect the first storage cell 121, preventing it from degrading to the sixth-level storage state.

[0063] The second programming voltage applied to the eleventh memory cell 131 can be different from the first programming voltage applied to the first memory cell 121. Since the eleventh memory cell 131 is the second end memory cell, when the corresponding second programming voltage is applied to it, the same second programming voltage can be applied to the twelfth memory cell 132 simultaneously. Then, a second verification voltage of the corresponding value can be applied to the twelfth memory cell 132 to verify that it has the desired storage state. After programming, the twelfth memory cell 132 and the eleventh memory cell 131 can have the same level of storage state.

[0064] like Figure 7 As shown, the first storage cell 121 and the second storage cell 122 have the same storage level. Specifically, the number of electrons captured by the portion of the charge trapping layer 143 located in the second storage cell 122 is equivalent to the number of electrons captured by its portion in the first storage cell 121. The electrons in the floating gate of the second storage cell 122 exert a repulsive force on the electrons in the floating gate of the first storage cell 121, effectively suppressing the lateral migration of electrons in the first storage cell 121. The first storage cell 121, as the first end storage cell, has improved reliability. Each end storage cell in the three-dimensional memory 1 can be protected by its neighboring storage cells, thereby improving the data reliability of the three-dimensional memory 1.

[0065] like Figure 8 As shown, in many cases, the amount of data to be stored in the three-dimensional memory 1 will cause the last storage units in different storage strings 101 to 104 to not be located in the same layer. Based on the amount of data to be stored, it can be determined that the last storage units in the first storage string 101 and the third storage string 103 are located in the eleventh layer, while the last storage unit in the second storage string 102 of the fourth storage string 104 is located in the tenth layer.

[0066] Data can be stored in the three-dimensional memory 1 using sequential programming, for example, starting from the fourth memory cell 124 of the first memory string 101. When programming to the tenth level, the first memory cell 121 can be programmed first. Since the first memory cell 121 will become a closed memory cell, it is not necessary to program the adjacent second memory cell 122. When programming the eleventh memory cell 131, since the eleventh memory cell 131 is the second end memory cell in the second memory string 102, the twelfth memory cell 132 can be programmed. Specifically, the same first programming voltage can be applied to the word line connecting the eleventh memory cell 131 and the word line connecting the twelfth memory cell 132. After this programming step, the twelfth memory cell 132, as the second adjacent memory cell, and the eleventh memory cell 131, as the second end memory cell, can have the same level of storage state.

[0067] The terms "first," "second," "third," etc., used in this document are only used to distinguish one feature from another and do not imply any limitation on the features. Therefore, in some respects, the second storage string 102 can be regarded as the first storage string, the eleventh storage unit 131 as the first end storage unit, and the twelfth storage unit 132 as the first adjacent storage unit.

[0068] After programming each memory cell in the tenth layer, the memory cells in the eleventh layer can be programmed. When programming the eleventh layer, the second memory cell 122 can be programmed first. Since the second memory cell 122 is the first end memory cell in the first memory string 101, the sixth memory cell 126 can also be programmed. Specifically, the same third programming voltage can be applied to the word line connected to the second memory cell 122 and the word line connected to the sixth memory cell 126. After this programming step, the sixth memory cell 126, as the first adjacent memory cell, and the second memory cell 122, as the first end memory cell, can have the same level of storage state. For example, the tenth memory cell 130 in the second memory string 102 can be left idle. The programming method for a three-dimensional memory provided in this embodiment can improve the reliability of data stored in the three-dimensional memory.

[0069] like Figure 9 As shown, this disclosure provides a three-dimensional memory 20 in another aspect. The three-dimensional memory 20 includes a plurality of three-dimensional memories 1 and peripheral circuitry.

[0070] The three-dimensional memory 1 includes multiple word lines and multiple memory strings. Each memory string includes multiple memory cells. Memory cells located at the same height in multiple memory strings are connected to the same word line.

[0071] The peripheral circuit can also be a semiconductor structure, such as including... Figure 9The following components are shown: page buffer / sensor amplifier 21, column decoder / bit line (BL) driver 22, row decoder / word line (WL) driver 23, voltage generator 24, control logic unit 25, register 26, interface 27, and data bus 28. It should be understood that the three-dimensional memory 20 may also include... Figure 9 Additional peripheral circuitry not shown.

[0072] Page buffer / sensor amplifier 21 can be configured to read / program (write) data from / to the three-dimensional memory 1 according to control signals from the control logic unit 25.

[0073] In one example, the page buffer / sensing amplifier 21 can store a page of programming data (write data) that will be programmed into a page of the three-dimensional memory 1.

[0074] In another example, the page buffer / sensor amplifier 21 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line.

[0075] In yet another example, the page buffer / sensor amplifier 21 can also sense a low-power signal representing a data bit stored in the memory cell from the bit line during a read operation and amplify a small voltage swing to a recognizable logic level. The column decoder / bit line driver 22 can be configured to be controlled by the control logic unit 25 and to select one or more memory strings by applying a bit line voltage generated by the voltage generator 24.

[0076] The line decoder / word line driver 23 can be configured to be controlled by the control logic unit 25 and to select / deselect the three-dimensional memory 1 and the word lines of the memory blocks. The line decoder / word line driver 23 can also be configured to drive the word lines using word line voltages generated by the voltage generator 24.

[0077] In some implementations, the line decoder / word line driver 23 may also select / deselect and drive the source select gate line (not shown) and the drain select gate (not shown).

[0078] Voltage generator 24 can be configured to be controlled by control logic unit 25 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages that will be provided to the memory cell array.

[0079] Control logic unit 25 can be coupled to each part of the peripheral circuitry described above and is configured to control the operation of each part. Control logic unit 25 can execute the flash memory operation methods described below. Register 26 can be coupled to control logic unit 25 and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuitry.

[0080] For example, the control logic unit 25 is configured to: determine, based on the amount of data to be stored in the multiple storage strings, a first end storage unit in a first storage string and a first neighboring storage unit adjacent to the first end storage unit but not storing data. The control logic unit 25 can determine all end storage units and neighboring storage units.

[0081] The control logic unit 25 is configured to program the first end memory cell and the first adjacent memory cell, such that the first adjacent memory cell has the same programming state as the first end memory cell. Exemplarily, the control logic unit 25 is further configured to control the voltage generator 24 to apply a first programming voltage to the word line connected to the first end memory cell and the word line connected to the first adjacent memory cell, respectively.

[0082] The control logic unit 25 is further configured to: control the voltage generator 24 to apply a first verification voltage to the word line connected to the first adjacent memory cell and to apply a first verification voltage to the word line connected to the first end memory cell.

[0083] In an exemplary embodiment, the control logic unit 25 is further configured to: determine, based on the amount of data to be stored in the multiple storage strings, a second end storage unit in the second storage string and a second adjacent storage unit that is adjacent to the second end storage unit but does not store data. Depending on the actual amount of data, the second end storage unit of the second storage string and the first end storage unit of the first storage string may be located at different heights.

[0084] The control logic unit 25 is also configured to control the voltage generator 24 to apply a second programming voltage to the second end memory cell and the second adjacent memory cell, so that the second adjacent memory cell and the second end memory cell have the same programming state.

[0085] The control logic unit 25 is further configured to: control the voltage generator 24 to apply a second verification voltage to the word line connected to the second adjacent memory cell, and to apply a second verification voltage to the word line connected to the second end memory cell.

[0086] For example, the control logic unit 25 is configured to continuously program multiple memory strings to store data.

[0087] Interface 27 can be coupled to control logic unit 25 and act as a control buffer to buffer control commands received from the host (not shown) and forward them to control logic unit 25, and to buffer status information received from control logic unit 25 and forward it to the host. Interface 27 can also be coupled to column decoder / bit line driver 22 via data bus 28 and act as a data input / output (I / O) interface and data buffer to buffer and forward data to and from the memory cell array.

[0088] Exemplarily, the three-dimensional memory 1 includes a three-dimensional NAND-type memory structure. The memory string includes a channel layer, a tunneling layer, a charge trapping layer, and a barrier layer arranged sequentially. Word lines are disposed outside the barrier layer.

[0089] like Figure 10 As shown, this disclosure also provides a storage system 30, including at least one three-dimensional memory 20, a controller 3, and a connector 4. The connector 4 is used to couple the storage system 30 to an external device.

[0090] This disclosure provides a three-dimensional memory 20, which includes the aforementioned memory cell array and peripheral circuitry. The peripheral circuitry is electrically connected to the memory cell array, and the two are stacked or arranged in parallel. They can be bonded or electrically connected using other methods. The peripheral circuitry may include, for example, page buffers / sensor amplifiers, column decoders / bit line (BL) drivers, row decoders / word line (WL) drivers, voltage generators, control logic units, registers, interfaces, and data buses.

[0091] Exemplarily, the controller 3 and at least one three-dimensional memory 20 can be integrated into a memory card. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, eMMC), an SD card (SD, miniSD, microSD, SDHC), a universal flash memory card (UFS), etc. Exemplarily, the controller 3 and at least one three-dimensional memory 20 can be integrated into a solid-state drive (SSD).

[0092] The three-dimensional memory or storage system disclosed herein achieves reliable programming processing of the three-dimensional memory by limiting the peripheral circuitry, thereby improving the reliability of the stored data. This three-dimensional memory or storage system can stably and persistently provide good storage capacity.

[0093] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the described technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions in this disclosure.

Claims

1. A programming method for a three-dimensional memory, the three-dimensional memory comprising a first storage string, the first storage string comprising a plurality of storage cells, Its features are, The programming method includes: In response to the fact that the first end storage cell in the plurality of storage cells is to store data and the first adjacent storage cell adjacent to the first end storage cell is empty, a first programming voltage is applied to the first end storage cell and the first adjacent storage cell. The first adjacent storage unit is a non-virtual storage unit.

2. The programming method according to claim 1, wherein, The first programming voltage is applied synchronously to the first end memory cell and the first adjacent memory cell.

3. The programming method according to claim 2 further includes: A first verification voltage is applied to the first end memory cell and the first adjacent memory cell.

4. The programming method according to any one of claims 1-3, wherein, The three-dimensional memory further includes a second memory string arranged in parallel with the first memory string to form a memory cell array, and the programming method further includes: In response to data to be stored in the second end storage cell of the plurality of storage cells in the second storage string, and a second adjacent storage cell in the second storage string adjacent to the second end storage cell being vacant, a second programming voltage is applied to the second end storage cell; and The second programming voltage is applied to the second adjacent memory cell, wherein the second end memory cell and the first end memory cell are located in different rows in the memory cell array.

5. The programming method according to claim 4, wherein, The programming method also includes: A second verification voltage is applied to the second end memory cell and the second adjacent memory cell.

6. The programming method according to claim 5, wherein, The programming method is performed on the storage cells of the storage cell array in a manner that programs along the column direction of the storage cell array.

7. A three-dimensional memory, characterized in that, include: The first storage string includes multiple storage units; as well as The peripheral circuitry is configured as follows: In response to the fact that the first end storage cell in the plurality of storage cells is to store data and the first adjacent storage cell adjacent to the first end storage cell is vacant, a first programming voltage is applied to the first end storage cell. as well as The first programming voltage is applied to the first adjacent memory cell, wherein the first adjacent memory cell is a non-virtual memory cell.

8. The three-dimensional memory according to claim 7, wherein, The peripheral circuitry is configured to synchronously apply the first programming voltage to the first end memory cell and the first adjacent memory cell.

9. The three-dimensional memory according to claim 8, wherein, The peripheral circuit is also configured to apply a first verification voltage to the first adjacent memory cell and the first end memory cell.

10. The three-dimensional memory according to any one of claims 7-9, wherein, The three-dimensional memory further includes a second memory string arranged in parallel with the first memory string to form a memory cell array, and the peripheral circuitry is further configured as follows: In response to the second end storage cell in the second storage string having data to be stored and the second adjacent storage cell in the second storage string being vacant, a second programming voltage is applied to the second end storage cell; as well as The second programming voltage is applied to the second adjacent memory cell, wherein the second end memory cell and the first end memory cell are located in different rows in the memory cell array.

11. The three-dimensional memory according to claim 10, wherein, The peripheral circuit is also configured to apply a second verification voltage to the second adjacent memory and the second end memory cell.

12. The three-dimensional memory according to claim 11, wherein, The peripheral circuitry is also configured to program the memory cells of the memory cell array in a manner that follows the column-wise programming sequence of the memory cell array.

13. The three-dimensional memory according to claim 7, wherein, The three-dimensional memory further includes a second memory string arranged parallel to the first memory string to form a memory cell array, the three-dimensional memory including a three-dimensional NAND-type memory structure; and The first memory string and the second memory string each include a channel layer, a tunneling layer, a charge trapping layer and a blocking layer arranged in sequence, and the word lines connected to each row of memory cells in the memory cell array are disposed outside the blocking layer.

14. A storage system, characterized in that, include: The three-dimensional memory as described in any one of claims 7 to 13; as well as A controller is electrically connected to the three-dimensional memory and is used to control the three-dimensional memory.

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