Light-emitting diode with improved fracture and preparation method thereof

Abstract

The present disclosure provides a light-emitting diode with improved fracture resistance and a method for preparing the same, belonging to the field of optoelectronic manufacturing technology. The light-emitting diode comprises: a substrate, an epitaxial layer, a passivation layer, and at least two solder blocks; the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer sequentially stacked on the substrate, the passivation layer is located on the second semiconductor layer, and the surface of the passivation layer away from the substrate has a first via and a plurality of second vias; the solder blocks are located on the surface of the passivation layer away from the substrate, one solder block is connected to the second semiconductor layer via the first via, and at least one solder block is connected to the first semiconductor layer via the second via. The embodiments of the present disclosure can improve the problem of easy fracture due to poor strength of the epitaxial layer.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode with improved fracture resistance and a preparation method thereof. Background Art

[0002] Micro LEDs (Micro Light Emitting Diodes) refer to ultra-small light-emitting diodes with side lengths ranging from 10μm to 100μm. Due to their small size, micro LEDs can be arranged more densely, significantly improving resolution. They also have self-luminous properties, and have the characteristics of high brightness, high contrast, high responsiveness, and energy saving.

[0003] In related technologies, a light-emitting diode typically includes a substrate, an epitaxial layer, and two electrodes. The epitaxial layer includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer, stacked sequentially on the substrate. One electrode is located on and electrically connected to the second semiconductor layer. The second semiconductor layer also has a recess that exposes the first semiconductor layer. The other electrode is located within the recess and electrically connected to the first semiconductor layer.

[0004] After the grooves are provided on the epitaxial layer, steep steps are formed on the epitaxial layer, which causes stress concentration problems. In addition, the strength of the region where the grooves are provided on the epitaxial layer is also low, making it prone to fracture. Summary of the Invention

[0005] The present disclosure provides a light-emitting diode with improved fracture resistance and a method for manufacturing the same, which can improve the problem of poor epitaxial layer strength and easy fracture. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode with improved current conduction, the light-emitting diode comprising: a substrate, an epitaxial layer, a passivation layer and at least two solder blocks; the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer stacked in sequence on the substrate, the passivation layer is located on the second semiconductor layer, and the surface of the passivation layer away from the substrate has a first via and multiple second vias; the solder blocks are located on the surface of the passivation layer away from the substrate, one solder block is connected to the second semiconductor layer through the first via, and at least one solder block is connected to the first semiconductor layer through the second via.

[0007] Optionally, a plurality of the second via holes are distributed along an edge of the epitaxial layer.

[0008] Optionally, the orthographic projection of the epitaxial layer on the substrate is a rectangle, and some of the second vias are located at corners of the rectangle.

[0009] Optionally, the aperture of the second via hole located at the corner of the rectangle is larger than the aperture of the second via hole located at the side of the rectangle.

[0010] Optionally, a diameter of an end of the second via hole close to the substrate is smaller than a diameter of an end of the second via hole away from the substrate.

[0011] Optionally, in the direction of the long side of the rectangle, the inclination angle of the hole wall of the axial cross section of the second via hole is smaller than the inclination angle of the hole wall of the axial cross section of the second via hole in the direction of the short side of the rectangle.

[0012] Optionally, the solder joint block includes a Cr layer, a first Al layer, a first Ti layer, a second Al layer, a second Ti layer and an Au layer stacked in sequence.

[0013] Optionally, the epitaxial layer further includes a transparent conductive layer, which is located between the second semiconductor layer and the passivation layer. The first via is opposite to the transparent conductive layer, and the orthographic projection of the second via on the substrate is outside the orthographic projection of the transparent conductive layer on the substrate.

[0014] On the other hand, an embodiment of the present disclosure also provides a method for preparing a light-emitting diode with improved fracture, the preparation method comprising: providing a substrate; forming an epitaxial layer and a passivation layer on the substrate, the epitaxial layer comprising a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence on the substrate, the passivation layer being located on the second semiconductor layer, and the surface of the passivation layer away from the substrate having a first via and a plurality of second vias; making at least two solder blocks on the surface of the passivation layer away from the substrate, one of the solder blocks being connected to the second semiconductor layer through the first via, and at least one of the solder blocks being connected to the first semiconductor layer through the second via.

[0015] Optionally, forming the second via on the epitaxial layer includes: forming a photoresist layer on the surface of the passivation layer, the photoresist layer having first through holes corresponding one-to-one to the second through holes, and the distance between the hole wall of the first through hole and the center line of the first through hole gradually decreases from the surface of the photoresist layer away from the epitaxial layer to the surface of the photoresist layer close to the epitaxial layer; and etching the second via on the epitaxial layer through the first through hole of the photoresist layer.

[0016] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0017] The light-emitting diode provided by the embodiments of the present disclosure includes an epitaxial layer stacked on a substrate. The epitaxial layer includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence. A passivation layer is located on the second semiconductor layer. The surface of the passivation layer has a first via and a second via. The first via penetrates the passivation layer to expose the second semiconductor layer, and the second via penetrates the passivation layer, the second semiconductor layer, and the multi-quantum well layer to expose the first semiconductor layer. In this way, two solder joints on the passivation layer can be connected to the corresponding semiconductor layer in the epitaxial layer through the two vias, respectively.

[0018] Compared to related art, the light-emitting diode does not have grooves in the epitaxial layer. Instead, it uses secondary vias to connect the solder joints to the semiconductor layer below the epitaxial layer. This means that the epitaxial layer thickness is not reduced, thus ensuring its strength and avoiding stress concentration at the steps of the grooves after the grooves are created, thereby improving the problem of epitaxial wafer fracturing. Furthermore, the multiple secondary vias are dispersed, thus optimizing the problem of concentrated stress on the chip after the grooves are created in related art. This is achieved by distributing the stress at the locations of the secondary vias, achieving the goal of distributing the stress, improving the strength of the epitaxial layer, and further improving the problem of epitaxial wafer fracturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 This is a structural diagram of a light emitting diode provided by the related art;

[0021] Figure 2 is a top view of a light emitting diode provided by an embodiment of the present disclosure;

[0022] Figure 3 yes Figure 2 An AA cross-sectional view is provided;

[0023] Figure 4 is a schematic structural diagram of a second via provided in an embodiment of the present disclosure;

[0024] Figure 5 yes Figure 4 A BB cross-section diagram is provided;

[0025] Figure 6 yes Figure 4 A CC cross-section diagram is provided;

[0026] Figure 7is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure;

[0027] Figure 8 This is a schematic diagram of a process for preparing a light-emitting diode provided by an embodiment of the present disclosure;

[0028] Figure 9 This is a schematic diagram of a process for preparing a light-emitting diode provided in an embodiment of the present disclosure.

[0029] The descriptions of the marks in the figure are as follows:

[0030] 10. Substrate;

[0031] 20. epitaxial layer; 21. first semiconductor layer; 22. multi-quantum well layer; 23. second semiconductor layer; 24. passivation layer; 25. transparent conductive layer; 201. first via hole; 202. second via hole;

[0032] 30. Solder block; 31. Electrode;

[0033] 50. Photoresist layer; 51. First through hole; 52. Second through hole;

[0034] 60. Protective layer;

[0035] 70. groove;

[0036] 8. Mask plate; 80. Quartz plate; 81. First photolithography hole; 82. Second photolithography hole; 83. Chrome layer. DETAILED DESCRIPTION

[0037] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0038] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar words used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprise" mean that the elements or objects preceding "include" or "comprises" encompass the elements or objects listed after "include" or "comprises," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0039] Figure 1 This is a schematic diagram of the structure of a light emitting diode provided by the related technology. Figure 1 As shown, the light-emitting diode includes a substrate 10, an epitaxial layer 20, and two electrodes 31. The epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 stacked in sequence on the substrate 10. One electrode 31 is located on the second semiconductor layer 23 and is electrically connected to the second semiconductor layer 23. The second semiconductor layer 23 is also provided with a groove 70 that exposes the first semiconductor layer 21. The other electrode 31 is located in the groove 70 and is electrically connected to the first semiconductor layer 21.

[0040] like Figure 1 As shown, after the groove 70 is opened on the epitaxial layer 20, the thickness of the epitaxial layer 20 is thinned to a certain extent, resulting in a decrease in the strength of the epitaxial layer 20; and the groove 70 forms a relatively steep step on the epitaxial layer 20, which will cause stress concentration problems and make the chip easy to break.

[0041] Figure 2 This is a top view of a light emitting diode provided by an embodiment of the present disclosure. Figure 3 yes Figure 2 An AA cross-section diagram is provided. Figure 2 The light emitting diode shown in FIG. 3 is not provided with the soldering point block 30 . Figure 3 yes Figure 2 Cross-section view at section line AA.

[0042] like Figure 3As shown, the light-emitting diode includes: a substrate 10, an epitaxial layer 20, a passivation layer 24 and at least two solder blocks 30; the epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 stacked in sequence on the substrate 10, the passivation layer 24 is located on the second semiconductor layer 23, and the surface of the passivation layer 24 away from the substrate 10 has a first via 201 and a plurality of second vias 202, the first via 201 exposes the second semiconductor layer 23, the second via 202 exposes the first semiconductor layer 21, and the plurality of second vias 202 are distributed at intervals.

[0043] like Figure 3 As shown, the soldering blocks 30 are located on the surface of the passivation layer 24 away from the substrate 10 . One soldering block 30 is connected to the second semiconductor layer 23 through the first via 201 , and the other soldering block 30 is connected to the first semiconductor layer 21 through the second via 202 .

[0044] The light-emitting diode provided by the embodiment of the present disclosure includes an epitaxial layer 20 stacked on a substrate 10. The epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 stacked in sequence. A passivation layer 24 is located on the second semiconductor layer 23. The surface of the passivation layer 24 has a first via 201 and a second via 202. The first via 201 penetrates the passivation layer 24 to expose the second semiconductor layer 23, and the second via 202 penetrates the passivation layer 24, the second semiconductor layer 23, and the multi-quantum well layer 22 to expose the first semiconductor layer 21. In this way, the two solder joints 30 on the passivation layer 24 can be connected to the corresponding semiconductor layer in the epitaxial layer 20 through the two vias, respectively.

[0045] Compared to the related art, the light-emitting diode does not have grooves 70 formed in the epitaxial layer 20. Instead, second vias 202 are formed to connect the solder joint block 30 to the semiconductor layer located below the epitaxial layer 20. This means that the thickness of the epitaxial layer 20 is not reduced, thereby ensuring the strength of the epitaxial layer 20 and avoiding the stress concentration problem at the step of the groove 70 after the groove 70 is formed, thereby improving the problem of the epitaxial wafer being prone to fracture. In addition, multiple second vias 202 are dispersed. This optimizes the problem of relatively concentrated stress on the chip after the groove is formed in the related art to stress being applied at the locations of each second via 202, achieving the purpose of dispersing the stress, improving the strength of the epitaxial layer 20, and further improving the problem of the epitaxial wafer being prone to fracture.

[0046] Optionally, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate 10. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.

[0047] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0048] Exemplarily, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0049] Optionally, the first semiconductor layer 21 is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0050] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers, wherein the multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0051] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0052] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0053] Optionally, the second semiconductor layer 23 is a magnesium-doped p-type GaN layer, and the thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0054] Alternatively, as Figure 3 As shown, the passivation layer 24 can be a distributed Bragg reflector (DBR layer), which includes multiple periodic alternating layers of SiO2 and TiO2. The number of periods in the DBR layer can be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0055] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0056] In addition to the passivation function, the DBR layer is also used to reflect the light emitted from the multi-quantum well layer 22 to the DBR layer to the substrate 10, thereby improving the light extraction effect.

[0057] Optionally, the two soldering blocks 30 are both rectangular blocks to increase the area and facilitate electrical conduction. Furthermore, the two soldering blocks 30 are spaced apart on the surface of the passivation layer 24 .

[0058] Alternatively, as Figure 3As shown, a protective layer 60 is further provided on the surface of the passivation layer 24 , and the protective layer 60 extends from the surface of the passivation layer 24 to the substrate 10 , and the protective layer 60 has a through hole exposing the soldering block 30 for electrical connection.

[0059] For example, in the embodiment of the present disclosure, the protective layer 60 may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.

[0060] Alternatively, as Figure 2 As shown, a plurality of second via holes 202 are distributed along the edge of the epitaxial layer 20 .

[0061] The edge of the epitaxial layer 20 refers to the outer contour of the orthographic projection of the epitaxial layer 20 on the substrate 10 .

[0062] For example, the outer contour of the orthographic projection of the epitaxial layer 20 on the substrate 10 is a rectangle, and the edges of the epitaxial layer 20 are the positions of the corners and the sides of the rectangle.

[0063] Since the edge of the chip is more difficult to break than the central area, the second via 202 is set at the edge of the epitaxial layer 20 to distribute the stress of the chip at the edge of the chip, thereby effectively preventing the central area of ​​the chip from being subjected to greater stress, thereby reducing the problem of breakage.

[0064] Alternatively, as Figure 2 As shown, the orthographic projection of the epitaxial layer 20 on the substrate 10 is a rectangle, and some of the second via holes 202 are located at the corners of the rectangle.

[0065] For the edge of the chip, since the corner area is more difficult to break than the side area, some second vias are set at the corners of the rectangle to avoid setting more second vias at other positions of the chip and weakening the strength of the chip.

[0066] Alternatively, as Figure 2 As shown, some second via holes 202 are located on the sides of the rectangle on the epitaxial layer. The distribution density of the second via holes 202 located at the corners of the rectangle is higher than the distribution density of the second via holes 202 located at the sides of the rectangle.

[0067] The distribution density is the number of second via holes 202 distributed per unit area. A higher distribution density indicates that the number of second via holes 202 distributed per unit area is greater, and the distribution of the second via holes 202 is denser.

[0068] By arranging more second via holes 202 in the corner areas and arranging a smaller number of second via holes 202 in the side areas, the problem of chip breakage can be further effectively avoided.

[0069] Alternatively, as Figure 2As shown, the aperture of the second via hole 202 located at the corner of the rectangle is larger than the aperture of the second via hole 202 located at the side of the rectangle.

[0070] Since the corner area is more difficult to break than the side area, the second via 202 with a larger aperture is set in the corner area so that the corner area bears greater stress, and the second via 202 with a smaller aperture is set in the side area so that the side area bears less stress, which can further effectively avoid the problem of chip breakage.

[0071] Furthermore, by providing some second via holes 202 with larger apertures, it is possible to enhance the ohmic contact between the soldering block 30 and the first semiconductor layer 21 .

[0072] Alternatively, as Figure 3 As shown, the aperture of the second via hole 202 at one end close to the substrate 10 is smaller than the aperture of the second via hole 202 at one end away from the substrate 10 .

[0073] In the disclosed embodiment, the apertures of the second via hole 202 are different at both ends, so that the hole wall of the second via hole 202 is inclined relative to the central axis of the second via hole 202. Compared with a hole wall perpendicular to the substrate 10, the inclined hole wall can effectively prevent stress accumulation, thereby reducing stress concentration and improving the problem of easy chip breakage.

[0074] Figure 4 2 is a schematic structural diagram of a second via hole 202 provided in an embodiment of the present disclosure. Figure 5 yes Figure 4 A BB cross-section diagram is provided. Figure 6 yes Figure 4 A CC cross-section diagram is provided. Figure 5 、 6 As shown, the inclination angle α of the hole wall of the axial section of the second via 202 in the direction of the long side of the rectangle (see the X direction in the figure) is smaller than the inclination angle β of the hole wall of the axial section of the second via 202 in the direction of the short side of the rectangle (see the Y direction in the figure).

[0075] In the embodiment of the present disclosure, the soldering blocks 30 are arranged along the long side direction of the chip, that is, the arrangement direction of the soldering blocks 30 is the long side direction of the chip.

[0076] The inclination angle of the second via hole 202's wall in the axial cross-section along the chip's long side is smaller than the inclination angle of the second via hole 202's wall in the axial cross-section along the chip's short side. That is, the wall of the second via hole 202 is more gently sloped along the chip's long side, while it is steeper along the chip's short side. Because chips are more susceptible to fracture along their long sides, making the wall of the second via hole 202 more gently sloped along their long sides can further alleviate stress concentration, reducing stress on the chip along its long sides and effectively preventing chip fracture.

[0077] Optionally, the solder bump 30 includes a Cr layer, a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked in sequence.

[0078] Compared to related technologies, the LED eliminates electrodes and connects directly to the semiconductor layer via solder bumps 30. To improve the reliability of the connection between solder bumps 30 and the semiconductor layer, a Cr layer is provided at the end of solder bumps 30 that contacts the semiconductor layer. Because metallic chromium has excellent current conductivity, it forms a good ohmic contact between solder bumps 30 and the semiconductor layer.

[0079] Illustratively, the thickness of the Cr layer is 100 Å to 500 Å, the thickness of the first Al layer is 8,000 Å to 12,000 Å, the thickness of the first Ti layer is 100 Å to 500 Å, the thickness of the second Al layer is 8,000 Å to 12,000 Å, the thickness of the second Ti layer is 500 Å to 1,500 Å, and the thickness of the Au layer is 2,000 Å to 5,000 Å.

[0080] For example, the thickness of the Cr layer is 200 angstroms, the thickness of the first Al layer is 10,000 angstroms, the thickness of the first Ti layer is 200 angstroms, the thickness of the second Al layer is 10,000 angstroms, the thickness of the second Ti layer is 1,000 angstroms, and the thickness of the Au layer is 3,000 angstroms.

[0081] Alternatively, as Figure 3 As shown, the epitaxial layer 20 further includes a transparent conductive layer 25 , which is located between the second semiconductor layer 23 and the passivation layer 24 . The first via 201 is opposite to the transparent conductive layer 25 , and the orthographic projection of the second via 202 on the substrate 10 is located outside the orthographic projection of the transparent conductive layer 25 on the substrate 10 .

[0082] Optionally, the transparent conductive layer 25 may be an indium tin oxide (ITO) film. ITO films have good transmittance and low resistivity. Using ITO as the transparent conductive layer 25 allows more light to be transmitted through the transparent conductive layer 25, thereby ensuring the desired effect. Furthermore, due to its low resistivity, it facilitates carrier conduction and improves injection efficiency.

[0083] Exemplarily, the thickness of the transparent conductive layer 25 may be 800 angstroms to 1200 angstroms.

[0084] In the embodiment of the present disclosure, since only one first via hole 201 is provided, the carrier conduction efficiency between the solder joint block 30 and the second semiconductor layer 23 can be improved by providing a transparent conductive layer 25 between the first via hole 201 and the second semiconductor layer 23 .

[0085] Figure 7 This is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure. Figure 3 As shown in the light emitting diode. Figure 7 As shown, the preparation method comprises:

[0086] S11: providing a substrate 10.

[0087] S12 : forming an epitaxial layer 20 and a passivation layer on the substrate 10 .

[0088] Among them, the epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 stacked in sequence on the substrate 10, the passivation layer 24 is located on the second semiconductor layer 23, and the surface of the passivation layer 24 away from the substrate 10 has a first via 201 and multiple second vias 202, the first via 201 exposes the second semiconductor layer 23, the second via 202 exposes the first semiconductor layer 21, and the multiple second vias 202 are distributed at intervals.

[0089] S13 : forming at least two solder bumps 30 on the surface of the passivation layer 24 away from the substrate 10 .

[0090] One soldering point block 30 is connected to the second semiconductor layer 23 through the first via hole 201 , and at least one soldering point block 30 is connected to the first semiconductor layer 21 through the second via hole 202 .

[0091] The light-emitting diode fabricated by this method includes an epitaxial layer 20 stacked on a substrate 10. The epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 stacked in sequence. A passivation layer 24 is located on the second semiconductor layer 23. The surface of the passivation layer 24 has a first via 201 and a second via 202. The first via 201 penetrates the passivation layer 24 to expose the second semiconductor layer 23, and the second via 202 penetrates the passivation layer 24, the second semiconductor layer 23, and the multi-quantum well layer 22 to expose the first semiconductor layer 21. In this way, two solder joints 30 on the passivation layer 24 can be connected to the corresponding semiconductor layer in the epitaxial layer 20 through the two vias, respectively. Compared to the related art, the light-emitting diode does not have grooves 70 formed in the epitaxial layer 20. Instead, second vias 202 are formed to connect the solder joint block 30 to the semiconductor layer located below the epitaxial layer 20. This means that the thickness of the epitaxial layer 20 is not reduced, thereby ensuring the strength of the epitaxial layer 20 and avoiding the stress concentration problem at the step of the groove 70 after the groove 70 is formed, thereby improving the problem of the epitaxial wafer being prone to fracture. In addition, multiple second vias 202 are dispersed. This optimizes the problem of relatively concentrated stress on the chip after the groove is formed in the related art to stress being applied at the locations of each second via 202, achieving the purpose of dispersing the stress, improving the strength of the epitaxial layer 20, and further improving the problem of the epitaxial wafer being prone to fracture.

[0092] In step S11, the substrate 10 is a sapphire substrate, a silicon substrate or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0093] As an example, in the embodiment of the present disclosure, the substrate 10 is a sapphire substrate. Sapphire substrate is a commonly used substrate with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a sapphire flat sheet substrate.

[0094] The sapphire substrate may be pre-treated by placing the sapphire substrate in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking the sapphire substrate for 12 to 18 minutes. For example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0095] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0096] Figure 8 FIG. 1 is a schematic diagram of a process for preparing a light emitting diode according to an embodiment of the present disclosure. Figure 8As shown, growing the epitaxial layer 20 on the substrate 10 in step S12 may include: sequentially forming a first semiconductor layer 21 , a multi-quantum well layer 22 , a second semiconductor layer 23 and a passivation layer 24 on the sapphire substrate by MOCVD technology.

[0097] The first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0098] Optionally, the first semiconductor layer 21 is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0099] The growth temperature of the n-type GaN layer may be 1000° C. to 1100° C., and the growth pressure of the n-type GaN layer may be 100 Torr to 300 Torr.

[0100] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers, wherein the multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0101] When growing the multi-quantum well layer 22, the pressure of the MOCVD reaction chamber is controlled at 200 Torr. When growing the InGaN quantum well layer, the reaction chamber temperature is 760°C to 780°C. When growing the GaN quantum barrier layer, the reaction chamber temperature is 860°C to 890°C.

[0102] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0103] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0104] Optionally, the second semiconductor layer 23 is a magnesium-doped p-type GaN layer, and the thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0105] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer may be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer may be 800° C. to 1000° C.

[0106] Before forming the passivation layer 24 in step S12 , the step may include: forming a transparent conductive layer 25 on the surface of the second semiconductor layer 23 .

[0107] Exemplarily, the thickness of the transparent conductive layer 25 may be 800 angstroms to 1200 angstroms.

[0108] Alternatively, the passivation layer 24 may be a DBR layer, which includes a plurality of SiO2 layers and TiO2 layers periodically and alternately stacked. The number of periods of the DBR layer may be between 20 and 50. For example, the number of periods of the DBR layer is 32.

[0109] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0110] After the passivation layer 24 is formed in step S12 , it is necessary to further etch the surface of the passivation layer 24 to form the first via hole 201 and the second via hole 202 .

[0111] The preparation method for forming the first via hole 201 and the second via hole 202 may include the following steps:

[0112] In the first step, a photoresist layer 50 is formed on the surface of the passivation layer 24 .

[0113] like Figure 9 As shown, a photoresist film is first formed on the surface of the passivation layer 24 , and then the photoresist film is photoetched using a mask plate 8 to form a photoresist layer 50 .

[0114] like Figure 9 As shown, the photoresist layer 50 has a first through hole 51 corresponding one-to-one to the second via hole 202. From the surface of the photoresist layer away from the epitaxial layer to the surface of the photoresist layer close to the epitaxial layer, the distance between the hole wall of the first through hole 51 and the center line of the first through hole 51 gradually decreases. The first through hole 51 is used to etch to form the second via hole 202.

[0115] Among them, the mask plate 8 includes a chromium layer 83 and a quartz plate 80 stacked in sequence. The chromium layer 83 has first photolithography holes 81 corresponding one-to-one to the first through holes 51. From the top surface of the chromium layer 83 to the bottom surface of the chromium layer 83, the distance from the center line of the first photolithography hole 81 to the inner wall of the first photolithography hole 81 gradually increases, that is, the cross-section of the first photolithography hole 81 is trapezoidal.

[0116] like Figure 9 As shown, the photoresist layer 50 further has a second through hole 52 , which is a circular hole and is used for etching to form the first via hole 201 .

[0117] The chromium layer 83 further has second photolithography holes 82 corresponding one-to-one to the second through holes 52 .

[0118] Since the thicker the chromium layer, the more significant its light-blocking effect, in the region of the photoresist film opposite the first photolithographic hole 81, the thicker the chromium layer 83, the less material is etched from the photoresist film, while the thinner the chromium layer 83, the greater the extent of the etching. Therefore, the chromium layer 83 can form a first through hole 51 in the photoresist film, with the hole wall inclined relative to the central axis of the first through hole 51.

[0119] In the second step, the first through hole 51 and the second through hole 52 of the photoresist layer 50 are etched on the surface of the passivation layer to form the first through hole 201 and the second through hole 202 .

[0120] In S13, making at least two solder blocks 30 on the surface of the passivation layer 24 may include: forming at least two solder blocks 30 by photolithography, one solder block 30 is connected to the transparent conductive layer 25 through the first via 201, and at least one solder block 30 is connected to the first semiconductor layer 21 through each second via 202.

[0121] In the embodiment of the present disclosure, the solder joint block 30 includes a Cr layer, a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked in sequence.

[0122] Illustratively, the thickness of the Cr layer is 100 Å to 500 Å, the thickness of the first Al layer is 8,000 Å to 12,000 Å, the thickness of the first Ti layer is 100 Å to 500 Å, the thickness of the second Al layer is 8,000 Å to 12,000 Å, the thickness of the second Ti layer is 500 Å to 1,500 Å, and the thickness of the Au layer is 2,000 Å to 5,000 Å.

[0123] For example, the thickness of the Cr layer is 200 angstroms, the thickness of the first Al layer is 10,000 angstroms, the thickness of the first Ti layer is 200 angstroms, the thickness of the second Al layer is 10,000 angstroms, the thickness of the second Ti layer is 1,000 angstroms, and the thickness of the Au layer is 3,000 angstroms.

[0124] In the embodiment of the present disclosure, after manufacturing the solder joint block 30 , the preparation method may further include: manufacturing a protective layer 60 on the surface of the passivation layer 24 .

[0125] For example, in the embodiment of the present disclosure, the protective layer 60 may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.

[0126] It should be noted that after the protective layer 60 is grown on the surface of the passivation layer 24 , a photolithography technique may be used to etch through holes on the surface of the protective layer 60 to expose the soldering blocks 30 , so as to facilitate electrical connection.

[0127] Finally, the sapphire can be invisible cut and scratched, which can effectively reduce the loss of brightness. Then, the light-emitting diode is tested.

[0128] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light-emitting diode comprises: a substrate (10), an epitaxial layer (20), a passivation layer (24), and at least two solder joint blocks (30); The epitaxial layer (20) comprises a first semiconductor layer (21), a multi-quantum well layer (22), and a second semiconductor layer (23) sequentially stacked on the substrate (10); a surface of the epitaxial layer (20) away from the substrate (10) has no steps; the passivation layer (24) is located on the second semiconductor layer (23); and a surface of the passivation layer (24) away from the substrate (10) has a first via hole (201) and a plurality of second via holes (202); The soldering point block (30) is located on the surface of the passivation layer (24) away from the substrate (10), one of the soldering point blocks (30) is connected to the second semiconductor layer (23) through the first via hole (201), and at least one of the soldering point blocks (30) is connected to the first semiconductor layer (21) through the second via hole (202), and a plurality of the second via holes (202) are distributed along the edge of the epitaxial layer (20), and the positive projection of the epitaxial layer (20) on the substrate (10) is a rectangle, and some of the second via holes (202) are located at the corners of the rectangle, and the aperture of the second via holes (202) located at the corners of the rectangle is larger than the aperture of the second via holes (202) located at the side of the rectangle.

2. The light emitting diode according to claim 1, characterized in that The aperture of the second via hole (202) at one end close to the substrate (10) is smaller than the aperture of the second via hole (202) at one end away from the substrate (10).

3. The light emitting diode according to claim 2, characterized in that In the direction of the long side of the rectangle, the inclination angle of the hole wall of the axial section of the second via hole (202) is smaller than the inclination angle of the hole wall of the axial section of the second via hole (202) in the direction of the short side of the rectangle.

4. The light emitting diode according to any one of claims 1 to 3, characterized in that: The soldering point block (30) comprises a Cr layer, a first Al layer, a first Ti layer, a second Al layer, a second Ti layer and an Au layer stacked in sequence.

5. The light emitting diode according to any one of claims 1 to 3, characterized in that: The epitaxial layer (20) further comprises a transparent conductive layer (25), wherein the transparent conductive layer (25) is located between the second semiconductor layer (23) and the passivation layer (24), the first via hole (201) is opposite to the transparent conductive layer (25), and the orthographic projection of the second via hole (202) on the substrate (10) is located outside the orthographic projection of the transparent conductive layer (25) on the substrate (10).

6. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: providing a substrate; forming an epitaxial layer and a passivation layer on the substrate, wherein the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer sequentially stacked on the substrate, wherein a surface of the epitaxial layer away from the substrate has no steps, the passivation layer is located on the second semiconductor layer, and a surface of the passivation layer away from the substrate has a first via hole and a plurality of second via holes; At least two solder joints are made on the surface of the passivation layer away from the substrate, one of the solder joints is connected to the second semiconductor layer through the first via, and at least one of the solder joints is connected to the first semiconductor layer through the second via. Multiple second vias are distributed along the edge of the epitaxial layer, and the positive projection of the epitaxial layer on the substrate is a rectangle. Some of the second vias are located at the corners of the rectangle, and the aperture of the second vias located at the corners of the rectangle is larger than the aperture of the second vias located at the sides of the rectangle.

7. The preparation method according to claim 6, characterized in that Forming the second via hole on the epitaxial layer includes: forming a photoresist layer on a surface of the passivation layer, the photoresist layer having first through holes corresponding one-to-one to the second via holes, and a distance between a hole wall of the first through hole and a center line of the first through hole gradually decreasing from a surface of the photoresist layer away from the epitaxial layer to a surface of the photoresist layer close to the epitaxial layer; The second via hole is formed by etching the epitaxial layer through the first through hole of the photoresist layer.

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