Dual-channel independent automatic identification battery load boost-buck circuit

Abstract

The application discloses a double-channel independent automatic identification battery load step-up and step-down circuit, which comprises a low step-up and step-down control chip, an energy storage inductor, a rechargeable battery, a first battery load and a second battery load; the step-up and step-down control chip comprises a step-up and step-down control module, a load detection module, a step-up bypass capacitor, a first detection resistor and a second detection resistor, an output port VOUT1, an output port VOUT2, a first detection port VEND1, a second detection port VEND2 and a ground terminal GND; the rechargeable battery is connected between the port BAT and the ground terminal GND; the first battery load is connected between the output port VOUT1 and the ground terminal GND; the second battery load is connected between the output port VOUT2 and the ground terminal GND; the first detection resistor is connected between the first detection port VEND1 and the ground terminal GND; and the second detection resistor is connected between the second detection port VEND2 and the ground terminal GND. Therefore, the application realizes independent automatic identification of double-channel battery loads and three-stage charging management by adding the load detection module to detect the voltage of the output port and the detection port.

Description

Technical Field

[0001] This invention belongs to the field of power supply circuit design technology, and relates to a dual-channel independent automatic identification of battery load buck-boost circuit. Background Technology

[0002] With the continuous development of integrated circuit technology, step-up and step-down DC-DC power management products have been widely developed and applied, realizing high-efficiency DC-to-DC power conversion and applicable to various electronic product usage environments and occasions.

[0003] Please see Figure 1 , Figure 1 The diagram shown is a connection schematic of a buck-boost DC-DC converter circuit in the prior art. Figure 1 As shown, the control chip 212 has five ports: VIN, LX, BAT, VOUT1, and ground GND. The positive terminal of input capacitor 102 and the USB power port are connected to port VIN, while the negative terminal of input capacitor 102 is grounded. Energy storage inductor 104 is connected between port LX and port BAT. Battery bypass capacitor 105 is connected between port BAT and ground GND. The positive terminal of rechargeable battery 106 is connected between port BAT and ground GND. Port output capacitor 107 and battery load 108 are connected in parallel between port VOUT1 and ground GND.

[0004] Those skilled in the art will understand that in the above circuit, the DC-DC conversion mode, such as buck or boost DC-DC conversion mode, can be determined by the voltage value of port VIN. Specifically, when selecting the power conversion mode by determining the voltage value of port VIN through port MODE module 401, the following situations can be considered:

[0005] ①. When VIN≥4.7V, the port VIN, the switching PMOS transistor 404, the freewheeling NMOS transistor 405 and the inductor 104 form a synchronous buck architecture, the battery 106 performs switching charging, and at the same time provides power to the battery load at the port VOUT.

[0006] ②. When 4.5 ≤ VIN < 4.7V, the synchronous buck converter does not work, and the VIN port only provides power to the battery load;

[0007] ③. When VIN < 4.5V, the switching NMOS transistor 405, the freewheeling PMOS transistor 404, and the energy storage inductor 104 form a synchronous boost architecture, and the battery 106 discharges to provide power to the battery load 108.

[0008] ④. When the VIN port is floating, the battery load 108 connected to the VOUT port is charged by the synchronous boost formed by the control chip 212 and the energy storage inductor 104.

[0009] As can be seen from the working principle of the above circuit, when the VIN port is floating, if the battery load 108 is being charged, it is impossible to monitor whether the battery load 108 is fully charged. Even if the battery load 108 is fully charged, the synchronous boost will still be in working state. Summary of the Invention

[0010] To address the aforementioned technical problems, this invention proposes a dual-channel independent automatic battery load identification buck-boost circuit, the technical solution of which is as follows:

[0011] A dual-channel independent automatic battery load identification buck-boost circuit includes a buck-boost control chip, an energy storage inductor, a rechargeable battery, a first battery load, and a second battery load. The buck-boost control chip comprises a buck-boost control module, a load detection module, a boost bypass capacitor, a first detection resistor, a second detection resistor, a power port VIN, an inductor port LX, a charging port BAT, a buck-boost port PMID, an output port VOUT1, an output port VOUT2, a first detection port VEND1, a second detection port VEND2, and a ground terminal GND. Port VIN receives the voltage from the power supply. The energy storage inductor is connected between port LX and port BAT. The positive terminal of the rechargeable battery is connected to port BAT, and the negative terminal of the rechargeable battery is connected to ground GND. The first battery load is connected between output port VOUT1 and ground terminal GND, and the second battery load is connected between output port VOUT2 and ground terminal GND. The boost bypass capacitor... A circuit capacitor is connected between the step-up / step-down port PMID and the ground terminal GND; the first sensing resistor is connected between the first sensing port VEND1 and the ground terminal GND, and the second sensing resistor is connected between the second sensing port VEND2 and the ground terminal GND; wherein, the step-up / step-down control module is used to manage and select the power path according to the input voltage of the power port VIN; the load detection module detects the output port VOUT1, the output port VOUT2, the first sensing port VEND1, and the second sensing port VEND2 respectively; when the voltage of the output port VOUT1 is greater than or equal to V11 and less than V12, and the voltage of the first sensing port VEND1 is less than a predetermined threshold V1, the charging of the first battery load ends; or, when the voltage of the output port VOUT2 is greater than or equal to V21 and less than or equal to V22, and the voltage of the second sensing port VEND1 is less than a predetermined threshold V1, the charging of the second battery load ends.

[0012] Furthermore, the load detection module includes a load controller, a first charging channel PMOS transistor, a first charging sampling PMOS transistor, a second charging channel PMOS transistor, and a second charging sampling PMOS transistor; wherein, the load controller outputs different signals VGT1 and VGT2 respectively based on the feedback signals from the output port VOUT1, the first detection port VEND1, the output port VOUT2, and the second detection port VEND2, to control the first charging channel PMOS transistor, the first charging sampling PMOS transistor 503, the second charging channel PMOS transistor, and the second charging sampling PMOS transistor, so as to connect... The battery load connected to output ports VOUT1 and VOUT2 implements three-stage charging; the first stage of charging: when the load detector detects that output port VOUT1 < V13, the PMOS transistor of the first charging channel is in trickle charging mode, and the voltage value of the first detection port VEND1 is V2; when the load detector detects that output port VOUT2 < V23, the PMOS transistor of the first charging channel is in trickle charging mode, and the voltage value of the second detection port VEND1 is V2; wherein, V13 is less than V12, V23 is less than V22, and V2 is greater than V1; the second stage of charging: when When the load detector detects that output port V13 ≤ VOUT1 < V12, the PMOS transistor in the first charging channel is in constant current charging mode, and the voltage value of the first detection port VEND1 is V3; the charging current is 100% of the set value. Similarly, when the load detector detects that output port V23 ≤ VOUT2 < V22, the PMOS transistor in the second charging channel is in constant current charging mode, and the voltage value of the second detection port VEND1 is V3; the charging current is 100% of the set value; where V3 is greater than V2; the third stage of charging: when the load detector detects that output port V12 ≤ VOUT1 < V12... When V1 < V11, the first charging channel PMOS transistor is in constant voltage charging mode, and the charging current decreases linearly with the voltage of the output port VOUT1. Charging ends when the voltage of the first detection port VEND1 is a predetermined threshold V1. Similarly, when the load detector detects that the output port V12 ≤ VOUT1 < V11, the second charging channel PMOS transistor is in constant voltage charging mode, and the charging current decreases linearly with the voltage of the output port VOUT2 until the voltage of the second detection port is a predetermined threshold V1, where V11 is greater than V12, V21 is greater than V22, and V3 is greater than V2.

[0013] Furthermore, V11 and V21 are 4.2 volts; V12 and V22 are 4.05 volts; V13 and V23 are 2.9 volts; V1 is 0.1 volts, V2 is 1 volt, and V3 is 0.2 volts.

[0014] Furthermore, the dual-channel independent automatic battery load identification buck-boost circuit also includes a high-voltage isolation module; the buck-boost control module includes a mode selector, which is used to manage and select the power path according to the input voltage of the power port VIN; when VIN≥V2, a synchronous buck circuit is formed in the circuit containing the energy storage inductor to perform switch-type charging of the rechargeable battery, and at the same time provide power to the load; when V41≤VIN<V42, the synchronous buck circuit does not work, and the power port VIN only provides power to the load. The load provides power; when VIN < V41, a synchronous boost circuit is formed in the circuit containing the energy storage inductor to discharge the rechargeable battery and provide power to the load; wherein, V41 is less than V42, and the operating voltage of the boost / buck control module and the load is V43, which is greater than V42; when VIN ≥ V44 or VIN < V41, the input high-voltage isolation module is used to isolate the power port VIN from the boost / buck control module and the output port VOUT; wherein, V43 < V44.

[0015] Furthermore, the high-voltage isolation module includes an NMOS isolation transistor, a power regulator, and a charge pump; wherein, the drain of the NMOS isolation transistor is connected to the port VIN, its source is connected to the port VOUT, and its gate is connected to the output of the charge pump; the input of the power regulator is connected to the port VIN, and its output supplies power to the charge pump; the input of the charge pump is connected to the output of the power regulator, and its output is connected to the gate of the NMOS isolation transistor.

[0016] Furthermore, the high-voltage isolation module includes a power regulator, a gate-clamped Zener diode, a PMOS isolation transistor, a first substrate switching diode, and a second substrate switching diode; wherein, the source of the PMOS isolation transistor is connected to port VIN, its drain is connected to port VOUT, and its gate is connected to the output node ENB of the power regulator; the input of the power regulator is connected to port VIN, and its output is connected to the output node ENB; the anode of the gate-clamped Zener diode is connected to the output node ENB, and its cathode is connected to the source of the PMOS isolation transistor; the anode of the first substrate switching diode is connected to port VIN, and its cathode is connected to the substrate of the PMOS isolation transistor; the anode of the second substrate switching diode is connected to VOUT, and its cathode is connected to the substrate of the PMOS isolation transistor.

[0017] Furthermore, the buck-boost control module includes a PMOS transistor, an NMOS transistor, a mode selector, a substrate selector, and a buck-boost controller. Specifically: the source of the PMOS transistor is connected to VOUT, its drain is connected to LX, and its gate is connected to the VPG output of the buck-boost controller; the source of the NMOS transistor is connected to ground, its drain is connected to LX, and its gate is connected to the VNG output of the buck-boost controller; the input of the mode selector is connected to VIN, and its output is connected to the VMOD input of the buck-boost controller; the two inputs of the substrate selector are VOUT and BAT, and its output, VSUB, is connected to the input of the buck-boost controller; the four inputs of the buck-boost controller are VOUT, VMOD, VSUB, and BAT, and its two outputs are VPG and VNG.

[0018] Furthermore, V41 is 4.5 volts, V42 is 4.7 volts, V43 is 5 volts and V44 is 6.5 volts.

[0019] Furthermore, the chip with the functional timing circuit also includes an input capacitor and a battery bypass capacitor. The input capacitor is connected between the port VIN and the ground terminal GND; the battery bypass capacitor is connected between the positive terminal of the rechargeable battery and the ground terminal GND.

[0020] Furthermore, the dual-channel independent automatic battery load identification buck-boost circuit also includes a first output capacitor and a second output capacitor. The first output capacitor is connected between the first battery load and the ground terminal GND; the second output capacitor is connected between the second battery load and the ground terminal GND.

[0021] As can be seen from the above technical solution, the present invention provides a dual-channel independent automatic identification of battery load buck-boost circuit based on the above circuit, realizing independent automatic identification of dual-channel battery load and three-stage charging management. Attached Figure Description

[0022] Figure 1 The diagram shown is a connection schematic of a buck-boost DC-DC converter circuit in the prior art.

[0023] Figure 2 The diagram shown is a schematic of a dual-channel independent automatic battery load identification buck-boost circuit in an embodiment of the present invention.

[0024] Figure 3 The diagram shown is a schematic of the dual-channel load detection waveform in an embodiment of the present invention.

[0025] Figure 4 The diagram shown is a schematic of the input high-voltage isolation module in an embodiment of the present invention.

[0026] Figure 5The diagram shown is a schematic representation of power path management in an embodiment of the present invention.

[0027] Component designation explanation

[0028] 101 control chip

[0029] 102 Input capacitor

[0030] 103 Boost bypass capacitor

[0031] 104 Energy Storage Inductor

[0032] 105 Battery Bypass Capacitor

[0033] 106 rechargeable batteries

[0034] 107 First output capacitor

[0035] 108 First Battery Load

[0036] 109 First detection resistor

[0037] 110 Second output capacitor

[0038] 111 Second Battery Load

[0039] 112 Second detection resistor

[0040] 201 High Voltage Isolation Module

[0041] 202 Buck-Boost Control Module

[0042] 203 Load Detection Module

[0043] 501 Load Controller

[0044] 502 First charging channel PMOS transistor

[0045] 503 First charging sampling PMOS transistor

[0046] 504 Second charging channel PMOS transistor

[0047] 505 Second charging sampling PMOS transistor. Detailed Implementation

[0048] The following is in conjunction with the appendix Figure 2-3 The specific embodiments of the present invention will be further described in detail below.

[0049] It should be noted that in the dual-channel independent automatic battery load identification buck-boost circuit of the present invention, a load detection module, a first detection port VEND1, a second detection port VEND2, a first detection resistor, and a second detection resistor are added. By detecting the voltage of the output terminal and the detection port, dual-channel independent automatic identification of battery load and control of charging status are realized.

[0050] Please see Figure 2 , Figure 2 The diagram shown is a schematic of a dual-channel independent automatic battery load identification buck-boost circuit in an embodiment of the present invention. Figure 2 As shown, the dual-channel independent automatic battery load identification buck-boost circuit includes: buck-boost control chip 101, input capacitor 102, energy storage inductor 104, battery bypass capacitor 105, rechargeable battery 106, boost bypass capacitor 103, first output capacitor 107, first battery load 108, first detection resistor 109, second output capacitor 110, second battery load 111, and second detection resistor 112.

[0051] The buck-boost control chip 101 includes an input high-voltage isolation module 201, a buck-boost control module 202, a load detection module 203, a power port VIN, an inductor port LX, a charging port BAT, a boost output port PMID, a first output port VOUT1, a first detection port VEND1, a second output port VOUT2, a second detection port VEND2, and a ground terminal GND.

[0052] In an embodiment of the invention, the port VIN can be connected to a charger (e.g., a USB port). The port LX is connected to one end of the energy storage inductor 104, the other end of which is connected to the port BAT of the control chip 101, the positive terminal of the battery bypass capacitor 105, and the positive terminal of the rechargeable battery 106; the port PMID is connected to the positive terminal of the boost bypass capacitor 103; the port VOUT1 is connected to the positive terminal of the first output capacitor 107 and the positive terminal of the first battery load 108; the port VEND1 is connected to one end of the sampling resistor 109, the other end of which is connected to ground; the port VOUT2 is connected to... The positive terminals of the second output capacitor 110 and the second battery load 111 are connected to each other. The port VEND2 is connected to one end of the sampling resistor 112, and the other end of the sampling resistor 112 is connected to ground. The port GND terminal is connected to ground. The negative terminals of the input capacitor 102, the boost bypass capacitor 103, the battery bypass capacitor 105, the rechargeable battery 106, the first output capacitor 107, the first battery load, the second output capacitor 110, and the second battery load 108 are all connected to the ground terminal GND.

[0053] The step-up / step-down control module is used to manage and select the power path based on the input voltage of the power port VIN; the load detection module detects the output port VOUT1, the output port VOUT2, the first detection port VEND1, and the second detection port VEND2 respectively; wherein: VOUT1 is the voltage value of port VOUT1 of chip 101, VEND1 is the voltage value of port VEND1 of chip 101, VGT1 is the signal output by load controller 501 after processing the signals of VOUT1 and VEND1 and controlling the conduction capability of the first charging channel PMOS transistor 502 and the first charging sampling PMOS transistor 503, the highest voltage of VGT1 is the voltage value of port PMID VPMID, and IOUT1 is the current flowing through the first charging channel PMOS transistor.

[0054] When the voltage of the output port VOUT1 is greater than or equal to V11 and less than V12, and the voltage of the first detection port VEND1 is less than a predetermined threshold V1, the charging of the first battery load ends; or, when the voltage of the output port VOUT2 is greater than or equal to V21 and less than or equal to V22, and the voltage of the second detection port VEND1 is less than a predetermined threshold V1, the charging of the second battery load ends.

[0055] Specifically, in a preferred embodiment of the present invention, the load detection module includes a load controller, a first charging channel PMOS transistor, a first charging sampling PMOS transistor, a second charging channel PMOS transistor, and a second charging sampling PMOS transistor; wherein, the load controller outputs different signals VGT1 and VGT2 respectively based on the feedback signals from the output port VOUT1, the first detection port VEND1, the output port VOUT2, and the second detection port VEND2, to control the first charging channel PMOS transistor, the first charging sampling PMOS transistor 503, the second charging channel PMOS transistor, and the second charging sampling PMOS transistor, so that the battery load connected to the output port VOUT1 and the output port VOUT2 can achieve three-stage charging.

[0056] First stage of charging: When the load detector detects that the output port VOUT1 < V13, the PMOS transistor of the first charging channel is in trickle charging mode, and the voltage value of the first detection port VEND1 is V2; when the load detector detects that the output port VOUT2 < V23, the PMOS transistor of the first charging channel is in trickle charging mode, and the voltage value of the second detection port VEND1 is V2; wherein, V13 is less than V12, V23 is less than V22, and V2 is greater than V1.

[0057] Second stage of charging: When the load detector detects that the output port V13≤VOUT1<V12, the PMOS transistor of the first charging channel is in constant current charging mode, the voltage value of the first detection port VEND1 is V3, and the charging current is 100% of the set value; similarly, when the load detector detects that the output port V23≤VOUT2<V22, the PMOS transistor of the second charging channel is in constant current charging mode, the voltage value of the second detection port VEND1 is V3, and the charging current is 100% of the set value; wherein, V3 is greater than V2.

[0058] The third stage of charging: When the load detector detects that the output port V12≤VOUT1<V11, the PMOS transistor of the first charging channel is in constant voltage charging mode, and the charging current decreases linearly with the voltage of the output port VOUT1. Charging ends when the voltage of the first detection port VEND1 is a predetermined threshold V1. Similarly, when the load detector detects that the output port V12≤VOUT1<V11, the PMOS transistor of the second charging channel is in constant voltage charging mode, and the charging current decreases linearly with the voltage of the output port VOUT2 until the voltage of the second detection port is a predetermined threshold V1, where V11 is greater than V12, V21 is greater than V22, and V3 is greater than V2.

[0059] Please see Figure 3 , Figure 3 The diagram shown is a schematic of the dual-channel load detection waveform in an embodiment of the present invention. In this embodiment, it can be assumed that V11 and V21 are 4.2 volts; V12 and V22 are 4.05 volts; V13 and V23 are 2.9 volts; V1 is 0.1 volts, V2 is 1 volt, and V3 is 0.2 volts. The following description uses the first charging channel as an example.

[0060] like Figure 3 As shown, when the load detector 501 detects that VOUT1 < 2.9V, the first charging channel PMOS transistor 502 is in trickle charging mode, the charging current IOUT1 is 20% of the set value, and the voltage of VEND1 is 0.2V; when the load detector 501 detects that 2.9V ≤ VOUT1 < 4.15V, the first charging channel PMOS transistor 502 is in constant current charging mode, the charging current IOUT1 is 100% of the set value, and the voltage of VEND1 is 1V; when the load detector 501 detects that 4.15V ≤ VOUT1 < 4.2V, the first charging channel PMOS transistor 502 is in constant voltage charging mode, the charging current IOUT1 decreases linearly with the voltage of VOUT1 until the voltage of VEND1 is 0.1V and charging ends; when the voltage of VOUT1 drops from 4.2V to 4.05V, it will trigger the entry into constant current charging mode.

[0061] It should be noted that the second charging channel PMOS transistor 504 and the first charging channel PMOS are independent of each other and their detection does not affect each other, but the working principle of the two charging channels is the same.

[0062] In some preferred embodiments of the present invention, it is assumed that the buck-boost control module 202 and the load 108 operate at a 5V voltage. When VIN is high (e.g., greater than 6.5 volts) or low (e.g., less than 4.5 volts), the input high voltage isolation module 201 isolates the chip port VIN from the buck-boost control module 202 and the output port VOUT. That is, the load 108 only accepts the discharge of the rechargeable battery 106. In this way, the buck-boost control module 202 and the load 108 connected to the output port VOUT will not be damaged. Furthermore, the rechargeable battery 106 can also avoid being reverse-charged by the charger (e.g., USB port).

[0063] Please see again Figure 2 In this embodiment, the high-voltage isolation module 201 may include an NMOS isolation transistor 303, a power regulator (REG / UVLO / OVP) 301, and a charge pump 302. The drain of the NMOS isolation transistor 303 is connected to port VIN, its source is connected to the output terminal VOUT, and its gate is connected to the output of the charge pump 302. The input of the power regulator 301 is connected to VIN, and its output supplies power to the charge pump 302. The input of the charge pump 302 is connected to the output of the power regulator 301, and its output is connected to the gate of the NMOS isolation transistor 303.

[0064] In another preferred embodiment of the invention, such as Figure 4 As shown, the high-voltage isolation module 201 may also include a power regulator 304, a gate-clamped Zener diode 305, a PMOS isolation transistor 306, a first substrate switching diode 307, and a second substrate switching diode 308. The source of the PMOS isolation transistor 306 is connected to port VIN, its drain is connected to port VOUT, and its gate is connected to the output ENB of the power regulator; the input of the power regulator is connected to port VIN, and its output is ENB; the anode of the gate-clamped Zener diode 305 is connected to ENB, and its cathode is connected to the source of the PMOS isolation transistor; the anode of the first substrate switching diode 307 is connected to port VIN, and its cathode is connected to the substrate of the PMOS isolation transistor 306; the anode of the second substrate switching diode 308 is connected to port VOUT, and its cathode is connected to the substrate of the PMOS isolation transistor 306.

[0065] It should be noted that the boost / buck control module 202 can employ any of the existing technologies. For example, in an embodiment of the present invention, such as... Figure 2As shown, the buck-boost control module 202 may include a PMOS transistor 404, an NMOS transistor 405, a mode selector (MODE) 401, a substrate selector (SUB) 402, and a buck-boost controller (BUCK-BOOSTControl) 403.

[0066] In this configuration, the source of PMOS transistor 404 is connected to VOUT, its drain is connected to LX, and its gate is connected to the VPG output of buck-boost controller 403; the source of NMOS transistor 405 is connected to ground, its drain is connected to LX, and its gate is connected to the VNG output of buck-boost controller 403; the input of mode selector 401 is connected to port VIN, and its output is connected to the input of buck-boost controller 403, VMOD; the two inputs of substrate selector 402 are port VOUT and port BAT, and its output, VSUB, is connected to the input of buck-boost controller 403; the four inputs of buck-boost controller 403 are port VOUT, port VMOD, port VSUB, and port BAT, and its two outputs are port VPG and port VNG.

[0067] In this embodiment, since the substrate selector 402 does not play a related role in the technical solution of the present invention, it will not be described in detail here.

[0068] The following is combined Figure 2 Reference Figure 5 The inventive principle of this invention will be explained below. In this embodiment, as... Figure 2 As shown, the buck-boost control module 202 includes a mode selector 401, which is used to manage and select the power path according to the input voltage of the power port VIN. When VIN≥V2, a synchronous buck circuit is formed in the circuit containing the energy storage inductor to perform switch-type charging of the rechargeable battery and to provide power to the load. When V41≤VIN<V42, the synchronous buck circuit does not work, and the power port VIN only provides power to the load. When VIN<V41, a synchronous boost circuit is formed in the circuit containing the energy storage inductor to discharge the rechargeable battery and provide power to the load. Wherein, V41 is less than V42, and the operating voltage of the buck-boost control module and the load is V3, where V3 is greater than V42. When VIN≥V44 or VIN<V41, the input high-voltage isolation module is used to isolate the power port VIN from the buck-boost control module and the output port VOUT. Wherein, V43<V44.

[0069] Specifically, please refer to Figure 5 , Figure 5The diagram illustrates power path management in an embodiment of the present invention. In this embodiment, V41, V42, V43, and V44 are all DC voltage values, and V41 < V42 < V43 < V44. Figure 5 As shown, V41 is 4.5 volts, V42 is 4.7 volts, V43 is 5 volts, and V44 is 6.5 volts. That is, the operating voltage of the boost / buck control module and the load is V3 = 5 volts.

[0070] When the mode selector 401 detects VIN < 4.5V or VIN > 6.5V, the VREG output level of the power regulator 301 is 0, the charge pump 302 does not work and its output level is 0, that is, the gate of the NMOS isolation transistor 303 is low, the NMOS isolation transistor 303 is turned off, and the port VIN and port VOUT are open. At the same time, when the mode selector 401 detects VIN < 4.5V or VIN > 6.5V, the output signal VMOD makes the buck-boost controller 403 put into the boost working mode, and the rechargeable battery 106 discharges to the load 108 through the energy storage inductor 104 and the buck-boost control module 202.

[0071] When the mode selector 401 detects 4.5V≤VIN≤6.5V, the VREG output of the power regulator 301 is VIN (when 4.5V≤VIN≤5V) or 5V (when 5V<VIN≤6.5V). The charge pump 302 operates with an output level of 7V, which means the gate of the NMOS isolation transistor 303 is at a high level of 7V. Therefore, the NMOS isolation transistor 303 is turned on, and the connection between port VIN and port VOUT is closed.

[0072] When the mode selector 401 detects that 4.5V≤VIN<4.7V, the output signal VMOD puts the buck-boost controller 403 into standby mode. The buck-boost control module 202 does not charge or discharge the rechargeable battery 106, and VIN directly supplies power to VOUT through the NMOS isolation tube 303.

[0073] When the mode selector 401 detects that 4.7V≤VIN<6.5V, the output signal VMOD puts the buck-boost controller 403 into charging mode. VIN charges the rechargeable battery 106 through the NMOS isolation tube 303 and the buck-boost control module 202, and VIN directly supplies power to VOUT through the NMOS isolation tube 303.

[0074] In summary, the dual-channel independent automatic battery load identification buck-boost circuit of the present invention can be specifically used in headphones. It adds a load detection module, a first detection port VEND1, a second detection port VEND2, a first detection resistor, and a second detection resistor. By detecting the voltage at the output terminals and detection ports of the left and right headphones, it can independently and automatically detect the charging status of the dual-channel battery load of the left and right headphones, and conveniently monitor whether the dual-channel battery load of the left and right headphones is fully charged.

[0075] The above description is merely a preferred embodiment of the present invention. The embodiments are not intended to limit the scope of patent protection of the present invention. Therefore, any equivalent structural changes made based on the description and drawings of the present invention should also be included within the scope of protection of the present invention.

Claims

1. A dual-channel independent automatic battery load identification buck-boost circuit, characterized in that, The device includes a buck-boost control chip, an energy storage inductor, a rechargeable battery, a first battery load, and a second battery load. The buck-boost control chip comprises a buck-boost control module, a load detection module, a boost bypass capacitor, a first detection resistor, a second detection resistor, a power port VIN, an inductor port LX, a charging port BAT, a buck-boost port PMID, an output port VOUT1, an output port VOUT2, a first detection port VEND1, a second detection port VEND2, and a ground terminal GND. The VIN port receives the voltage of the power supply; the energy storage inductor is connected between the LX port and the BAT port; the positive terminal of the rechargeable battery is connected to the BAT port; the negative terminal of the rechargeable battery is connected to ground GND; the first battery load is connected between the output port VOUT1 and ground GND; the second battery load is connected between the output port VOUT2 and ground GND; the boost bypass capacitor is connected between the buck-boost port PMID and ground GND; the first sensing resistor is connected between the first sensing port VEND1 and ground GND; the second sensing resistor is connected between the second sensing port VEND2 and ground GND. The step-up / step-down control module is used to manage and select the power path based on the input voltage of the power port VIN; the load detection module detects the voltages of the output ports VOUT1, VOUT2, the first detection port VEND1, and the second detection port VEND2, respectively. The load detection module includes a load controller, a first charging channel PMOS transistor, a first charging sampling PMOS transistor, a second charging channel PMOS transistor, and a second charging sampling PMOS transistor. The gates of the first charging channel PMOS transistor, the first charging sampling PMOS transistor, the second charging channel PMOS transistor, and the second charging sampling PMOS transistor are connected to the load controller, and their sources are connected to the buck-boost port PMID and the power supply port VIN via an input high-voltage isolation module. The drain of the first charging channel PMOS transistor is connected to the output port VOUT1 and the load controller. The drain of the first charging sampling PMOS transistor is connected to the first detection port VEND1 and the load controller. The second charging channel PMOS transistor... The drain of the first charging channel PMOS transistor is connected to the output port VOUT2 and the load controller, and the drain of the second charging sampling PMOS transistor is connected to the second detection port VEND2 and the load controller. The load controller outputs different signals VGT1 and VGT2 according to the feedback signals from the output port VOUT1, the first detection port VEND1, the output port VOUT2, and the second detection port VEND2, respectively, to control the first charging channel PMOS transistor, the first charging sampling PMOS transistor, the second charging channel PMOS transistor, and the second charging sampling PMOS transistor, so that the battery load connected to the output port VOUT1 and the output port VOUT2 can achieve three-stage charging. First stage of charging: When the load controller detects that the output port VOUT1 < V13, the PMOS transistor of the first charging channel is in trickle charging mode, and the voltage value of the first detection port VEND1 is V3; when the load controller detects that the output port VOUT2 < V23, the PMOS transistor of the second charging channel is in trickle charging mode, and the voltage value of the second detection port VEND2 is V3. Second stage of charging: When the load controller detects that output port V13≤VOUT1<V12, the PMOS transistor in the first charging channel is in constant current charging mode, the voltage value of the first detection port VEND1 is V2, and the charging current is 100% of the set value; similarly, when the load controller detects that output port V23≤VOUT2<V22, the PMOS transistor in the second charging channel is in constant current charging mode, the voltage value of the second detection port VEND2 is V2, and the charging current is 100% of the set value; The third stage of charging: When the load controller detects that the output port V12≤VOUT1<V11, the PMOS transistor of the first charging channel is in constant voltage charging mode, and the charging current decreases linearly with the voltage of the output port VOUT1. Charging ends when the voltage of the first detection port VEND1 is a predetermined threshold V1. Similarly, when the load controller detects that the output port V22≤VOUT2<V21, the PMOS transistor of the second charging channel is in constant voltage charging mode, and the charging current decreases linearly with the voltage of the output port VOUT2 until the voltage of the second detection port is a predetermined threshold V1. Among them, V11 is greater than V12, V21 is greater than V22, V13 is less than V12, V23 is less than V22, V2 is greater than V1, and V3 is less than V2.

2. The dual-channel independent automatic battery load identification buck-boost circuit according to claim 1, characterized in that, V11 and V21 are 4.2 volts; V12 and V22 are 4.05 volts; V13 and V23 are 2.9 volts; V1 is 0.1 volts, V2 is 1 volt, and V3 is 0.2 volts.

3. The dual-channel independent automatic battery load identification buck-boost circuit according to claim 1, characterized in that, The input high-voltage isolation module includes an NMOS isolation transistor, a power regulator, and a charge pump; wherein, the drain of the NMOS isolation transistor is connected to the port VIN, its source is connected to the port PMID, and its gate is connected to the output of the charge pump; the input of the power regulator is connected to the port VIN, and its output is used to supply power to the charge pump.

4. The dual-channel independent automatic battery load identification buck-boost circuit according to claim 1, characterized in that, The input high-voltage isolation module includes a power regulator, a gate-clamped Zener diode, a PMOS isolation transistor, a first substrate switching diode, and a second substrate switching diode. The source of the PMOS isolation transistor is connected to port VIN, its drain is connected to port PMID, and its gate is connected to the output node ENB of the power regulator. The input of the power regulator is connected to port VIN, and its output is connected to the output node ENB. The anode of the gate-clamped Zener diode is connected to the output node ENB, and its cathode is connected to the source of the PMOS isolation transistor. The anode of the first substrate switching diode is connected to port VIN, and its cathode is connected to the substrate of the PMOS isolation transistor. The anode of the second substrate switching diode is connected to the drain of the PMOS isolation transistor, and its cathode is connected to the substrate of the PMOS isolation transistor.

5. The dual-channel independent automatic battery load identification buck-boost circuit according to claim 1, characterized in that, The buck-boost control module includes a PMOS transistor, an NMOS transistor, a mode selector, a substrate selector, and a buck-boost controller. The source of the PMOS transistor is connected to the input high-voltage isolation module, its drain is connected to LX, and its gate is connected to the VPG output of the buck-boost controller. The source of the NMOS transistor is connected to ground, its drain is connected to LX, and its gate is connected to the VNG output of the buck-boost controller. The input of the mode selector is connected to port VIN, and its output is connected to the input terminal VMOD of the buck-boost controller.

6. The dual-channel independent automatic battery load identification buck-boost circuit according to claim 1, characterized in that, It also includes an input capacitor and a battery bypass capacitor. The input capacitor is connected between the port VIN and the ground terminal GND; the battery bypass capacitor is connected between the positive terminal of the rechargeable battery and the ground terminal GND.

7. The dual-channel independent automatic battery load identification buck-boost circuit according to claim 1, characterized in that, It also includes a first output capacitor and a second output capacitor, wherein the first output capacitor is connected between the first battery load and the ground terminal GND; and the second output capacitor is connected between the second battery load and the ground terminal GND.

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