A charge pump circuit structure for low power consumption PWM modulation of AMOLED

Abstract

The present invention proposes a charge pump circuit structure of low-power PWM modulation for AMOLED, comprising five modules, namely, a charge pump module, a pulse width modulation module, a slope generation module, a logic module and a driving module. The charge pump module is composed of four Pmos tubes, namely, Pmos2, Pmos3, Pmos4 and Pmos5, a flying capacitor C2 and a capacitor C3, the pulse width modulation module is composed of a voltage-dividing resistor R2, a resistor R3, an error amplifier EA and a comparator COMP, a slope signal slope is generated by the slope generation module, the logic module is composed of a D trigger, a rising edge capture module, an RS trigger and a NAND gate, and the driving module is composed of two driving devices and a group of staggered clock generators. The structure has the advantages of low power consumption, high precision, high efficiency and small area.

Description

Technical Field

[0001] The present invention relates to the technical field of charge pumps, and in particular to a charge pump circuit structure of an AMOLED low-power PWM modulation. Background Art

[0002] AMOLED stands for Active Matrix Organic Light Emitting Device display. Advantages of this display over traditional LCDs include low power consumption, manufacturing flexibility, and faster refresh rates. Compared to traditional LCDs, AMOLED displays do not have a backlight, so each pixel consists of a different color OLED that emits light independently. OLEDs emit light based on the current provided through a drive transistor, which is controlled by a programmed voltage.

[0003] The transistor itself is a nonlinear device and will show a certain resistance effect in the circuit. The resistance value of this resistor changes nonlinearly and varies according to the size of the current passing through. Studies have shown that when a MOSFET with lower on-resistance (RDSON) replaces a diode, the forward voltage drop is much lower than the forward voltage drop of a diode rectifier, so the conduction loss of the rectifier is greatly reduced.

[0004] Since the PWM modulator is used to generate adjustment signals to adjust the brightness of each OLED light-emitting unit, a charge pump circuit is required to provide a high voltage or negative voltage higher than the external power supply voltage when the load is heavy. However, according to the charge pump characteristics: when the charge pump duty cycle is from 0 to 50%, the output voltage is from low to high, and when it is from 50% to 100%, the output voltage is from high to low. Even if the charge pump reaches the maximum output energy, it cannot meet the load requirements, and the output energy of the charge pump will decrease. The above two reasons will lead to unstable performance and high power consumption of the PWM modulation circuit.

[0005] The present invention designs a charge pump circuit structure of low-power PWM modulation for AMOLED, which can be controlled by logic so that when the duty cycle of PH1 is higher than 50%, the duty cycle is fixed at 50%. At this time, the load changes from heavy load to light load, which can effectively avoid energy loss on the rdson tube. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a charge pump circuit structure of low-power PWM modulation of AMOLED, which includes five modules: a charge pump module, a pulse width modulation module, a ramp generation module, a logic module and a drive module.

[0007] Among them, the charge pump module is composed of four Pmos tubes, namely Pmos2, Pmos3, Pmos4 and Pmos5, plus a flying capacitor C2 and a capacitor C3. The positive end of the flying capacitor C2 is connected to the drain end of Pmos2 and the source end of Pmos3, and the negative end of the flying capacitor C2 is connected to the drain end of Pmos5 and the source end of Pmos4; the driving signal PH1 is connected to the gate end of Pmos2 and the gate end of Pmos5, the driving signal PH2 is connected to the gate end of Pmos3 and the gate end of Pmos4, the input signal AVDD is connected to the source end of Pmos2, the input signal vicb is connected to the drain end of Pmos4, the ground signal gnd is connected to the source end of Pmos5, the output signal vgh is connected to the drain end of pmos3 and the positive end of the filter capacitor C3, and the negative end of the filter capacitor C3 is connected to the ground signal gnd.

[0008] Among them, the pulse width modulation module is composed of a voltage-dividing resistor R2, a resistor R3, an error amplifier EA and a comparator COMP. The output signal vgh of the charge pump module is connected to one end of the voltage-dividing resistor R2, the other end of the voltage-dividing resistor R2 is connected to the input signal FB and one end of the voltage-dividing resistor R3, the other end of the voltage-dividing resistor R3 is connected to the ground signal gnd, the positive input of the error amplifier EA is connected to the input signal vref that is independent of temperature, the negative input of the error amplifier EA is connected to the input signal FB, the output end VC of the error amplifier EA is connected to the negative input end of the comparator COMP, the positive input end of the comparator COMP is connected to the slope signal slope, and the output end of the comparator COMP is connected to the input end R of the RS trigger to provide an R signal for the RS trigger.

[0009] Among them, the slope signal slope is generated by the slope generating module, and the slope generating module is composed of an inverter inv, an nmos tube nmos1, a Pmos tube Pmos1, a resistor R1 and a capacitor C1. The clock signal CK2_A with a 50% duty cycle is connected to the input end of the inverter, and the output end of the inverter is connected to the gate end of Pmos1 and the gate end of nmos1. The output end of the inverter outputs the signal CK2_B, the source end of Pmos1 is connected to the power signal, the drain end of Pmos1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the positive end of the capacitor C1 and the drain end of nmos1. The node signal at the connection is the slope signal slope with a 50% duty cycle input to the positive end of the comparator COMP, the negative end of the capacitor C1 is grounded, and the source end of nmos1 is grounded.

[0010] Among them, the logic module is composed of a D flip-flop, a rising edge capture module, an RS flip-flop and a NAND gate. The clock input signal CLK is connected to the input clk terminal of the D flip-flop. The input terminal D and the output terminal QB of the D flip-flop are short-circuited together. The output terminal Q outputs a divided clock signal CK2_A with a duty cycle of 50%. The divided clock signal CK2_A serves as the input signal of the rising edge capture module. The rising edge capture module outputs the rising edge signal CK2 of the divided clock signal CK2_A. The input terminal S of the RS trigger is connected to the rising edge signal CK2. The input terminal R of the RS trigger is connected to the output terminal of the comparator COMP in the pulse width modulation module. The output terminal of the RS flip-flop is connected to one input terminal PH1_ii of the NAND gate. The other input terminal of the NAND gate is connected to the divided clock signal CK2_A with a duty cycle of 50%. The output terminal PH1_i signal of the NAND gate serves as the input terminal of the driving module.

[0011] The driving module is composed of two driving devices and a group of staggered clock generators. The output PH1_i signal of the NAND gate is connected to the input of the staggered clock generator to generate two groups of non-overlapping staggered clock signals. The two groups of signals are respectively connected to the input of the two driving devices, and the output of the two driving devices outputs the driving signal PH1 and the driving signal PH2 respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 Shown is a circuit diagram of the present invention;

[0013] Figure 2 Shown is a working timing diagram of the PWM modulation of the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] See also Figure 1 The present invention provides a charge pump circuit structure of low-power PWM modulation for AMOLED, including five modules: a charge pump module, a pulse width modulation module, a ramp generation module, a logic module and a driving module.

[0016] Among them, the charge pump module is composed of four Pmos tubes, namely Pmos2, Pmos3, Pmos4 and Pmos5, plus a flying capacitor C2 and a capacitor C3. The positive end of the flying capacitor C2 is connected to the drain end of Pmos2 and the source end of Pmos3, and the negative end of the flying capacitor C2 is connected to the drain end of Pmos5 and the source end of Pmos4; the driving signal PH1 is connected to the gate end of Pmos2 and the gate end of Pmos5, the driving signal PH2 is connected to the gate end of Pmos3 and the gate end of Pmos4, the input signal AVDD is connected to the source end of Pmos2, the input signal vicb is connected to the drain end of Pmos4, the ground signal gnd is connected to the source end of Pmos5, the output signal vgh is connected to the drain end of pmos3 and the positive end of the filter capacitor C3, and the negative end of the filter capacitor C3 is connected to the ground signal gnd.

[0017] Among them, the pulse width modulation module is composed of a voltage-dividing resistor R2, a resistor R3, an error amplifier EA and a comparator COMP. The output signal vgh of the charge pump module is connected to one end of the voltage-dividing resistor R2, the other end of the voltage-dividing resistor R2 is connected to the input signal FB and one end of the voltage-dividing resistor R3, the other end of the voltage-dividing resistor R3 is connected to the ground signal gnd, the positive input of the error amplifier EA is connected to the input signal vref that is independent of temperature, the negative input of the error amplifier EA is connected to the input signal FB, the output end VC of the error amplifier EA is connected to the negative input end of the comparator COMP, the positive input end of the comparator COMP is connected to the slope signal slope, and the output end of the comparator COMP is connected to the input end R of the RS trigger to provide an R signal for the RS trigger.

[0018] Among them, the slope signal slope is generated by the slope generating module, and the slope generating module is composed of an inverter inv, an nmos tube nmos1, a Pmos tube Pmos1, a resistor R1 and a capacitor C1. The clock signal CK2_A with a 50% duty cycle is connected to the input end of the inverter, and the output end of the inverter is connected to the gate end of Pmos1 and the gate end of nmos1. The output end of the inverter outputs the signal CK2_B, the source end of Pmos1 is connected to the power signal, the drain end of Pmos1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the positive end of the capacitor C1 and the drain end of nmos1. The node signal at the connection is the slope signal slope with a 50% duty cycle input to the positive end of the comparator COMP, the negative end of the capacitor C1 is grounded, and the source end of nmos1 is grounded.

[0019] Among them, the logic module is composed of a D flip-flop, a rising edge capture module, an RS flip-flop and a NAND gate. The clock input signal CLK is connected to the input clk terminal of the D flip-flop. The input terminal D and the output terminal QB of the D flip-flop are short-circuited together. The output terminal Q outputs a divided clock signal CK2_A with a duty cycle of 50%. The divided clock signal CK2_A serves as the input signal of the rising edge capture module. The rising edge capture module outputs the rising edge signal CK2 of the divided clock signal CK2_A. The input terminal S of the RS trigger is connected to the rising edge signal CK2. The input terminal R of the RS trigger is connected to the output terminal of the comparator COMP in the pulse width modulation module. The output terminal of the RS flip-flop is connected to one input terminal PH1_ii of the NAND gate. The other input terminal of the NAND gate is connected to the divided clock signal CK2_A with a duty cycle of 50%. The output terminal PH1_i signal of the NAND gate serves as the input terminal of the driving module.

[0020] The driving module is composed of two driving devices (dr) and a group of staggered-phase clock generators (phase_gen). The output terminal PH1_i signal of the NAND gate is connected to the input terminal of the staggered-phase clock generator to generate two groups of non-overlapping staggered-phase clock signals. The two groups of signals are respectively connected to the input terminals of the two driving devices, and the output terminals of the two driving devices output driving signals PH1 and PH2 respectively.

[0021] How it works:

[0022] 1. ClK generation: ring oscillator generation;

[0023] 2. CK2_A generates: the divided frequency signal of CLK, whose duty cycle is fixed at 50%;

[0024] 3. Generation of CK2: Capture the rising edge of CK2_A;

[0025] 4. Generation of FB: voltage division of vgh, FB = K*vgh, FB = VREF when stable;

[0026] 5. Generation of VC: Output of error amplifier, vc = K*(VREF-FB);

[0027] 6. Generation of Slope signal: fixed slope signal with a duty cycle of 50% (controlled by CK2_A);

[0028] 7. Generation of R signal: VC is compared with slope signal. When VC is higher, R signal moves further back (away from CK2). When VC is lower, R signal moves forward (closer to CK2).

[0029] 8. PH1 signal generation: The low level time is from the rising edge of the CK2 signal to the rising edge of the R signal, and the high level time is from the rising edge of the R signal to the rising edge of the CK2 signal. Since the rising edge of CK2 is fixed and VC controls the rising edge of the R signal, the duty cycle of the PH1 signal can be changed by VC (the maximum duty cycle is 50%, because when the charge pump duty cycle changes from 0 to 50%, the output voltage changes from low to high; when it changes from 50% to 100%, the output voltage changes from high to low, so the duty cycle is controlled to be linearly adjusted within 0 to 50%), so as to change the proportion corresponding to the charge and discharge of the charge pump and control the vgh voltage;

[0030] 9. PH2 signal generation: opposite to PH1.

[0031] Feedback control working process:

[0032] The difference between VREF and FB is amplified by the error amplifier to generate VC, VC = Av (VREF-FB), that is, when FB is higher, VC is higher, and when FB is lower, VC is lower; VC is compared with the slope signal (when VC is higher, the R signal is further back, that is, away from CK2. The lower VC is, the more forward the R signal is, that is, close to CK2, thereby adjusting the duty cycle of PH1 and PH2 and controlling the vgh voltage. Feedback control loop process: when FB is less than VREF → VC outputs high → PH1 low level time becomes longer (the longest cannot exceed 50%), that is, the charging time is increased → vgh outputs high → FB increases → VFB = VREF; similarly, when FB is greater than VREF → VC outputs low → PH1 low level time becomes shorter (the shortest is 0), that is, the charging time is reduced → vgh outputs low → FB decreases → FB = VREF.

[0033] See also Figure 2The ring oscillator always generates a fixed frequency clock CIK, which is divided by two by the D flip-flop to generate a clock signal CK2_A with a fixed duty cycle of 50%. The rising edge extraction module extracts the rising edge clock signal CK2 of CK2_A as the S end of the RS flip-flop. The CK2_A signal also controls the slope signal generation module, that is, the slope signal is a low signal for 50% of the time and a triangular wave signal for 50% of the time. When the load is heavy, vgh is pulled down by the load. Even if the charge pump reaches 50% (maximum output energy), it cannot meet the load requirements. When VFB is low, VC is high, that is, VC is always greater than slope, that is, the R end of the RS flip-flop is always low, and the R signal is not triggered. At this time, since the S signal is always It will be triggered, so the PH1 duty cycle will be more than 50%. When it is greater than 50%, the charge pump output energy will decrease instead (Charge pump characteristics: when the charge pump duty cycle increases from 0 to 50%, the output voltage increases from low to high; when it increases from 50% to 100%, the output voltage decreases from high to low.), so through logic control, when the PH1 duty cycle is higher than 50%, the duty cycle is fixed at 50%. At this time, the load changes from heavy load to light load, vgh gradually increases, that is, VFB gradually increases, and VC gradually decreases until VC and slope intersect, that is, the R signal will generate a high level, that is, the PH1 duty cycle decreases from 50%, thereby suppressing the vgh voltage from increasing, achieving negative feedback control, and finally stabilizing VFB equal to VREF, that is, vgh is stable (vgh=K*VFB).

[0034] The present invention provides an AMOLED low-power PWM modulated charge pump circuit structure with the following advantages:

[0035] 1. Low power consumption: When lightly loaded, low power consumption can be achieved through 0% duty cycle;

[0036] 2. High precision. Duty cycle adjustment belongs to analog signal adjustment, which can achieve higher precision than digital adjustment.

[0037] 3. High efficiency and small area: Compared with a fixed duty cycle, changing Rdson reduces the need for an Rdson regulating tube, thereby reducing the area and avoiding energy loss on the Rdson tube.

[0038] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0039] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is limited by the appended claims and their equivalents.

Claims

1. A charge pump circuit structure for low-power PWM modulation of AMOLED, characterized in that: include: Charge pump module, pulse width modulation module, ramp generation module, logic module and drive module; The charge pump module is composed of four Pmos tubes, namely Pmos2, Pmos3, Pmos4 and Pmos5, plus a flying capacitor C2 and a capacitor C3, the positive end of the flying capacitor C2 is connected to the drain end of the Pmos2 and the source end of the Pmos3, and the negative end of the flying capacitor C2 is connected to the drain end of the Pmos5 and the source end of the Pmos4; the driving signal PH1 is connected to the gate end of the Pmos2 and the gate end of the Pmos5, the driving signal PH2 is connected to the gate end of the Pmos3 and the gate end of the Pmos4, the input signal AVDD is connected to the source end of the Pmos2, the input signal vicb is connected to the drain end of the Pmos4, the ground signal gnd is connected to the source end of the Pmos5, the output signal vgh is connected to the drain end of the Pmos3 and the positive end of the filter capacitor C3, and the negative end of the filter capacitor C3 is connected to the ground signal gnd; The pulse width modulation module is composed of a voltage-dividing resistor R2, a resistor R3, an error amplifier EA and a comparator COMP. The output signal vgh of the charge pump module is connected to one end of the voltage-dividing resistor R2, the other end of the voltage-dividing resistor R2 is connected to the input signal FB and one end of the voltage-dividing resistor R3, the other end of the voltage-dividing resistor R3 is connected to the ground signal gnd, the positive input of the error amplifier EA is connected to the input signal vref that is independent of temperature, the negative input of the error amplifier EA is connected to the input signal FB, the output end VC of the error amplifier EA is connected to the negative input end of the comparator COMP, the positive input end of the comparator COMP is connected to the slope signal slope, and the output end of the comparator COMP is connected to the input end R of the RS trigger to provide an R signal for the RS trigger; The slope signal slope is generated by the slope generating module, which is composed of an inverter inv, an nmos tube nmos1, a Pmos tube Pmos1, a resistor R1 and a capacitor C1. The clock signal CK2_A with a 50% duty cycle is connected to the input end of the inverter, the output end of the inverter is connected to the gate end of the Pmos1 and the gate end of the nmos1, the output end of the inverter outputs the signal CK2_B, the source end of the Pmos1 is connected to the power signal, the drain end of the Pmos1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the positive end of the capacitor C1 and the drain end of the nmos1, and the node signal at the connection is the slope signal slope with a 50% duty cycle input to the positive end of the comparator COMP, the negative end of the capacitor C1 is grounded, and the source end of the nmos1 is grounded; The logic module is composed of a D flip-flop, a rising edge capture module, an RS flip-flop and a NAND gate. The clock input signal CLK is connected to the input clk terminal of the D flip-flop. The input terminal D and the output terminal QB of the D flip-flop are short-circuited together. The output terminal Q outputs a divided clock signal CK2_A with a duty cycle of 50%. The divided clock signal CK2_A serves as the input signal of the rising edge capture module. The rising edge capture module outputs the rising edge signal CK2 of the divided clock signal CK2_A. The input terminal S of the RS trigger is connected to the rising edge signal CK2. The input terminal R of the RS trigger is connected to the output terminal of the comparator COMP in the pulse width modulation module. The output terminal of the RS flip-flop is connected to one input terminal PH1_ii of the NAND gate. The other input terminal of the NAND gate is connected to the divided clock signal CK2_A with a duty cycle of 50%. The output terminal PH1_i signal of the NAND gate serves as the input terminal of the driving module.

2. The charge pump circuit structure of low power consumption PWM modulation of AMOLED according to claim 1, characterized in that: The driving module is composed of two driving devices and a group of staggered clock generators. The output terminal PH1_i signal of the NAND gate is connected to the input terminal of the staggered clock generator to generate two groups of non-overlapping staggered clock signals. The two groups of signals are respectively connected to the input terminals of the two driving devices, and the output terminals of the two driving devices respectively output driving signals PH1 and PH2.

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