A time synchronization method and device

Abstract

The present application belongs to the field of industrial Internet technology. Specifically, a time synchronization method and device are provided, which includes, when receiving a precise time synchronization protocol message, determining the time deviation between the current time of the chip and the current time of the network master clock in the message; generating a time adjustment command based on the time deviation; adjusting the time of the central timing node of the chip according to the time adjustment command, and generating a real-time adjustment pulse; wherein the real-time adjustment pulse is a pulse for adjusting the time within seconds; adjusting the time of the module timing nodes of the chip in turn according to the real-time adjustment pulse. Based on the technical solution provided by the present application, the gating accuracy of the time-sensitive network can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of industrial Internet, and in particular to a time synchronization method and device. Background Art

[0002] The precise time synchronization protocol messages in the network are often sent at a fixed period, sending the master device time in the network to each slave device in the network. During the period of a precise time synchronization protocol message, the slave device in the network has a timing deviation with the master device in the network due to the deviation between the local timing clock of the device and the timing clock frequency of the master device in the network.

[0003] At present, when each slave device runs the precise time synchronization protocol, it adjusts the time of the slave device according to the time in the precise time synchronization protocol message sent by the master device. The timing circuit of the slave device generally includes two types: centralized and distributed. When the chip scale is large, the centralized timing circuit will cause a large load on the central timing node, and it is difficult to increase the working main frequency. In the distributed timing circuit, the module timing node will have a deviation in the interval between the central node sending two consecutive second synchronization beat signals, and the deviation can only be eliminated when the synchronization signal is received again. However, in the time-sensitive network (TSN), this deviation will affect the gating accuracy of the TSN queue scheduling, especially when the deviation of the chip local timing clock frequency is relatively large, which will cause the queue gating accuracy to become very poor. Summary of the invention

[0004] In view of this, the present invention provides a time synchronization method and device, which can not only realize the time synchronization between the timing node in the chip and the main timing node in the network, but also improve the gating accuracy of the time-sensitive network.

[0005] In order to achieve the above-mentioned purpose, the first aspect of the present application provides a time synchronization method, including: when receiving a precise time synchronization protocol message, determining the time deviation between the current time of the chip and the current time of the network master clock in the message; generating a time adjustment command based on the time deviation; adjusting the time of the central timing node of the chip according to the time adjustment command, and generating a real-time adjustment pulse; wherein the real-time adjustment pulse is a pulse for adjusting the time within seconds; and adjusting the time of the module timing nodes of the chip in turn according to the real-time adjustment pulse.

[0006] From the above, by sending real-time adjustment pulses between the central timing node and each module timing node in real time, and adjusting the time of each timing node in the chip according to the real-time adjustment pulses, the synchronization of each timing node with the precise time of the network master clock is achieved; in addition, since the real-time adjustment pulse is a real-time timing adjustment pulse for timing within seconds, the gating accuracy of time-sensitive networks within seconds can be improved.

[0007] As a possible implementation manner of the first aspect, adjusting the time of the central timing node of the chip according to the time adjustment command includes: if the time deviation includes a time deviation of second timing, directly updating the second timing time of the central timing node.

[0008] As a possible implementation method of the first aspect, adjusting the time of the central timing node of the chip according to the time adjustment command includes: if the time deviation includes a time deviation for timing within seconds, determining a first adjustment step value and a number of adjustments based on the difference between the frequency of the chip timing clock and the time deviation; and adjusting the time of the central timing node of the chip based on the first adjustment step value and the number of adjustments.

[0009] As described above, the methods of adjusting the time of the central timing node for time deviations of different accuracies are provided respectively. Through the above adjustments, the time synchronization accuracy of the central timing node can be improved.

[0010] As a possible implementation manner of the first aspect, the time deviation includes a deviation direction and a deviation magnitude.

[0011] As a possible implementation method of the first aspect, adjusting the time of the module timing nodes of the chip in sequence according to the real-time adjustment pulse includes: generating a second adjustment step value according to the frequency of the chip timing clock; and adjusting the time of the module timing node according to the second adjustment step value and the timing period of the chip timing clock.

[0012] As a possible implementation method of the first aspect, it also includes: adjusting the time of the module timing node of the chip according to the synchronization signal pulse; when there is a deviation between the time obtained after adjustment according to the real-time adjustment pulse and the time obtained after adjustment according to the synchronization signal pulse, the time obtained after adjustment according to the synchronization signal pulse is used as the update time of the module timing node.

[0013] As described above, an implementation method for adjusting the module timing node time according to the real-time adjustment pulse and the synchronization signal pulse is provided. Through the above adjustment, the time synchronization accuracy of the module timing node can be improved.

[0014] As a possible implementation method of the first aspect, adjusting the time of the module timing nodes of the chip in sequence according to the real-time adjustment pulse includes: when the module timing node performs time adjustment: the previous module timing node transmits the real-time adjustment pulse to the adjacent next module timing node to adjust the time of the next module timing node.

[0015] As a possible implementation manner of the first aspect, the method further includes: delaying the real-time adjustment pulse by one beat and sending it to the next module timing node.

[0016] The second aspect of the present application provides a time synchronization device, including: a determination module, a first generation module, a second generation module and an adjustment module. The determination module is used to determine the time deviation between the current time of the chip and the current time of the network master clock in the message when receiving a precise time synchronization protocol message; the first generation module is used to generate a time adjustment command based on the time deviation; the second generation module is used to adjust the time of the central timing node of the chip according to the time adjustment command, and generate a real-time adjustment pulse; wherein the real-time adjustment pulse is a pulse for adjusting the time within seconds; the adjustment module is used to adjust the time of the module timing nodes of the chip in sequence according to the real-time adjustment pulse.

[0017] A third aspect of the present application provides a computing device, comprising: a processor, and a memory; the memory stores program instructions, and when the program instructions are executed by the processor, the processor executes the time synchronization method described in any one of the first aspects above. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The various technical features of the present application and the relationship between them are further explained below with reference to the accompanying drawings. The accompanying drawings are exemplary, and some technical features are not shown in actual proportion. In addition, some drawings may omit technical features that are commonly used in the technical field to which the present application belongs and are not essential for understanding and implementing the present application, or additional technical features that are not essential for understanding and implementing the present application may be shown. In other words, the combination of the various technical features shown in the accompanying drawings is not used to limit the present application. In addition, throughout the present application, the same figure numbers refer to the same content. The specific description of the drawings is as follows:

[0019] Figure 1 A framework diagram of a centralized local timing circuit provided by the related technology of this application;

[0020] Figure 2 A framework diagram of a distributed local timing circuit provided by the related technology of this application;

[0021] Figure 3 A framework diagram of a time synchronization circuit provided in an embodiment of the present application;

[0022] Figure 4 A flowchart of a time synchronization method provided in an embodiment of the present application;

[0023] Figure 5 A framework diagram of a TSN switching chip provided in an embodiment of the present application;

[0024] Figure 6 A schematic diagram of the structure of a time synchronization device provided in an embodiment of the present application;

[0025] Figure 7 A schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0026] Figure 8 A schematic diagram of the structure of another computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The words "first, second, third, etc." or module A, module B, module C and other similar terms in the specification and claims are only used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that the specific order or sequence can be interchanged where permitted so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0028] In the following description, the numbers representing the steps, such as S110, S120, etc., do not necessarily mean that the steps must be executed in this manner. If permitted, the order of the previous and next steps can be interchanged, or they can be executed simultaneously.

[0029] The term "comprising" as used in the description and claims should not be interpreted as being limited to what is listed thereafter; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the features, integers, steps or components mentioned, but does not exclude the presence or addition of one or more other features, integers, steps or components and groups thereof. Therefore, the expression "a device comprising means A and B" should not be limited to a device consisting of components A and B only.

[0030] References to "one embodiment" or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present application. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places in this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. In addition, in one or more embodiments, the particular features, structures, or characteristics can be combined in any appropriate manner, as would be apparent to one of ordinary skill in the art from this disclosure.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present application. In case of any inconsistency, the meaning described in this specification or the meaning derived from the contents recorded in this specification shall prevail. In addition, the terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0032] Before describing the specific implementation methods of the present application in detail, the related technologies of the present application are first described in detail.

[0033] like Figure 1 As shown, the related art provides an implementation scheme of a centralized local timing circuit. In this implementation scheme, the chip is generally composed of a central timing node and multiple module timing nodes. The central timing node is used to receive the signal of the local timing clock (clock) and the precise time synchronization protocol message. When other timing nodes (module timing nodes) in the chip need to use local timing time, they need to use the timing signal issued by the central timing node. In this related art, when the chip scale is relatively large and the number of modules using the chip local timing time is large, the load corresponding to the central timing node is large. At this time, if the chip area is large, it will cause the routing on the chip to be longer, making the physical implementation of the chip more difficult; in addition, in this related art, since the central timing node of the chip corresponds to a large load, it is difficult to increase the main frequency of the chip.

[0034] like Figure 2As shown, the related art also provides an implementation scheme of a distributed local timing circuit. In this implementation scheme, the chip is also composed of a central timing node and multiple module timing nodes. The central timing node and each module timing node use the local clock main frequency as the timing reference and independently time each other. The central timing node sends the synchronization signal pulse to the adjacent module timing node with a second timing cycle, and the module timing node sends the synchronization pulse to the next module timing node adjacent to it, and so on until the synchronization signal is transmitted to the last module timing node. In this related technology, when the central timing node receives the precise time synchronization protocol message, it adjusts the timing time of the central timing node according to the time deviation. Each module timing node adjusts its own timing time when receiving the synchronization signal pulse, thereby realizing the synchronization of the chip timing time. However, in this related technology, when the chip scale is relatively large, although the physical implementation of the chip is relatively simple, within the time interval between the central timing node sending two consecutive synchronization signal pulse beats, the local timing of the module timing node will have a deviation within seconds, but this deviation can only be eliminated after the next synchronization signal is received. In the application of time-sensitive networks, this intra-second deviation will affect the gating accuracy of the time-sensitive network, especially when the frequency deviation of the chip's local timing clock is large, which will cause the gating accuracy of the time-sensitive network to become very poor and unable to meet application requirements.

[0035] Based on the research on related technologies, a time synchronization method provided in an embodiment of the present application is described in detail below in conjunction with the accompanying drawings.

[0036] like Figure 3 FIG. 1 is a schematic diagram of a time synchronization circuit provided by an embodiment of the present application. The time synchronization circuit includes a central timing node and multiple module timing nodes. Figure 3 As shown, the output end of the central timing node is connected to the input end of the module timing node 1, and the output end of the module timing node 1 is connected to the input end of the module timing node 2, in accordance with the above-mentioned head-to-tail connection method, until it is connected to the last module timing node n in the chip. In addition, whether it is the central timing node or each module timing node, it can receive a timing clock signal (clock), so the architecture mode is a distributed mode. It should be understood that the above-mentioned connection can be a cable connection or a communication connection, which is not limited in this embodiment.

[0037] In this embodiment, the input end of the central timing node is used to receive the precise time synchronization protocol, the time adjustment command and the timing clock signal; the output end of the central timing node is used to output the real-time adjustment pulse and the synchronization signal pulse. In this embodiment, the synchronization signal pulse is a pulse for timing in seconds, for example, the synchronization signal pulse can be sent once per second. The real-time adjustment pulse is a pulse for timing in seconds, for example, the real-time adjustment pulse can be sent once per nanosecond. The input end of the module timing node is used to receive the real-time adjustment pulse and the synchronization signal pulse sent by the previous timing node, and is also used to receive the timing clock signal; wherein the previous timing node can be a central timing node or a module timing node.

[0038] like Figure 4 The flowchart of a time synchronization method provided by an embodiment of the present application is shown. The implementation process of the method mainly includes steps S110-S140, and each step is introduced in turn below:

[0039] S110: When receiving a precise time synchronization protocol message, determine a time deviation between a current time of the chip and a current time of a network master clock in the message.

[0040] In this embodiment, the precise time synchronization protocol may include: IEEE 1588 (PTP) or IEEE 8021.AS (gPTP), etc. The precise time synchronization protocol works in master-slave mode, and clock calibration is completed with the help of clock synchronization messages. The network master clock periodically sends synchronization messages, and the slave clock calculates the time delay of the master-slave line message transmission and the clock offset of the master and slave clocks based on the timestamp information of the received message, and adjusts the local time accordingly, so that the slave clock maintains a time base consistent with the network master clock.

[0041] In this embodiment, the current time of the chip is obtained by the local clock of the chip; the precise time synchronization protocol message contains the timestamp of the network master clock. The time deviation between the current time of the chip and the timestamp of the network master clock is obtained by subtracting the current time of the chip and the timestamp of the network master clock. It should be understood that the time deviation mentioned in this embodiment includes the deviation direction and the deviation magnitude. As an implementation method, the deviation direction can be determined by the positive and negative signs of the difference, and the deviation magnitude can be determined by the absolute value of the difference.

[0042] S120: Generate a time adjustment command based on the time deviation.

[0043] The time adjustment command includes the size of the adjustment and the direction of the adjustment. For example, if the time deviation calculated by step S110 is -5ns, the time adjustment command should include adjusting 5ns in the positive direction. It should be understood that the positive or negative direction here can be determined according to the positive and negative signs, which can be predefined. For example, a positive adjustment is defined when the time deviation is positive, that is, the current time is adjusted faster, and a negative adjustment is defined when the time deviation is negative, that is, the current time is adjusted slower.

[0044] S130: Adjust the time of the central timing node of the chip according to the time adjustment command, and generate a real-time adjustment pulse.

[0045] In this embodiment, if the time deviation includes the time deviation of second timing, for example, the time deviation is 2s, the second timing time of the central timing node is directly modified and updated. If the time deviation includes the time deviation of intra-second timing, the first adjustment step value and the number of adjustments are determined based on the difference between the frequency of the chip timing clock and the time deviation. The step value is the time interval between two adjustment pulses.

[0046] Specifically: determine the period of the chip timing clock through the frequency of the chip timing clock, and use the period of the chip timing clock as the first adjustment step value; then determine the number of adjustments based on the time deviation and the first adjustment step value. For example: the frequency of the chip timing clock is 500MHz, then the first adjustment step value is: 1 / 500MHz = 2ns. If the time deviation at this time is 200ns, it is necessary to adjust 100 times with a step value of 2ns within 1s, that is, the number of adjustments is 100 times.

[0047] Next, the time of the central timing node in the chip is adjusted based on the first adjustment step and the number of adjustments determined above.

[0048] Each time the central timing node makes a time adjustment, a real-time adjustment pulse signal is sent to the next module timing node. The real-time pulse signal is a pulse for adjusting the time within a second. In addition, the real-time pulse signal includes the size of the adjustment and the direction of the adjustment. It should be understood that the module timing node in this embodiment can be each Ethernet interface MAC or PHY, etc.

[0049] S140: adjusting the time of the module timing nodes of the chip in sequence according to the real-time adjustment pulse.

[0050] In this embodiment, when the module timing node does not receive the real-time adjustment pulse, normal timing is performed using the period of the chip timing clock as a unit.

[0051] As an implementation manner, when there are multiple module timing nodes, the time of each module timing node of the chip is adjusted in sequence according to the real-time adjustment pulse.

[0052] When the module timing node receives the real-time adjustment pulse, it first generates a second adjustment step value according to the frequency of the chip timing clock, and then adjusts the time of the module timing node according to the second adjustment step value and the timing period of the chip timing clock.

[0053] Specifically: the period of the chip timing clock is determined by the frequency of the chip timing clock, and the period of the chip timing clock is used as the second adjustment step value. Then the second adjustment step value is superimposed in the next timing cycle of the chip timing clock. For example: the frequency of the chip timing clock is 500MHz, then the second adjustment step value is: 1 / 500MHz=2ns. If the adjustment direction is positive, the time of the module timing node in the next timing cycle is +4ns. If the adjustment direction is negative, the time of the module timing node in the next timing cycle is +0ns. It should be understood that since the frequency of the chip timing clock is 500MHz, if the second adjustment step value is 0, the time of the module timing node in the next timing cycle is +2ns. Therefore, when there is a positive adjustment step value of 2ns, the time of the module timing node in the next timing cycle is +4ns. When there is a negative adjustment step value of 2ns, the time of the module timing node in the next timing cycle is +0ns.

[0054] In addition, by Figure 3 It can be seen that in addition to the real-time adjustment pulse, there is also a synchronization signal pulse between each timing node. In this embodiment, the synchronization signal pulse is a pulse sent by the second timing, for example, it can be sent once for 1s; and the real-time adjustment pulse is a timing pulse within a second, for example, it can be sent once for 1ns. Therefore, when the timing node receives the synchronization signal pulse, the time of the timing node of the chip is adjusted according to the synchronization signal pulse; when the timing node receives the real-time adjustment pulse, the time of the timing node of the chip is adjusted according to the real-time adjustment pulse. As an implementation method, when the time T1 of the timing node obtained after adjustment according to the real-time adjustment pulse is different from the time T2 of the timing node obtained after adjustment according to the synchronization signal pulse (i.e., inconsistent), the time T2 obtained after adjustment according to the synchronization signal pulse is used as the update time of the timing node. It can be understood that: when a time error occurs within a second, the adjustment is made based on the adjustment instruction of the real-time adjustment pulse, and when a time error occurs in the second timing, the adjustment is made based on the adjustment instruction of the synchronization signal pulse.

[0055] Each time the module timing node makes a time adjustment, the real-time adjustment pulse is delayed by one beat (i.e., one cycle) and sent to the next adjacent module timing node to adjust the time of the next module timing node. Similarly, the real-time adjustment pulse and adjustment direction are sent to all timing nodes in the chip, thereby achieving synchronization of all timing nodes in the chip with the network master clock time.

[0056] Based on the time synchronization method provided in the embodiment of the present application, if the timing clock is 500 MHz, the synchronization accuracy between the module timing node and the network master clock time can be controlled to 2ns, thereby improving the gating accuracy of the time-sensitive network.

[0057] like Figure 5 As shown, a TSN switching chip provided by an embodiment of the present application, wherein the Devcpu module in the TSN switching chip serves as a central timing node, and each Ethernet interface MAC module in the TSN switching chip serves as a plurality of module timing nodes. Through the time synchronization method provided by the above embodiment, by sending real-time adjustment pulses and adjustment direction signals between the Devcpu module and each MAC module, the synchronization of each MAC module with the precise time of the network master clock is achieved, thereby ensuring the accuracy of the TSN egress queue gating scheduling in the MAC module.

[0058] Another embodiment of the present application provides a time synchronization device, which can be implemented by a software system, or by a hardware device, or by a combination of a software system and a hardware device. It should be understood that the time synchronization method and the time synchronization device are based on the same concept, and since the principles of the method and the device for solving the problem are similar, the implementation of the device and the method can refer to each other, and the repeated parts will not be repeated.

[0059] It should be understood that Figure 6 This is only an exemplary structural diagram of a time synchronization device, and the present application does not limit the division of functional modules in the lane structure recognition device. Figure 6 As shown, the time synchronization device can be logically divided into multiple modules, each module can have different functions, and the function of each module can be realized by a processor in the electronic device reading and executing instructions in the memory. Exemplarily, the time synchronization device includes a determination module 610, a first generation module 620, a second generation module 630 and an adjustment module 640.

[0060] In an optional implementation, the time synchronization device is used to execute Figure 4The contents described in steps S110-S140 shown. Specifically, it can be: a determination module 610, which is used to determine the time deviation between the current time of the chip and the current time of the network master clock in the message when receiving a precise time synchronization protocol message; a first generation module 620, which is used to generate a time adjustment command based on the time deviation; a second generation module 630, which is used to adjust the time of the central timing node of the chip according to the time adjustment command, and generate a real-time adjustment pulse; wherein the real-time adjustment pulse is a pulse for adjusting the time within seconds; an adjustment module 640, which is used to adjust the time of the module timing nodes of the chip in sequence according to the real-time adjustment pulse.

[0061] In some embodiments, adjusting the time of the central timing node of the chip according to the time adjustment command includes: if the time deviation includes the time deviation of the second timing, directly updating the second timing time of the central timing node.

[0062] In this embodiment, the time of the central timing node of the chip is adjusted according to the time adjustment command, including: if the time deviation includes a time deviation of timing within seconds, a first adjustment step value and a number of adjustments are determined based on the difference between the frequency of the chip timing clock and the time deviation; and the time of the central timing node of the chip is adjusted based on the first adjustment step value and the number of adjustments.

[0063] In some embodiments, the time deviation includes a deviation direction and a deviation magnitude.

[0064] In some embodiments, adjusting the time of the module timing nodes of the chip in sequence according to the real-time adjustment pulse includes: generating a second adjustment step value according to the frequency of the chip timing clock; and adjusting the time of the module timing node according to the second adjustment step value and the timing period of the chip timing clock.

[0065] In some embodiments, it also includes: adjusting the time of the module timing node of the chip according to the synchronization signal pulse; when there is a deviation between the time obtained after adjusting according to the real-time adjustment pulse and the time obtained after adjusting according to the synchronization signal pulse, the time obtained after adjusting according to the synchronization signal pulse is used as the update time of the module timing node.

[0066] In some embodiments, adjusting the time of the module timing nodes of the chip in sequence according to the real-time adjustment pulse includes: when the module timing node performs time adjustment: the previous module timing node transmits the real-time adjustment pulse to the adjacent next module timing node to adjust the time of the next module timing node.

[0067] In some embodiments, it also includes: delaying the real-time adjustment pulse by one beat (ie, one cycle) and sending it to the next module timing node.

[0068] The present application also provides a computing device, including a processor and a memory. The memory stores program instructions, which, when executed by the processor, cause the processor to execute Figure 4 The method of the corresponding embodiment, or each optional embodiment thereof.

[0069] Figure 7 9 is a schematic structural diagram of a computing device 900 provided in an embodiment of the present application. The computing device 900 includes: a processor 910 and a memory 920.

[0070] It should be understood that Figure 7 The computing device 900 shown in FIG. 9 may further include a communication interface 930 , which may be used for communicating with other devices.

[0071] The processor 910 may be connected to a memory 920. The memory 920 may be used to store the program code and data. Therefore, the memory 920 may be a storage unit inside the processor 910, or an external storage unit independent of the processor 910, or a component including a storage unit inside the processor 910 and an external storage unit independent of the processor 910.

[0072] Optionally, the computing device 900 may further include a bus. The memory 920 and the communication interface 930 may be connected to the processor 910 via a bus. The bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc.

[0073] It should be understood that in the embodiment of the present application, the processor 910 may adopt a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. Alternatively, the processor 910 may adopt one or more integrated circuits to execute relevant programs to implement the technical solutions provided in the embodiment of the present application.

[0074] The memory 920 may include a read-only memory and a random access memory, and provides instructions and data to the processor 910. A portion of the processor 910 may also include a nonvolatile random access memory. For example, the processor 910 may also store information on the device type.

[0075] When the computing device 900 is running, the processor 910 executes the computer-executable instructions in the memory 920 to perform the operating steps of the above method.

[0076] It should be understood that the computing device 900 according to the embodiment of the present application can correspond to the corresponding subjects in the methods according to the embodiments of the present application, and the above-mentioned and other operations and / or functions of each module in the computing device 900 are respectively for implementing the corresponding processes of each method of the present embodiment. For the sake of brevity, they will not be repeated here.

[0077] The present application also provides another computing device, such as Figure 8 The structure schematic diagram of another computing device 1000 provided by the embodiment is shown, including: a processor 1010, and an interface circuit 1020, wherein the processor 1010 accesses a memory through the interface circuit 1020, and the memory stores program instructions, and when the program instructions are executed by the processor, the processor executes Figure 4 In addition, the computing device may also include a communication interface, a bus, etc. For details, see Figure 7 The description of the embodiment shown is omitted. Exemplarily, the interface circuit 1020 may be a CAN bus or a LIN bus.

[0078] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0079] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0080] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0081] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0082] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0083] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0084] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, it is used to execute a time synchronization method, which includes at least one of the solutions described in the above embodiments.

[0085] The computer storage medium of the embodiment of the present application can adopt any combination of one or more computer-readable media. Computer-readable media can be computer-readable signal media or computer-readable storage media. Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples (non-exhaustive lists) of computer-readable storage media include: electrical connections with one or more wires, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this document, computer-readable storage media can be any tangible medium containing or storing programs, which can be used by instruction execution systems, devices or devices or used in combination with them.

[0086] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0087] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0088] Computer program code for performing the operation of the present application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., using an Internet service provider to connect through the Internet).

[0089] Note that the above are only preferred embodiments of the present application and the technical principles used. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the concept of the present application, all of which belong to the protection scope of the present application.

Claims

1. A time synchronization method, characterized in that: include: Upon receiving a precise time synchronization protocol message, determining a time deviation between a current time of the chip and a current time of a network master clock in the message; generating a time adjustment command based on the time deviation; Adjust the time of the central timing node of the chip according to the time adjustment command, and generate a real-time adjustment pulse; wherein the real-time adjustment pulse is a pulse for adjusting the time within a second; sequentially adjusting the time of the module timing nodes of the chip according to the real-time adjustment pulse; The step of sequentially adjusting the time of the module timing nodes of the chip according to the real-time adjustment pulse comprises: upon receiving the real-time adjustment pulse, generating a second adjustment step value according to the frequency of the chip timing clock; Adjust the time of the module timing node according to the second adjustment step value and the timing period of the chip timing clock; The time deviation includes a deviation direction and a deviation magnitude.

2. The method according to claim 1, characterized in that The step of adjusting the time of the central timing node of the chip according to the time adjustment command includes: If the time deviation includes the time deviation of the second timing, the second timing time of the central timing node is directly updated.

3. The method according to claim 1, characterized in that The step of adjusting the time of the central timing node of the chip according to the time adjustment command includes: If the time deviation includes a time deviation of timing within seconds, determining a first adjustment step value and an adjustment number based on a difference between the frequency of the chip timing clock and the time deviation; The time of the central timing node of the chip is adjusted based on the first adjustment step value and the adjustment number.

4. The method according to claim 1, characterized in that: Also includes: Adjusting the time of the module timing node of the chip according to the synchronization signal pulse; When there is a deviation between the time obtained after adjustment according to the real-time adjustment pulse and the time obtained after adjustment according to the synchronization signal pulse, the time obtained after adjustment according to the synchronization signal pulse is used as the update time of the module timing node.

5. The method according to claim 1, characterized in that: The step of sequentially adjusting the time of the module timing nodes of the chip according to the real-time adjustment pulse comprises: When the module timing node performs time adjustment: the previous module timing node transmits a real-time adjustment pulse to the next adjacent module timing node to adjust the time of the next module timing node.

6. The method according to claim 5, characterized in that Also includes: The real-time adjustment pulse is delayed by one cycle and sent to the next module timing node.

7. A time synchronization device, characterized in that: include: A determination module, configured to determine, upon receiving a precise time synchronization protocol message, a time deviation between a current time of the chip and a current time of a network master clock in the message; A first generating module, configured to generate a time adjustment command based on the time deviation; A second generating module is used to adjust the time of the central timing node of the chip according to the time adjustment command, and generate a real-time adjustment pulse; wherein the real-time adjustment pulse is a pulse for adjusting the time within a second; An adjustment module, used for sequentially adjusting the time of the module timing nodes of the chip according to the real-time adjustment pulse; The adjustment module is specifically used to generate a second adjustment step value according to the frequency of the chip timing clock when receiving the real-time adjustment pulse; adjust the time of the module timing node according to the second adjustment step value and the timing period of the chip timing clock; wherein the time deviation includes the deviation direction and the deviation size.

8. A computing device, characterized in that include: processor, and memory; The memory stores program instructions thereon, and when the program instructions are executed by the processor, the processor executes the time synchronization method according to any one of claims 1 to 6.

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