Operand pool instruction reservation cluster in scheduler circuitry of processor

Abstract

A scheduler circuit in a processor discloses an operand pool instruction reservation cluster. The scheduler circuit includes multiple operand pool reservation circuits, each with a allocated number of source operands for storing instructions that must be ready before issuance. Instructions with the same number of source operands but not yet ready for issuance can be stored in operand pool reservation circuits with the same allocated number of source operands. In this way, multiple reservation entries and associated comparator circuits in the cluster scheduler circuit are distributed across multiple operand pool reservation circuits to avoid or reduce the increase in the number and complexity of scheduling path connections in each reservation circuit. This can avoid or reduce the increase in scheduling latency for a given number of reservation entries in the cluster scheduler circuit.

Description

Technical Field

[0001] The technology disclosed herein relates to a computer processor (“processor”), and more specifically to a scheduler circuit that schedules the execution of instructions in an instruction pipeline within the processor. Background Technology

[0002] Microprocessors, also known as “processors,” perform computational tasks for a variety of applications. A traditional microprocessor includes a central processing unit (CPU), which comprises one or more processor cores, also called “CPU cores.” The CPU executes computer program instructions (“instructions”), also known as “software instructions,” to perform operations based on data and generate results, i.e., produce values. Instructions that generate produce values ​​are “producer” instructions. These produce values ​​can then be stored in memory, provided as output to input / output (“I / O”) devices, or used as input values ​​to (i.e., communicated) another “consumer” instruction executed by the CPU (for example). Therefore, consumer instructions depend on the produce values ​​generated by the producer instructions as input values ​​for their execution. These producer and consumer instructions are also collectively referred to as dependent instructions.

[0003] Instruction pipelining is a processing technique that increases the throughput of instructions being executed by a processor by breaking down the processing of each instruction into a series of steps. These steps are executed in one or more instruction pipelines, each consisting of multiple stages in the instruction processing circuitry of the processor. Optimal processor performance can be achieved if all stages in the instruction pipeline can process instructions simultaneously and sequentially, as the instructions are ordered in the pipeline. Furthermore, many modern processors are out-of-order processors, capable of executing the data flow of instructions based on the availability of the input data consumed by the instructions rather than the program order of the instructions. Therefore, an out-of-order processor can execute instructions once all the input data to be consumed by them has been generated. While sequential processing of the data flow of instructions can lead to unpredictable specific order of instruction execution, sequential execution of the data flow in out-of-order processors can achieve performance gains. For example, when retrieving input data to be consumed for an older instruction, instead of "stopping" (i.e., intentionally introducing processing delays), an out-of-order processor can continue executing the most recently fetched instruction, which can be executed immediately. In this way, processor clock cycles that would not otherwise be used for instruction processing and execution can be effectively utilized by an out-of-order processor.

[0004] The instruction processing circuitry in the processor includes an instruction fetching circuit configured to retrieve instructions to be executed from an instruction memory (e.g., system memory or instruction cache). For example, the instruction memory may be located in or be part of the system memory in a processor-based system. The fetched instructions are decoded and preprocessed in the instruction pipeline of the instruction processing circuitry before reaching the execution circuitry. The decoded instructions are also provided to a reservation circuit in the scheduler circuitry. The scheduler circuitry is configured to issue the decoded instructions to be executed from the reservation circuitry to the execution circuitry once all source register operands (e.g., immediate values, values ​​stored in memory, and values ​​generated from producer instructions) are available and any structural hazard for the decoded instructions has been resolved. For example, the scheduler circuitry is responsible for ensuring that the necessary values ​​for the operands of the decoded consumer instructions are available before issuing the decoded consumer instructions to the execution circuitry for execution. The execution circuitry is configured to execute the decoded instructions received from the scheduler circuitry.

[0005] The scheduler circuit is configured to broadcast a wake-up signal on the wake-up bus to "wake up" a consumer instruction in response to the publication of a producer instruction to the execution circuit. The wake-up signal indicates that the value produced by the execution of the published producer instruction will be available, and therefore the consumer instruction of the producer instruction can now be published to the execution circuit following the producer instruction. In other words, once a producer instruction is scheduled by the scheduler circuit to be published from the reserved circuit to the execution circuit, it is known that the value produced by the execution of the producer instruction will soon become available for its consumer instruction. Because the wake-up signal is generated in response to the published producer instruction, its consumer instruction can only be woken up at least one (1) clock cycle after the producer instruction, thus ensuring that the producer instruction is executed before the consumer instruction executes using the value produced by the consumer instruction. Therefore, the critical timing path in the instruction processing circuit of the processor is the wake-up path in the scheduler circuit to wake up the instruction to be published to the execution circuit. The wake-up or scheduling delay of an instruction is the number of clock cycles after its publication when the value it produces is available for consumption by the consumer instruction. Some producer instructions are single-clock-cycle (“single-cycle”) delayed producers, meaning that the execution circuitry can generate and make the produced value available for the producer instruction within one (1) clock cycle. Other producer instructions are multi-clock-cycle delayed producers, meaning that the execution circuitry generates and makes the produced value available for the producer instruction within more than one (1) clock cycle. An important part of the wake-up design in the scheduler circuitry is that consumer instructions that rely on single-cycle delayed producer instructions can be issued by the scheduler circuitry in clock cycles back-to-back with the producer instructions to reduce scheduling latency.

[0006] A traditional scheduler circuit includes a reservation circuit with "M" reservation entries to store M instructions awaiting execution. The scheduler circuit also includes a pick circuit that controls when the M instructions awaiting execution by the execution circuit in the reservation circuit are issued in the issue channels. The pick circuit determines which instruction to issue based on a comparator circuit that compares register information in a wake-up signal received on the wake-up bus, indicating that the specified register is ready to be used as a source operand for an instruction. Each reservation entry in the reservation circuit can receive a wake-up signal from "K" producer instructions, which can be issued by the scheduler circuit in each clock cycle. Therefore, in this example, "M" refers to the instruction window size, and "K" refers to the issue width or number of issue channels to the execution circuit, where producer instructions can be issued to the execution circuit for execution. Typically, a larger M-entry size and a larger K-issue width are required to improve processor performance. As mentioned above, an important part of the wake-up design in the scheduler circuit is that consumer instructions, which rely on single-cycle delays for producer instructions, can be issued back-to-back with the producer instructions in clock cycles. The three (3) main components of the wake-up timing path in the scheduler circuit that affect single-cycle wake-up are: (1) the propagation time (i.e., timing delay) of the K wake-up signals coupled on the wake-up bus from the K publish channels to the pick circuit as a result of publishing K producer instructions in the publish channels; (2) the wake-up time in the pick circuit, which employs a scheme to compare the wake-up signals with reserved instructions to select K instructions to be published from M entries in the reserved circuit; and (3) the propagation time of coupling the K pick signals generated by the pick circuit to the M entries in the reserved circuit to select the K entries to be published from the M entries in the K publish channels. It may be desirable to increase the instruction window size M in the reserved circuit of the processor's instruction processing circuit to increase processor performance. The larger the instruction window size, the more likely it is to always be ready to publish K available instructions in the K publish channels to maximize the efficiency of the execution circuit. However, increasing the instruction window size M to improve performance may adversely affect the delay of all three (3) components of the wake-up timing path. For example, the wake-up time in the select circuit is affected by the load on the wake-up bus connected to the comparator in the select circuit. As the number of entries in the reserved circuit increases, the capacitive load on the wake-up bus also increases because it must drive the additional comparator circuitry in the select circuit. Summary of the Invention

[0007] Exemplary aspects disclosed herein include an operand pool instruction reservation cluster in a scheduler circuitry within a processor. The processor includes instruction processing circuitry comprising multiple instruction processing stages configured to pipeline the processing and execution of fetched instructions according to a data stream. Scheduler circuitry is included in the instruction processing stages of the instruction processing circuitry to schedule the issuance of instructions to be executed to the execution circuitry. The scheduler circuitry includes a reservation circuitry that controls the issuance of such instructions until their source operands are ready to be consumed. The scheduler circuitry also includes a pick circuitry comprising a comparator circuitry configured to compare register information received in a wake-up signal indicating which registers are available for consumption with the source operands of reserved instructions in the reservation circuitry to determine if any reserved instructions are ready to be issued. Once it is known that the necessary value for the source operand of an instruction will be available when the instruction is executed, the scheduler circuitry is responsible for issuing the instruction to the issuance channel for execution by the execution circuitry. Therefore, once it is known that the necessary produced value from the producer instruction will be available for consumption before the execution of the consumer instruction, the scheduler circuitry issues the consumer instruction.

[0008] Ideally, the scheduler circuit should be designed so that, for performance reasons, consumer instructions that rely on single-cycle-delayed producer instructions can be issued in back-to-back clock cycles with the producer instructions. The delay of a producer instruction is the number of clock cycles (“cycles”) after its output value is consumed by the consumer instruction following its issuance. It may also be desirable to design the scheduler circuit so that, for performance reasons, consumer instructions that rely on single-cycle-delayed producer instructions can be issued in back-to-back clock cycles with the producer instructions. It may also be desirable to increase the number of reserved entries in the scheduler circuit to improve scheduling performance, as increasing the number of reserved entries increases the likelihood that enough instructions are ready to be issued in each issuance channel. However, increasing the number of reserved entries in the scheduler circuit increases the number and complexity of scheduling path connections in the scheduler circuit, thereby increasing scheduling latency. The increased scheduling latency may prevent the scheduler circuit from issuing all single-cycle-delayed producer instructions in the back-to-back clock cycles with the producer instructions.

[0009] Therefore, in the exemplary aspects disclosed herein, an operand pool cluster scheduler circuit (“scheduler circuit”) is provided in the instruction processing circuitry of the processor. The operand pool cluster scheduler circuit includes multiple operand pool reservation circuits, each operand pool reservation circuit having an allocated number of source operands for reserved instructions that must be ready before being issued. Instructions that must be ready for issuance with the same number of source operands are reserved (i.e., stored) in reservation entries in operand pool reservation circuits with the same allocated number of source operands. For example, consumer instructions that depend on two (2) source operands can be clustered together in the same operand pool reservation circuit, which is assigned to reserve and issue instructions with two (2) source operands. Similarly, consumer instructions that do not depend on any source operands (meaning these instructions will be ready for issuance without waiting for source operands to be ready) can be clustered together in the same operand pool reservation circuit, which is assigned to reserve and issue instructions without source operands. In this way, multiple reservation entries and associated comparator circuits in the operand pool cluster scheduler circuit are distributed across multiple operand pool reservation circuits to avoid or reduce the increase in the number and complexity of scheduling path connections in each reservation circuit. This avoids or reduces the increase in scheduling latency for a given number of reservation entries in the operand pool cluster scheduler circuit. In the non-cluster pick circuit, scheduling path connections are reduced for a given number of reservation entries because the signals used to issue scheduling instructions in each operand pool reservation circuit (e.g., wake-up signals, pick-up signals) do not necessarily have the same clock cycle latency to avoid impacting performance.

[0010] In this regard, in one exemplary aspect, a scheduler circuit is provided in a processor and configured to receive a plurality of instructions to be scheduled for execution, the plurality of instructions including producer instructions and consumer instructions. The scheduler circuit includes at least one operand pool reservation circuit allocated to store instructions having an allocated number of source operands. Each operand pool reservation circuit includes a plurality of reservation entries, each reservation entry configured to store an instruction to be published for execution, the instruction having a number of source operands equal to the allocated number of source operands for the operand pool reservation circuit. The scheduler circuit is configured to receive a consumer instruction from among the plurality of instructions based on a producer instruction from among the plurality of instructions. The scheduler circuit is further configured to store the received consumer instruction in a reservation entry from among the plurality of reservation entries in the operand pool reservation circuit of the at least one operand pool reservation circuit, the at least one operand pool reservation circuit having an allocated number of source operands equal to the number of unready source operands in the received consumer instruction. Each operand pool reservation circuit of at least one operand pool reservation circuit is configured to receive a wake-up signal from one or more wake-up signals, each wake-up signal being associated with one or more publish channel circuits in the processor. The wake-up signal includes at least one register tag indicating at least one source operand of at least one producer instruction published to one or more publish channel circuits. Each operand pool reservation circuit of at least one operand pool reservation circuit is further configured to compare the at least one register tag with a plurality of reservation entries in the operand pool reservation circuit. The operand pool reservation circuit allocates a number of source operands equal to the number of unready operands in the received consumer instructions. In response to at least one source register of a consumer instruction in a reservation entry among the plurality of reservation entries matching the at least one register tag, each operand pool reservation circuit of at least one operand pool reservation circuit is further configured to issue an instruction ready signal for the consumer instruction in the reservation entry to at least one pick circuit, the pick circuit being configured to issue a consumer instruction to be executed to a publish channel circuit among one or more publish channel circuits.

[0011] In another exemplary aspect, a method is provided for scheduling a plurality of instructions to be executed in an execution circuit in a processor, the plurality of instructions including producer instructions and consumer instructions. The method includes receiving a consumer instruction from among the plurality of instructions based on a producer instruction from among the plurality of instructions. The method further includes storing the received consumer instruction in a reservation entry from among a plurality of reservation entries in at least one operand pool reservation circuit, the at least one operand pool reservation circuit having a number of source operands allocated equal to the number of unread source operands in the received consumer instruction. Each operand pool reservation circuit in the at least one operand pool reservation circuit includes a plurality of reservation entries, each reservation entry being configured to store an instruction to be issued for execution, the number of unread source operands of the instruction being equal to the number of source operands allocated to the operand pool reservation circuit. The method further includes receiving a wake-up signal from one or more wake-up signals, each wake-up signal associated with one or more issue channel circuits in the processor, the wake-up signal including at least one register tag indicating at least one source operand of at least one producer instruction issued to the issue channel circuit in the one or more issue channel circuits. The method further includes comparing at least one register tag with a plurality of reservation entries in an operand pool reservation circuit, the operand pool reservation circuit having allocated the same number of source operands as the number of unread source operands in the received consumer instruction. The method further includes issuing an instruction ready signal for the consumer instruction in the reservation entry to at least one select circuit in response to at least one source register matching the at least one register tag in connection with a consumer instruction in one of the plurality of reservation entries, the at least one select circuit being configured to issue the consumer instruction to be executed to a select channel circuit of one or more select channel circuits.

[0012] After reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings, those skilled in the art will understand the scope of this disclosure and implement its additional aspects. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form part of this specification, illustrate several aspects of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0014] Figure 1 This is a schematic diagram of an exemplary processor-based system, which includes a processor having instruction processing circuitry including one or more instruction pipelines for processing computer instructions to be executed, wherein the instruction processing circuitry includes scheduler circuitry configured to reserve and schedule the issuance of instructions to be executed to execution circuitry.

[0015] Figure 2 It can be included in Figure 1 A schematic diagram of an exemplary non-cluster scheduler circuit in the instruction processing circuit, wherein the non-cluster scheduler circuit is configured to schedule the issuance of instructions to be executed by the execution circuit to the issuance channel;

[0016] Figure 3 It can be included in Figure 1 A schematic diagram of an exemplary operand pool cluster scheduler circuit in the instruction processing circuit, wherein the operand pool cluster scheduler circuit includes multiple operand pool reservation circuits, each operand pool reservation circuit being configured to cluster instructions with the same number of source operands for execution by the execution circuit, these source operands must be ready to be published to the publication channel by their respective pick circuits;

[0017] Figure 4 This is an explanation Figure 3 The exemplary process of allocating the operand pool cluster scheduler circuit to the operand pool reservation circuit and the flowchart of selecting instructions to the release channel for execution by the execution circuit, wherein the operand pool reservation circuit allocates multiple source operands prepared for these instructions to be released;

[0018] Figure 5 It can be included in Figure 1 A schematic diagram of another exemplary operand pool cluster scheduler circuit in the instruction processing circuit, wherein the operand pool cluster scheduler circuit includes a plurality of operand pool reservation circuits, wherein at least one of the operand pool reservation circuits has a reservation entry, the reservation entry having exchangeable real-time and non-real-time source register labels to avoid additional wake-up delay loss due to the issued instruction showing that the source operand is not ready in the same clock cycle;

[0019] Figure 6 yes Figure 5 A schematic diagram of an exemplary reservation entry in the operand pool reservation circuit of the operand pool cluster scheduler circuit, which enables the exchange of source register tags between the real-time source register tag circuit and the non-real-time source register tag circuit; and

[0020] Figure 7 This is an exemplary block diagram of a processor-based system, including a processor with instruction processing circuitry. The instruction processing circuitry includes an operand pool cluster scheduler circuit, which includes multiple operand pool reservation circuits. Each operand pool reservation circuit is configured to cluster instructions having the same number of source operands, which must be prepared to be published to a publication channel by their respective pick circuits for execution by the execution circuitry. The operand pool cluster scheduler circuit includes, but is not limited to, […]. Figure 3 and Figure 5 The operand pool cluster scheduler circuit in the middle. Detailed Implementation

[0021] Exemplary aspects disclosed herein include an operand pool instruction reservation cluster in a scheduler circuitry within a processor. The processor includes instruction processing circuitry comprising multiple instruction processing stages configured to pipeline the processing and execution of fetched instructions according to a data stream. Scheduler circuitry is included in the instruction processing stages of the instruction processing circuitry to schedule the issuance of instructions to be executed to the execution circuitry. The scheduler circuitry includes a reservation circuitry that controls the issuance of such instructions until their source operands are ready to be consumed. The scheduler circuitry also includes a pick circuitry comprising a comparator circuitry configured to compare register information received in a wake-up signal indicating which registers are available for consumption with the source operands of reserved instructions in the reservation circuitry to determine if any reserved instructions are ready to be issued. Once it is known that the necessary value for the source operand of an instruction will be available when the instruction is executed, the scheduler circuitry is responsible for issuing the instruction to the issuance channel for execution by the execution circuitry. Therefore, once it is known that the necessary produced value from the producer instruction will be available for consumption before the execution of the consumer instruction, the scheduler circuitry issues the consumer instruction.

[0022] Ideally, the scheduler circuit should be designed so that, for performance reasons, consumer instructions that rely on single-cycle-delayed producer instructions can be issued in back-to-back clock cycles with the producer instructions. The delay of a producer instruction is the number of clock cycles (“cycles”) after its issuance when its generated value will be available to the consumer instructions. It may also be desirable to design the scheduler circuit so that, for performance reasons, consumer instructions that rely on single-cycle-delayed producer instructions can be issued in back-to-back clock cycles with the producer instructions. It may also be desirable to increase the number of reserved entries in the scheduler circuit to improve scheduling performance, as increasing the number of reserved entries increases the likelihood that enough instructions will be ready to be issued in each issuance channel. However, increasing the number of reserved entries in the scheduler circuit increases the number and complexity of scheduling path connections in the scheduler circuit, thereby increasing scheduling delay. The increased scheduling delay may prevent the scheduler circuit from issuing all single-cycle-delayed producer instructions in the back-to-back clock cycles with the producer instructions.

[0023] Therefore, in the exemplary aspects disclosed herein, an operand pool cluster scheduler circuit (“scheduler circuit”) is provided in the instruction processing circuitry of the processor. The operand pool cluster scheduler circuit includes multiple operand pool reservation circuits, each operand pool reservation circuit having an allocated number of source operands for reserved instructions that must be ready before being issued. Instructions that must be ready for issuance with the same number of source operands are reserved (i.e., stored) in reservation entries in operand pool reservation circuits with the same allocated number of source operands. For example, consumer instructions that depend on two (2) source operands can be clustered together in the same operand pool reservation circuit, which is assigned to reserve and issue instructions with two (2) source operands. Similarly, consumer instructions that do not depend on any source operands (meaning these instructions will be ready for issuance without waiting for source operands to be ready) can be clustered together in the same operand pool reservation circuit, which is assigned to reserve and issue instructions without source operands. In this way, multiple reservation entries and associated comparator circuits in the operand pool cluster scheduler circuit are distributed across multiple operand pool reservation circuits to avoid or reduce the increase in the number and complexity of scheduling path connections in each reservation circuit. This avoids or reduces the increase in scheduling latency for a given number of reservation entries in the operand pool cluster scheduler circuit. In the non-cluster pick circuit, scheduling path connections are reduced for a given number of reservation entries because the signals used to issue scheduling instructions in each operand pool reservation circuit (e.g., wake-up signals, pick-up signals) do not necessarily have the same clock cycle latency to avoid impacting performance.

[0024] Before discussing an exemplary processor-based system including a processor, the processor includes operand pool cluster scheduler circuitry. This cluster scheduler circuitry includes multiple operand pool reservation circuits, each configured to cluster instructions with the same number of source operands, which must be ready to be published to a publication channel by their respective pick circuits for execution by the execution circuitry. Figure 3 (To begin), please refer to the following: Figures 1 to 2 The discussion includes processor-based systems that include non-operand pool cluster scheduler circuitry for scheduling instructions to be executed.

[0025] in this regard, Figure 1 This is a schematic diagram of an exemplary processor-based system 100 including processor 102. Processor 102 includes instruction processing circuitry 104, which includes scheduler circuitry 106 for scheduling instructions to be executed in processor 102. Processor 102 includes instruction processing circuitry 104, which includes one or more instruction pipelines I0-I for processing computer instructions for execution. NAs will be discussed in more detail below, instruction processing circuitry 104 includes scheduler circuitry 106, which is configured to reserve and schedule the issuance of instructions to be executed to execution circuitry 108. As an example, processor 102 may be an ordered or out-of-order processor (OoP). Instruction processing circuitry 104 includes instruction fetch circuitry 110, which is configured to fetch instruction 112 from instruction memory 114. As an example, instruction memory 114 may be provided in or as part of system memory in processor-based system 100. Instruction cache 116 may also be provided in processor 102 to cache instruction 112 fetched from instruction memory 114 to reduce timing latency in instruction fetch circuitry 110. In this example, the instruction fetching circuit 110 is configured to provide instruction 112, which is the fetched instruction 112F, as instruction stream 118 in instruction processing circuit 104 to one or more instruction pipelines I0-I before the fetched instruction 112F arrives at execution circuit 108 for execution. N Preprocessing is performed in China.

[0026] The instructions 112F extracted from instruction stream 118 include producer instructions and consumer instructions. The consumer instructions consume the value generated by instruction processing circuit 104 as a result of executing the producer instructions. Instruction pipeline I0-I N Different processing circuits or stages across instruction processing circuitry 104 are provided to preprocess and process the fetched instruction 112F in a series of steps that can be executed concurrently to increase throughput before the fetched instruction 112F is executed by execution circuitry 108. For example, a fetched store-based instruction 112F identified in instruction stream 118 as having a forward store-load can be identified as being forwarded to be consumed by the store-forward-load tracker circuitry 120 in instruction processing circuitry 104 before execution.

[0027] exist Figure 1 The instruction processing circuitry 104 of the processor 102 also provides a control flow prediction circuitry 122 (e.g., a branch prediction circuitry) to infer or predict the prediction result of the fetched conditional control instruction 112F (e.g., a conditional branch instruction), the effect of which is on the instruction pipeline I0-I NThe instruction control flow path of the instruction flow 118 processed in the instruction processing circuit 110. The instruction fetch circuit 110 can use the prediction of the control flow prediction circuit 122 to determine the next fetch instruction 112F to be fetched based on the predicted target address. The instruction processing circuit 104 also includes an instruction decoding circuit 124, which is configured to decode the fetch instruction 112F fetched by the instruction fetch circuit 110 into a decoded instruction 112D to determine the required instruction type and action. Encoding the required instruction type and action in the decoded instruction 112D can also be used to determine which instruction pipeline I0-I should place the decoded instruction 112D. N middle.

[0028] In this example, the decoded instruction 112D is placed in instruction pipeline I0-I. N The instruction is piped through one or more instruction pipelines and then provided to the renaming circuit 126 in the instruction processing circuit 104. The renaming circuit 126 is configured to determine if any register names in the decoded instruction 112D need to be renamed to break any register dependencies that would prevent parallel or out-of-order processing. The renaming circuit 126 is configured to invoke the rename access table circuit 128 to rename the logical source register operands and / or write the target register operands of the decoded instruction 112D to the available physical registers P0, P1, ..., P in the physical register file (PRF) 130. x The rename access table circuit 128 contains multiple register mapping entries 132(0)-132(P), each register mapping entry being mapped to (i.e., associated with) its respective logic registers R0-R1. p Each mapping entry in register mapping entries 132(0)-132(P) is configured to store the corresponding physical registers P0-P in PRF 130. x Logic registers R0-R p The corresponding mapping information for each physical register P0-P x Data entries 134(0)-134(X) are configured to store source register operands and / or destination register operands for decoding instruction 112D.

[0029] Figure 1 The instruction processing circuitry 104 in the processor 102 also includes a register access circuitry 136 preceding the scheduler circuitry 106. The register access circuitry 136 is configured to access physical registers P0-P in the PRF 130 based on register mapping entries 132(0)-132(P). x Register mapping entries 132(0)-132(P) are mapped to the logic registers R0-R in the renaming access table circuit 128 of the source register operands of the decoding instruction 112D. pThe register access circuit 136 is also configured to retrieve the generated value from the executed instruction 112E in the execution circuit 108. The register access circuit 136 is also configured to provide the generated value retrieved from the executed decoded instruction 112E as the source register operand for the decoded instruction 112D to be executed.

[0030] Furthermore, in the instruction processing circuit 104, the scheduler circuit 106 is provided in the instruction pipeline I0-I N It is also configured to store the decoding instruction 112D in a reserved entry until all source register operands for the decoding instruction 112D are available. For example, the scheduler circuit 106 is responsible for determining the release channel L0-L among the "K" release channels. K-1 Before the decoded consumer instruction 112D is sent to the execution circuit 108 for execution, the necessary values ​​of the operands of the decoded consumer instruction 112D are available. The scheduler circuit 106 sends the decoded instruction 112D, ready to be executed, to the execution circuit 108. This is done via channels L0-L. K-1 The number of entries is usually less than the number of reserved entries in scheduler circuit 106, therefore scheduler circuit 106 uses circuitry to distribute entries in distribution channels L0-L according to the distribution scheme. K-1 The middle dispatcher is ready to execute the decoding instruction 112D.

[0031] The publishing scheme can be based on the delay of the producer instruction that generates the value produced for the source operand of the decoded instruction 112D. For example, a producer instruction that can be executed by the execution circuit 108 in one (1) clock cycle and whose generated data is available is a single-clock-cycle delayed producer instruction. The execution circuit 108 may include multiple execution stages to execute producer instructions that require more than one (1) clock cycle to execute. The source operand of the decoded instruction 112D may include an immediate value, a value stored in memory, and a generated value from other decoded instructions 112D, which will be regarded as producer instructions to consumer instructions. The execution circuit 108 is configured to execute from the scheduler circuit 106 in publishing channels L0-L K-1 The decoding instruction 112D is issued in the instruction processing circuit 104. A write circuit 138 is also provided in the instruction processing circuit 104 to write back or commit the value generated from the executed instruction 112E to memory, such as PRF 130, cache memory or system memory.

[0032] Figure 2 It can be used as Figure 1A schematic diagram of an exemplary scheduler circuit 200 in the instruction processing circuit 104 of the instruction processing circuit 104 is provided to illustrate exemplary components of the scheduler circuit 200. In this example, the scheduler circuit 200 includes a reservation circuit 202, which includes a number of "M" reservation entries 204(0)-204(M-1). The reservation entries 204(0)-204(M-1) are configured to store received instructions in (one or more) instruction pipelines until they are ready for execution in the execution circuit 206, which may be... Figure 1 The execution circuit 108 is located in the reservation entry 204(0)-204(M-1). In this example, each reservation entry 204(0)-204(M-1) includes instruction fields INST(0)-INST(M-1), which are configured to store instructions to be issued received by the scheduler circuit 200. Each reservation entry 204(0)-204(M-1) also includes two (2) source register tag (SRT) circuits SRT(0)(1)-SRT(M-1)(2), each of which is configured to store a source register tag that identifies the source register operand in the corresponding instruction stored in the instruction fields INST(0)-INST(M-1) of the reservation entry 204(0)-204(M-1). For example, the SRT circuits SRT(0)(1)-SRT(M-1)(2) can be source physical register tag (SPRT) circuits used to identify the physical source register operands in the corresponding instructions stored in the instruction fields INST(0)-INST(M-1) of the reserved entries 204(0)-204(M-1) stored in the instruction field INST(0). The source operands of the instructions stored in the instruction fields INST(0)-INST(M-1) of the reserved entries 204(0)-204(M-1) are stored in the corresponding SRT circuits SRT(0)(1)-SRT(M-1)(2). The source register tag is used to identify the named register operands of the stored instructions, so it can be determined when the source register of the named source register operand in the consumer instructions stored in the reserved entries 204(0)-204(M-1) is ready to issue the instruction.

[0033] Scheduler circuit 200 is configured to issue ready-to-execute instructions to the corresponding execution channels E0-E in execution circuit 206. k-1 Coupled publishing channel L0-L K-1 One of the publishing channels. The execution circuit 206 is designed to receive and simultaneously execute on K publishing channels L0-L K-1 The system dispatches "K" instructions and provides K execution channels E0-E0. k-1To improve performance. Therefore, in this example, "M" refers to the command window size, and "K" refers to the release width or release channel L0-L. K-1 The number of producer instructions can be issued to execution circuit 206 for execution. If scheduler circuit 200 is included as... Figure 1 In the scheduler circuit 106, reserved entries 204(0)-204(M-1) will be configured to store entries from instruction pipelines I0-I before being passed to the execution circuit 108 for execution. N The decoding instruction 112D. Reserved entries 204(0)-204(M-1) store producer instructions and consumer instructions of producer instructions. Scheduler circuit 200 ensures that its consumer instructions are published on channels L0-L K-1 Before being published, producer instructions are published to the publication channel L0-L. K-1 The function is to be executed by the execution circuit 206. The scheduler circuit 200 is a synchronous circuit configured to operate and execute functions during the clock cycle of its processor.

[0034] Continue to refer to Figure 2 The scheduler circuit 200 also includes a selection circuit 208 configured to select instructions reserved in reserved entries 204(0)-204(M-1) when ready to publish. The selection circuit 208 is also coupled to K wake-up signals 214(0)-214(K-1), which are generated by K publish channel circuits 216(0)-216(K-1) in their respective publish channels L0-L0. K-1 Generated in [location]. Corresponding to the L0-L publishing channel. K-1 Each associated publishing channel circuit 216(0)-216(K-1) is configured to respond to publishing channels L0-L K-1 The producer instruction issued in the middle generates a corresponding wake-up signal 214(0)-214(K-1) among K wake-up signals 214(0)-214(K-1) on wake-up signal port 221. The wake-up signals 214(0)-214(K-1) may include corresponding source register tags (“register tags”) 218(0)-218(K-1) to identify the source register as ready to publish or not ready to publish. The register tags 218(0)-218(K-1) may be source physical register tags, which identify the physical source register as ready to publish or not ready to publish. When the scheduler circuit 200 is in the publishing channel L0-L K-1 When a producer instruction is issued, it means that the producer instruction will be executed by the execution circuit 206, and the data generated by its execution will be stored in the source register, which can be consumed by any consumer instruction of the producer instruction.

[0035] The content addressable memory (CAM) circuit 210 in the reservation circuit 202 is configured to compare the register tags 218(0)-218(K-1) in the received wake-up signals 214(0)-214(K-1) for producer instructions that issue up to M instructions in the respective reservation entries 204(0)-204(M-1). The CAM circuit 210 determines whether all source registers are ready based on the named source register operands of a given instruction reserved in the instruction fields INST(0)-INST(M-1) such that the instruction is ready to be issued for execution. For example, if the instruction reserved in the instruction fields INST(0)-INST(M-1) of the instruction reservation entries 204(0)-204(M-1) is a consumer of a previously issued producer instruction, the issuance of its producer instruction is indicated by the register tags 218(0)-218(K-1) in the wake-up signals 214(0)-214(K-1), and the issuance of its producer instruction indicates that data from the producer instruction will become available and thus the consumer instruction that consumes the source registers identified by the register tags 218(0)-218(K-1) is ready. The reservation circuit 202 is configured to generate M instruction ready signals indicating whether the instructions in the respective reservation entries 204(0)-204(M-1) are ready to be issued based on the comparison of the wake-up signals 214(0)-214(K-1) for the issued producer instructions with the M instructions in the respective reservation entries 204(0)-204(M-1).

[0036] Continuing reference Figure 2 , the pick circuit 208 includes K pick circuits 222(0)-222(K-1), which are configured to receive the M instruction ready signals 220(0)-220(M-1) from the reservation circuit 202 and generate the corresponding K issue channel pick signals 224(0)-224(K-1) to identify the respective instructions in the reservation entries 204(0)-204(M-1) that are ready to be issued, indicated as issue ready by the issue status. If K is not equal to M, providing the M instruction ready signals 220(0)-220(M-1) to the K pick circuits 222(0)-222(K-1) involves signal multiplexing. Typically, K < M because the execution circuit (such as Figure 2 the execution circuit 206 in) is generally not designed to be able to execute M instructions simultaneously, and it may not be necessary to achieve the desired performance because the M instructions may not be ready to be issued in every clock cycle. The K issue channel pick signals 224(0)-224(K-1) are provided to the K issue arbitration circuits 226(0)-226(K-1) in the reservation circuit 202, and each issue channel pick signal 224(0)-224(K-1) is coupled to the respective issue channel L0-LK-1 Each of the publication arbitration circuits 226(0)-226(K-1) is coupled to a reserved entry 204(0)-204(M-1), such that M reserved entries 204(0)-204(M-1) are multiplexed into K publication arbitration circuits 226(0)-226(K-1) (if K is not equal to M). The publication arbitration circuits 226(0)-226(K-1) are configured to select an instruction from the reserved entries 204(0)-204(M-1) and publish it in response to an instruction identified in the corresponding publication channel selection signal 224(0)-224(K-1) having a publication-ready state. Each of the publication arbitration circuits 226(0)-226(K-1) is configured to provide the identified instruction to be published from the received corresponding publication channel selection signal 224(0)-224(K-1) to the corresponding relevant publication channel L0-L. K-1 Then the identified instruction is provided to the corresponding execution channel L0-L in the execution circuit 206. K-1 It has been executed.

[0037] Return to reference Figure 2 It might be desirable to increase "M" to provide more reserved entries in scheduler circuit 200 and a larger "K" release width to improve performance. A key part of the wake-up design in scheduler circuit 200 is that consumer instructions, relying on single-cycle delay producer instructions, can be released by scheduler circuit 200 in back-to-back clock cycles with the producer instructions. Figure 2 In the scheduler circuit 200, there are three main components that affect the wake-up timing path of a single-cycle wake-up timing path. They are: (1) due to the release lane L0-L K-1 Up to K producer instructions were issued, sending K wake-up signals 214(0)-214(K-1) from K publish channels L0-L K-1 (2) The scheduling delay of the scheme in which the selection circuit 208 selects up to K instructions to be issued from M entries of the reserved entries 204(0)-204(M-1) in the reserved circuit 202; and (3) The scheduling delay of the scheme in which the selection circuit 208 selects up to K instructions to be issued from M entries of the reserved entries 204(0)-204(M-1) in the reserved circuit 202; and (4) The scheduling delay of the scheme in which the selection circuit 208 selects K issuance channel selection signals 224(0)-224(K-1) for the M entries in the reserved circuit 202 so that up to K instructions from the M reserved entries 204(0)-204(M-1) will be issued in the K issuance channels L0-L1. K-1 Release delay.

[0038] It may be desirable to increase the instruction window size M in reserved circuit 202. A larger instruction window size M allows for better control over the K publishing channels L0-L. K-1 The greater the likelihood that the system will always have K available instructions ready to be issued to maximize the efficiency of executing circuit 206, the better. However, increasing... Figure 2 Increasing the instruction window size M in the scheduler circuit 200 to improve performance may adversely affect the latency of all three (3) components in the wake-up timing path in the scheduler circuit 200. Increasing the instruction window size M increases the number of endpoints to which K wake-up signals 214(0)-214(K-1) need to be broadcast in the pick circuit 208, which can increase the capacitive and resistive loads in the wake-up timing path, thereby increasing latency. In addition, increasing the number of K broadcast channels L0-L K-1 The number of loads increases the number of wake-up signals 214(0)-214(K-1) coupled to the selection circuit 208, which in turn increases the capacitive and resistive loads on the selection circuit 208 and the capacitive and resistive loads in the wake-up timing path, thus increasing the delay of the selection circuit 208.

[0039] Figure 3 This is a schematic diagram of an instruction processing circuit 300 including an operand pool cluster scheduler circuit 302 (“scheduler circuit 302”), which includes multiple operand pool reservation circuits 304(0)-304(2). Each operand pool reservation circuit 304(0)-304(2) is configured to cluster instructions including producer and consumer instructions, which have the same number of source operands that must be ready to be published. Figure 3 The instruction processing circuit 300 supports an instruction set architecture (ISA) that allows instructions to have up to two (2) source operands (as a non-limiting example). As will be discussed in more detail below, each operand pool reservation circuit 304(0)-304(2) is allocated multiple source operands. The operand pool reservation circuits 304(0)-304(2) are configured to cluster instructions into corresponding reservation entries that have the same number of source operands that must be ready to schedule instructions to the K-1 release channels L0-L in the corresponding K-1 release channel circuits 306(0)-306(K-1). K-1 To be executed by the corresponding execution channel E0-E k-1 The corresponding execution circuits 308(0)-308(2) in the circuit are executed. This is consistent with... Figure 2 The scheduler circuit 200 in the middle is the opposite. Figure 2The scheduler circuit 200 includes a reservation circuit 202 for storing all instructions without considering clustering instructions with the same number of source operands. In this way, as an example, the total number of reservation entries in the scheduler circuit 302 can be distributed across operand pool reservation circuits 304(0)-304(2) to avoid or reduce the increase in the number of scheduling path connections and the increased complexity of each operand pool reservation circuit 304(0)-304(2). For a given total number of reservation entries, this avoids increasing or reducing scheduling latency in the scheduler circuit 302. Note that the number of publish channels L0-L2 and execute channels E0-E2 need not be the same as the number of provided operand pool reservation circuits 304(0)-304(2).

[0040] For example, Figure 3 The operand pool reservation circuit 304(0) in the scheduler circuit 302 is allocated to reserve instructions with zero (0) source operands or no source operands. Instructions reserved in the operand pool reservation circuit 304(0) are immediately ready for publication without comparing the source operands of the reserved instruction with register tags 310(0)-310(2) in the wake-up signals 312(0)-312(2) on the wake-up bus 314, which indicate that the source registers generated by the producer instruction are thus ready to be consumed by the consumer instruction. In this example, the operand pool reservation circuit 304(1) is allocated to reserve instructions with one (1) source operand. Once the source operands of an instruction are ready as determined by register labels 310(0)-310(2) in wake-up signals 312(0)-312(2), the instruction reserved in operand pool reservation circuit 304(1) is ready to be issued, and register labels 310(0)-310(2) indicate that the source register generated by the producer instruction is ready to be consumed by the consumer instruction. In this example, operand pool reservation circuit 304(2) is allocated to reserve an instruction with two (2) source operands. Once both source operands of the instruction are ready, as determined by register labels 310(0)-310(2) in wake-up signals 312(0)-312(2) indicating that the source register generated by the producer instruction is ready to be consumed by the consumer instruction, the instruction reserved in operand pool reservation circuit 304(2) is ready to be issued. If including Figure 3 The instruction processing circuit 300 in the processor supports an instruction set architecture (ISA) that allows the execution of instructions with more than three (3) source operands in the same clock cycle, and can also provide additional operand pool reservation circuitry to support the allocation of such a number of operands.

[0041] The number of comparator circuits in the operand pool reservation circuits 304(0)-304(2) in the reservation entry distribution scheduler circuit 302 can be reduced by including them in the respective operand pool reservation circuits 304(0)-304(2). As discussed in more detail below, the comparator circuits can be included in the reservation entries 320(0)-320(P0), 330(1)-330(P1), 338(0)-338(P2) in the respective operand pool reservation circuits 304(0)-304(2) to compare the register tags 310(0)-310(2) in the wake-up signals 312(0)-312(2) with the source operands of the reserved instructions in the respective reservation entries 320(0)-320(P0), 330(1)-330(P1), 338(0)-338(P2) to determine whether the instructions are ready to be issued. For example, no comparator circuit is needed in the reserved entries 320(0)-320(P0) in the operand pool reservation circuit 304(0) because the operand pool reservation circuit 304(0) is allocated to reserve instructions without source operands and can therefore be issued immediately. Therefore, for instructions reserved in the operand pool reservation circuit 304(0), no source operand comparison is required. As another example, only one (1) comparator circuit can be provided in each reserved entry 330(1)-330(P1) in the operand pool reservation circuit 304(1) because the operand pool reservation circuit 304(1) is allocated to reserve instructions with only one (1) source operand. There is no need to compare the two source operands of the instruction reserved in the reserved entries 330(1)-330(P1) of the operand pool reservation circuit 304(1) with the register labels 310(0)-310(2) of the wake-up signals 312(0)-312(2). For instructions with two (2) source operands, operand pool reservation circuit 304(2) is provided, each of which may have two comparator circuits in its reserved entries 338(0)-338(P2), such that the two source operands of such an instruction to be issued can be compared with the register labels 310(0)-310(2) of the wake-up signals 312(0)-312(2). If the source operands of its producer instruction are ready to be consumed after the producer instruction is executed, the instruction allocated to each operand pool reservation circuit in operand pool reservation circuit 304(0)-304(2) can be issued within a single clock cycle delay.

[0042] Therefore, by distributing the reservation entries 320(0)-320(P0), 330(1)-330(P1), and 338(0)-338(P2) across the corresponding operand pool reservation circuits 304(0)-304(2) in the scheduler circuit 302, the number of reservation entries 320(0)-320(P0), 330(1)-330(P1), and 338(0)-338(P2), which may include two comparator circuits, is reduced. This is contrary to the possibility that all reservation entries in a non-clustered reservation circuit must be able to provide all numbers of source operands for the reservation instruction. Figure 3 As shown, the wake-up bus 314 does not drive the operand pool reservation circuit 304(0) at all. As discussed in more detail below, the wake-up bus 314 drives only P1+1 comparator circuits in the operand pool reservation circuit 304(1), which is equal to the number of reservation entries 330(1)-330(P1) in the operand pool reservation circuit 304(1). The wake-up bus 314 drives 2×P2+1 comparator circuits in the operand pool reservation circuit 304(2), which is equal to the two comparator circuits for each reservation entry 338(1)-338(P2) in the operand pool reservation circuit 304(2). Therefore, the operand pool reservation circuits 304(0)-304(2) can have a total of (1×(P1+1))+(2×(P2+1))) comparator circuits. If all reserved entries 320(0)-320(P0), 330(0)-330(P1), and 338(0)-338(P2) are provided in a single, non-clustered reserved circuit, for example in Figure 2 In the scheduler circuit 200, the wake-up bus 314 may have to drive the 2×((P0+1)+(P1+1)+(P2+1)) comparator circuit in the operand pool reservation circuit 304(2), which is equal to the two comparator circuits of each reservation entry 338(1)-338(P2) in the operand pool reservation circuit 304(2).

[0043] Continue to refer to Figure 3 The scheduler circuit 302 is configured to receive instruction 316 from the instruction processing circuit 300. For example, Figure 3 The scheduler circuit 302 in the middle can be provided as Figure 1The scheduler circuit 106 in the processor 102 fetches instructions 112 to be decoded and executed. Instruction 316 may include producer instructions and consumer instructions with named source operands that point to source registers storing values ​​produced by the execution of the producer instructions. Scheduler circuit 302 is configured to store received instructions 316 into operand pool reservation circuits 304(0)-304(2) based on the number of source operands in instructions 316. In this example, if instruction 316 has no source operands, scheduler circuit 302 stores instruction 316 as instructions 318(0)-318(P0) in available reservation entries 320(0)-320(P0) in the operand pool reservation circuit 304(0) allocated to reserved instructions without source operands. Furthermore, if it is known that all source operands are ready, such as direct source operands, then the scheduler circuit 302 can store instruction 316 as instructions 318(0)-318(P0) in available reserved entries 320(0)-320(P0) in the operand pool reservation circuit 304(0). The scheduler circuit 302 can, as in... Figure 1 The processor 102 consults the rename access table circuit 128 to determine whether the received instruction 316 has a source operand that is ready.

[0044] Ready indicators 322(0)-322(P0) are set to the ready state in reserved entries 320(0)-320(P0) (e.g., logic "0" or "1" can indicate the ready state, and the opposite logic state can indicate the not-ready state) to indicate that the reserved instruction in reserved entries 320(0)-320(P0) is ready to be published. Operand pool reservation circuit 304(0) is not coupled to wake-up bus 314 because it is not necessary to access register tags 310(0)-310(2) to determine whether the source register operand of instruction 316 reserved in operand pool reservation circuit 304(0) is ready to be consumed. Instruction 316 reserved in operand pool reservation circuit 304(0) is ready to be picked by pick pool 0 circuit 324(0), and the instruction will be published by publish arbitration circuits 326(0)-326(2) to the corresponding publish channel L0-L. K-1 The release channel circuits 306(0)-306(2) are to be executed by the corresponding execution circuits 308(0)-308(K-1).

[0045] An instruction ready signal 335(0) is generated by operand pool reservation circuit 304(0) to indicate that the corresponding instruction 318(0)-318(P0) is ready to be selected for publication. In response to instruction ready signal 335(0), selection pool 0 circuit 324(0) is configured to select such instruction 318(0)-318(P0) to be published to publication arbitration circuits 326(0)-326(2) for publication to publication channels L0-L. K-1 The selection pool 0 circuit 324(0) is configured to issue a channel selection signal 337(0) to the issuing arbitration circuits 326(0)-326(2) to indicate that the corresponding instruction 318(0)-318(P0) is ready to be issued.

[0046] Continue to refer to Figure 3 If the received instruction 316 has one (1) unready source operand, the scheduler circuit 302 reserves instruction 316 in the operand pool reservation circuit 304 (1) for reserved instructions with one (1) source operand. Instruction 316 is reserved as instructions 328 (0)-328 (P1) in the available reservation entries 330 (0)-330 (P1) in the operand pool reservation circuit 304 (1). The scheduler circuit 302 can consult as follows Figure 1 The rename access table circuit 128 shown determines whether the received instruction 316 has a source operand. Each reservation entry 330(0)-330(P1) also includes source register tag circuits 332(0)-332(P1), which are configured to store source register tags that identify the source register operand of the reservation instruction 328(0)-328(P1) reserved in the corresponding reservation entry 330(0)-330(P1). If the source operand of the reservation instruction 328(0)-328(P1) in reservation entries 320(0)-320(P1) is ready, then the corresponding ready indicator 334(0)-334(P1) is also in each reservation entry 330(0)-330(P1) to store the ready state (e.g., a logical "0" or "1" can indicate the ready state, and the opposite logical state can indicate the not-ready state), and therefore the corresponding reservation instruction 328(0)-328(P1) is ready to be issued. In this example, each source register tag circuit in source register tag circuits 332(0)-332(P1) is coupled to wake-up bus 314 and configured to receive wake-up signals 312(0)-312(2), which may include register tags 310(0)-310(2), indicating which source registers will be published on publish channels L0-L1. K-1The producer instructions issued in the middle are generated. For example, the source register tag circuits 332(0)-332(P1) can be content addressable memory (CAM) circuits. If the comparison of the source register indicated in the register tag 310(0)-310(2) in the received wake-up signal 312(0)-312(2) matches the source register tag of the source register tag circuit 332(0)-332(P1) for the corresponding reserved instruction 328(0)-328(P1) in the reserved entry 330(0)-330(P1), then the operand pool reservation circuit 304(1) is configured to set the corresponding ready indicator 334(0)-334(P1) to the ready state to indicate that the source operand of the corresponding instruction 328(0)-328(P1) is ready to be consumed.

[0047] An instruction ready signal 335(1) is generated by operand pool reservation circuit 304(1) to indicate that the corresponding instruction 328(0)-328(P1) is ready to be selected for publication. In response to instruction ready signal 335(1), selection pool 1 circuit 324(1) is configured to select such instruction 328(0)-328(P1) to be published to publication arbitration circuits 326(0)-326(2) for publication to publication channels L0-L. K-1 The selection pool 1 circuit 324(1) is configured to issue a channel selection signal 337(1) to the issuing arbitration circuits 326(0)-326(2) to identify the corresponding instruction 328(0)-328(P1) ready for issuance.

[0048] If the comparison of the source register indicated in register tags 310(0)-310(2) in the received wake-up signals 312(0)-312(2) does not match the source register tag circuit 332(0)-332(P1) for the corresponding reserved instruction 328(0)-328(P1) in the reserved entries 330(0)-330(P1), then the operand pool reserved circuit 304(1) is configured to set or keep the corresponding ready indicator 334(0)-334(P1) in a not ready state to indicate that the corresponding instruction 328(0)-328(P1) is not yet ready to be issued. Such an instruction 328(0)-328(P1) will remain reserved in its corresponding reserved entry 330(0)-330(P1) until it is ready to be issued.

[0049] Continue to refer to Figure 3In this example, if the received instruction 316 has two (2) unprepared source operands, the scheduler circuit 302 reserves instruction 316 in the operand pool reservation circuit 304 (2) for reserved instructions with two (2) source operands. Instruction 316 is reserved as instructions 336 (0)-336 (P2) in the available reservation entries 338 (0)-338 (P2) in the operand pool reservation circuit 304 (2). Each reservation entry 338(0)-338(P2) also includes a first source register tag circuit 340(0)-340(P2) and a second source register tag circuit 342(0)-342(P2), which are configured to store corresponding first and second source register tags. The first and second source register tags identify the first and second source register operands of the reservation instructions 336(0)-336(P2) reserved in the corresponding reservation entry 338(0)-338(P2). If the corresponding first and second source register operands of reservation instructions 336(0)-336(P2) in reservation entries 338(0)-338(P2) are ready, then the ready state is also stored in the corresponding ready indicators 344(0)-344(P2) and 346(0)-346(P2) in each reservation entry 338(0)-338(P2). (For example, a logic "0" or "1" can indicate a ready state, and the opposite logic state can indicate a not-ready state.) If both source operands of reservation instructions 336(0)-336(P2) are ready, then the corresponding reservation instructions 336(0)-336(P2) are ready to be issued. In this example, each of the source register tag circuits 340(0)-340(P2) and 342(0)-342(P2) is coupled to the wake-up bus 314 and configured to receive wake-up signals 312(0)-312(2). The wake-up signals 312(0)-312(2) may include register tags 310(0)-310(2), which indicate which source registers will be generated by the release channels L0-L1. K-1 The producer instructions issued in the middle are generated.

[0050] For example, the source register tag circuits 340(0)-340(P2) and 342(0)-342(P2) can be CAM circuits. If the comparison of the source register indicated in the register tag 310(0)-310(2) in the received wake-up signal 312(0)-312(2) matches the source register tag of the source register tag circuits 340(0)-340(P2) and 342(0)-342(P2) for the corresponding reservation instruction 336(0)-336(P2) in the reservation entry 338(0)-338(P2), then the operand pool reservation circuit 304(2) is configured to set the corresponding ready indicators 344(0)-344(P2) and 346(0)-346(P2) to the ready state to indicate that such a corresponding source operand is ready to be consumed. At this point, once both source operands of instruction 336(0)-336(P2) are ready, as indicated by their corresponding ready indicators 344(0)-344(P2) and 346(0)-346(P2), the selection pool 2 circuit 324(2) is configured to select instruction 336(0)-336(P2) to be published to the publication arbitration circuit 326(0)-326(2) for publication to the publication channel L0-L. K-1 The instruction ready signal 335(2) is generated by the operand pool reservation circuit 304(2) to indicate that the corresponding instruction 336(0)-336(P2) is ready to be selected for publication. In response to the instruction ready signal 335(2), the selection pool 2 circuit 324(2) is configured to select such instructions 336(0)-336(P2) to be published to the publication arbitration circuit 326(0)-326(2) for publication to the publication channels L0-L. K-1 The selection pool 2 circuit 324(2) is configured to issue a channel selection signal 337(2) to the issuing arbitration circuits 326(0)-326(2) to identify the corresponding instruction 336(0)-336(P2) ready for issuance.

[0051] If the comparison of the source register indicated in register label 310(0)-310(2) in the received wake-up signal 312(0)-312(2) does not match the first or second source register label in the corresponding first or second source register label circuit 340(0)-340(P2), 342(0)-342(P2) for the corresponding reserved instruction 336(0)-336(P2) in the reserved entry 338(0)-338(P2), then the operand pool reserved circuit 304(2) is configured to set or keep the corresponding first and second ready indicators 344(0)-344(P2), 346(0)-346(P2) set to an unready state to indicate that such corresponding instruction 336(0)-336(P2) is not yet ready to be issued. Such instructions 336(0)-336(P2) will remain reserved in their respective reserved entries 338(0)-338(P2) until they are ready for release.

[0052] Figure 4 This is an explanation Figure 3 The scheduler circuit 302 in the instruction processing circuit 300 is allocated to the operand pool reservation circuits 304(0)-304(2) and selects such instructions to enter the issue channels L0-L. K-1 In the flowchart of the exemplary process 400, operand pool reservation circuits 304(0)-304(2) are allocated to multiple source operands that must be prepared for instructions to be issued. Process 400 includes a scheduler circuit 302 receiving a consumer instruction 316 (or a producer instruction 316) among multiple instructions 316. Figure 4 (Box 402 in the middle). Process 400 also includes a scheduler circuit 302 storing the received consumer instruction 316 in at least one operand pool reservation circuit 304(0)-304(2) in a plurality of reservation entries 320(0)-320(P0), 330(0)-330(P1), 338(0)-338(P2). At least one operand pool reservation circuit 304(0)-304(2) is allocated with the same number of source operands as the number of source operands in the received consumer instruction 316. Figure 4(Box 402 in the middle). Process 400 also includes scheduler circuit 302 receiving one or more wake-up signals 312(0)-312(2), each wake-up signal being associated with one or more publishing channel circuits 306(0)-306(2), the wake-up signals 312(0)-312(2) including at least one register tag 310(0)-310(2), the at least one register tag 310(0)-310(2) indicating at least one source operand of at least one producer instruction 316 published to one or more publishing channel circuits 306(0)-306(2). Figure 4 (Box 406 in the middle). Process 400 also includes scheduler circuit 302 comparing at least one register tag 310(0)-310(2) with a plurality of reserved entries 320(0)-320(P0), 330(0)-330(P1), 338(0)-338(P2) in operand pool reservation circuit 304(0)-304(2), which is allocated with the same number of source operands as the number of source operands in the received consumer instruction 316. Figure 4 (Box 408 in the middle). Process 400 also includes, in response to at least one source register of consumer instruction 316 in one of the plurality of reservation entries 320(0)-320(P0), 330(0)-330(P1), 338(0)-338(P2) being matched with at least one register tag 310(0)-310(2), scheduler circuit 302 directing at least one pick pool circuit 324(0)-310(2) to at least one pick pool circuit 324(0)-310(2). 24(2) Issue instruction ready signals 335(0)-335(2) for consumer instruction 316 in reserved entries 320(0)-320(P0), 330(0)-330(P1), 338(0)-338(P2), the at least one pick pool circuit 324(0)-324(2) is configured to issue the consumer instruction 316 to be executed to one or more issue channel circuits 306(0)-306(K-1). Figure 4 (in box 410).

[0053] exist Figure 3In the scheduler circuit 302, the source register tag circuits 340(0)-340(P2) and 342(0)-342(P2) in the operand pool reservation circuit 342(2) for instructions with two (2) source operands are both "real-time". This means that the source register tag circuits 340(0)-340(P2) and 342(0)-342(P2) are both coupled to the same wake-up bus 314, such that the source register tag circuits 340(0)-340(P2) and 342(0)-342(P2) compare their respective stored source register tags with the register tags 310(0)-310(2) in the wake-up signal 312(0)-312(2) in the same clock cycle as the generated wake-up signal 312(0)-312(2). This has the advantage that the scheduler circuit 302 can issue two (2) source operand instructions when its two source operands are ready in the same clock cycle. However, this comes at the cost of each reservation entry 338(0)-338(P2) in the operand pool reservation circuit 304(2), which has two corresponding source register tag circuits 340(0)-340(P2) and 342(0)-342(P2) coupled to the wake-up bus 314, thereby increasing the capacitive load on the wake-up bus 314. This can increase wake-up latency when the two source operands of the two source operand reservation instructions 336(0)-336(P2) in the operand pool reservation circuit 304(2) are frequently not ready within the same clock cycle. For example, such source operand reservation instructions 336(0)-336(P2) may rely on a multi-cycle producer instruction that does not generate source operands in the same clock cycle during execution.

[0054] Therefore, in the alternative operand pool reserved circuit design, Figure 3Multiple operand pool reservation circuits in the scheduler circuit 302, such as operand pool reservation circuit 304(2), can be designed such that only one of the first and second source register tag circuits 340(0)-340(P2) and 342(0)-342(P2) in each reservation entry 338(0)-338(P2) is "real-time," meaning it is coupled to the wake-up bus 314 to receive non-delayed wake-up signals 312(0)-312(2). For example, if the first source register tag circuit 340(0)-340(P2) is coupled to the wake-up bus 314, then the first source register tag circuit 340(0)-340(P2) can receive and perform a comparison of the register tag 310(0)-310(2) in the wake-up signal 312(0)-312(2) with its source register tag generated within the same clock cycle as the wake-up signal 312(0)-312(2). Then, if the second source register tag circuits 342(0)-342(P2) are coupled to the delayed wake-up bus, which delays the wake-up signals 312(0)-312(2) on the wake-up bus 314 by, for example, one (1) clock cycle, the second source register tag circuits 342(0)-342(P2) can receive and perform a comparison of register tags 310(0)-310(2) in the delayed wake-up signal. This has the benefit of reducing the capacitive load on the second source register tag circuits 342(0)-342(P2) coupled to the wake-up bus 314. For example, a delay circuit such as a flip-flop can be coupled to the wake-up bus 314 to generate a delayed wake-up signal on the delayed wake-up bus coupled to the second source register tag circuits 342(0)-342(P2).

[0055] On this point, Figure 5 This is a schematic diagram of an instruction processing circuit 500 including an operand pool cluster scheduler circuit 502 (“scheduler circuit 502”), which includes... Figure 3 The scheduler circuit 302 has multiple operand pool reserved circuits 304(0)-304(2). Figure 3 The scheduler circuit 302 and Figure 5 The common components among the scheduler circuits 502 are shown with common component numbers and therefore will not be described again here.

[0056] exist Figure 5In the scheduler circuit 502, an additional operand pool reservation circuit 304(3) is provided, which is also allocated to reservation instructions 316 having two (2) source operands. Except as described below, the operand pool reservation circuit 304(3) is similar to the operand pool reservation circuit 304(2), with one source tag register circuit in the source tag register circuit used to identify that the source operands of the reservation instructions in the operand pool reservation circuit 304(3) are real-time in the current clock cycle, while the other source tag register circuit is non-real-time in the current clock cycle.

[0057] refer to Figure 5 The instruction 316 reserved by the scheduler circuit 502 in the operand pool reservation circuit 304(3) is stored in the available reservation entries 506(0)-506(P3) in the operand pool reservation circuit 304(3). Each reservation entry 506(0)-506(P3) includes a first source register tag circuit 508(0)-508(P3) and a second source register tag circuit 510(0)-510(P3). The first source register tag circuit 508(0)-508(P3) and the second source register tag circuit 510(0)-510(P3) are each configured to store the corresponding first and second source register tags, which are identified in the corresponding reservation entry 506(0)-506(P3) (e.g., ...). Figure 2 The first and second source register operands of the reserved instructions 504(0)-504(P3) are reserved in the operand pool reservation circuit 304(2). For example, the first and second source register tag circuits 508(0)-508(P3) and 508(0)-508(P3) can be CAM circuits. If the corresponding first and second source operands of the reserved instructions 504(0)-504(P3) in the reserved entries 506(0)-504(P3) are ready in the reserved entry 506(0), the ready state is also stored in the corresponding ready indicators 512(0)-512(P3) and 514(0)-514(P3) in each reserved entry 506(0)-506(P3). (For example, logic "0" or "1" can indicate the ready state, and the opposite logic state can indicate the unready state.) If both source operands of the reservation instruction 504(0)-504(P3) are ready, then the corresponding reservation instruction 504(0)-504(P3) is ready to be issued.

[0058] exist Figure 5In the operand pool reservation circuit 304(3) of the scheduler circuit 502, only the first source register tag circuits 508(0)-508(P3) are coupled to the wake-up bus 314 to receive the wake-up signals 312(0)-312(2) within the same clock cycle in which the wake-up signals are generated. Therefore, the first source register tag circuits 508(0)-508(P3) are considered to be "real-time", which means that the first source register tag circuits 508(0)-508(P3) are able to compare the register tags 310(0)-310(2) in the wake-up signals 312(0)-312(2) with the first source register tags in the first source register tag circuits 508(0)-508(P3) within the same clock cycle in which the wake-up signals 312(0)-312(2) are generated. The second source register tag circuits 510(0)-510(P3) are coupled to delayed wake-up signals 312D(0)-312D(2) generated on the delayed wake-up bus 509 by, for example, a trigger delay circuit 511. In this example, the delay circuit 511 is configured to delay the wake-up signals 312(0)-312(2) by one (1) clock cycle to generate the delayed wake-up signals 312D(0)-312D(2). Therefore, the second source register tag circuits 510(0)-510(P3) are considered "non-real-time", meaning that the second source register tag circuits 510(0)-510(P3) cannot compare the register tags 310(0)-310(2) in the wake-up signals 312(0)-312(2) with the second source register tags in the first source register tag circuits 508(0)-508(P3) within the same clock cycle in which the wake-up signals 312(0)-312(2) are generated. The second source register tag circuit 510(0)-510(P3) can compare the register tag 310(0)-310(2) in the delayed wake-up signal 312D(0)-312D(2) with the second source register tag in the second source register tag circuit 510(0)-510(P3) in the next clock cycle after generating the wake-up signal 312(0)-312(2).

[0059] Therefore, if the comparison of the source register indicated in the register tags 310(0)-310(2) in the received wake-up signals 312(0)-312(2) matches the source register tag in the first source register tag circuit 508(0)-508(P3) for the corresponding reservation instruction 504(0)-504(P3) in the reservation entries 506(0)-506(P3), then the operand pool reservation circuit 304(3) is configured to set the corresponding ready indicator 512(0)-512(P3) to the ready state to indicate that the corresponding source operand is ready to be consumed. If the two source operands of such reserved instructions 504(0)-504(P3) are ready according to their ready indicators 512(0)-512(P3) and 514(0)-514(P3), then the selection pool 3 circuit 324(3) is configured to select such instructions 504(0)-504(P3) to be issued to the issuance arbitration circuits 326(0)-326(2) for issuance to the issuance channels L0-L. K-1 The instruction ready signal 335(3) is generated by the operand pool reservation circuit 304(3) to indicate that the corresponding instruction 504(0)-504(P3) is ready to be selected for publication. In response to the instruction ready signal 335(3), the selection pool 3 circuit 324(3) is configured to select such instructions 504(0)-504(P3) to be published to the publication arbitration circuits 326(0)-326(2) for publication to the publication channels L0-L. K-1 The selection pool 3 circuit 324(3) is configured to issue a channel selection signal 337(3) to the issuing arbitration circuits 326(0)-326(2) to identify the corresponding instruction 504(0)-504(P3) as ready to be issued.

[0060] Similarly, if the comparison of the source register indicated in the register tags 310(0)-310(2) in the received delayed wake-up signals 312D(0)-312D(2) matches the source register tag in the second source register tag circuit 510(0)-510(P3) for the corresponding reservation instruction 504(0)-504(P3) in the reservation entries 506(0)-506(P3), then the operand pool reservation circuit 304(3) is configured to set the corresponding ready indicator 514(0)-514(P3) to the ready state to indicate that the corresponding source operand is ready to be consumed. Similarly, if the two source operands of such reserved instructions 504(0)-504(P3) are ready according to their ready indicators 512(0)-512(P3) and 514(0)-514(P3), the selection pool 3 circuit 324(3) is configured to select such instructions 504(0)-504(P3) to be published to the publication arbitration circuit 326(0)-326(2) for publication to the publication channel L0-L. K-1 The instruction ready signal 335(3) is generated by the operand pool reservation circuit 304(3) to indicate that the corresponding instruction 504(0)-504(P3) is ready to be selected for publication. In response to the instruction ready signal 335(3), the selection pool 3 circuit 324(3) is configured to select such instructions 504(0)-504(P3) to be published to the publication arbitration circuits 326(0)-326(2) for publication to the publication channels L0-L. K-1 The selection pool 3 circuit 324(3) is configured to issue a channel selection signal 337(3) to the issuing arbitration circuits 326(0)-326(2) to indicate that the corresponding instruction 504(0)-504(P3) is ready to be issued.

[0061] Therefore, since the second source register tag circuits 510(0)-510(P3) are non-real-time and coupled to the delayed wake-up signal 312D(0)-312D(2) on the delayed wake-up bus 509, if both source operands of register tag 310(0)-310(2) become ready according to the register tag 310(0)-310(2) in the same clock cycle, the operand pool reservation circuit 304(3) cannot issue reservation instructions 504(0)-504(P3) in the current clock cycle. This is because the register tag 310(0)-310(2) will be delayed by one clock cycle from the arrival of the second source register tag circuit 510(0)-510(P3) due to the delayed wake-up signal 312D(0)-312D(2) with register tag 310(0)-312(2) generated by the delay circuit 511. This could result in a clock cycle loss when issuing reserved instructions 504(0)-504(P3) with both source operands ready in the same clock cycle. However, one advantage of the operand pool reservation circuit 304(3) is that it reduces the capacitive load that would increase the delay of the wake-up signals 312(0)-312 on the wake-up bus 314 by using the operand pool reservation circuit 304(3) on the wake-up bus 314, and thus increases the number of ready instructions issued by the scheduler circuit 502. The delay circuit 511 prevents the second source register tag circuits 510(0)-510(P3) in the operand pool reservation circuit 304(3) from increasing the capacitive load on the wake-up bus 314.

[0062] If the two source operands of the reserved instructions 504(0)-504(P3) in the operand pool reservation circuit 304(3) are not available in the same clock cycle, there are two possibilities regarding the order in which the source operands of the reserved instructions 504(0)-504(P3) are ready. One possibility is that the first source operand of the reserved instructions 504(0)-504(P3) to be ready is in the corresponding non-real-time second source register tag circuit 510(0)-510(P3). This means that the second source operand of the reserved instructions 504(0)-504(P3) to be ready to issue the reserved instructions 504(0)-504(P3) will be in the real-time first source register tag circuit 508(0)-508(P3). In this case, no issue clock cycle loss occurs because the reservation instructions 504(0)-504(P3) will be ready to be issued within the same clock cycle as the wake-up signals 312(0)-312(2), which include register tags 310(0)-310(2) that match the second operand of the reservation instructions 504(0)-504(P3) in the first source register tag circuit 508(0)-508(P3). The first source register tag circuit 508(0)-508(P3) does not receive the delayed wake-up signals 312D(0)-312D(2), and therefore in this example, the comparison of the second source operand in the wake-up signals 312(0)-312(2) can be executed within the same clock cycle as the wake-up signals 312(0)-312(2).

[0063] If the two source operands of the reserved instructions 504(0)-504(P3) in the operand pool reservation circuit 304(3) are unavailable in the same clock cycle, there is a second possibility for the order in which the source operands of the reserved instructions 504(0)-504(P3) are ready. The second possibility is that the first source operand of the reserved instructions 504(0)-504(P3) to be ready is in the corresponding real-time first source register tag circuit 508(0)-508(P3). This means that the second source operand of the reserved instructions 504(0)-504(P3) that needs to be ready to issue the reserved instructions 504(0)-504(P3) will be located in the non-real-time second source register tag circuit 510(0)-510(P3). This situation results in an additional release clock cycle loss because the second source operand of the reserved instructions 504(0)-504(P3) is in the non-real-time second source register tag circuit 510(0)-510(P3) if the second source operand is ready in a later clock cycle. As mentioned above, the second source register tag circuit 510(0)-510(P3) receives the delayed wake-up signal 312D(0)-312D(2), which in this example is delayed by one clock cycle. Therefore, in this case, the second source register tag circuit 510(0)-510(P3) is always in the subsequent clock cycle of comparing the register tag 310(0)-310(2) in the delayed wake-up signal 312D(0)-312D(2) to generate the register tag 310(0)-310(2) in the wake-up signal 312(0)-312D(2).

[0064] When the two source operands of the reservation instructions 504(0)-504(P3) in the operand pool reservation circuit 304(3) are unavailable in the same clock cycle, and the first source operand of the ready reservation instructions 504(0)-504(P3) is in the real-time first source register tag circuit 508(0)-508(P3), in order to remedy this additional release clock cycle loss in the second case, the operand pool reservation circuit 304(3) can be configured to exchange source register tags and their ready indicators between the first source register tag circuit 508(0)-508(P3) and the second source register tag circuit 510(0)-510(P3). Operand pool reservation circuit 304(3) can be configured in this second scenario to swap the first source register tag and its ready indicator that matches the first source operand of the ready reservation instruction 504(0)-504(P3) from the real-time first source register tag circuit 508(0)-508(P3) and ready indicator 512(0)-512(P3) to the corresponding non-real-time second source register tag circuit 510(0)-510(P3) and ready indicator 514(0)-514(P3). Similarly, the source register tag and its ready indicator of the second source operand of the reserved instruction 504(0)-504(P3) in the non-real-time second source register tag circuit 510(0)-510(P3) are swapped to the corresponding first source register tag circuit 508(0)-508(P3) and ready indicator 512(0)-512(P3). In this way, once the second source operand of the reservation instruction 504(0)-504(P3) is known to be ready via the register tags 310(0)-310(2) in the wake-up signals 312(0)-312(2), the first source register tag circuit 508(0)-508(P3) will be able to compare the source register tags of the second operand of the reservation instruction 504(0)-504(P3), which needs to be ready to be issued in the absence of a delay in the delayed wake-up signals 312D(0)-312D(2).

[0065] Figure 6 yes Figure 5A schematic diagram of an exemplary reservation entry 506 in the operand pool reservation circuit 304(3) of the scheduler circuit 502, which is capable of exchanging source register tags between a first source register tag circuit 508 and a second source register tag circuit 510. In this regard, the first source register tag circuit 508 includes a first source register tag field 600 configured to store a first source register tag SRT1. The second source register tag circuit 510 includes a second source register tag field 602 configured to store a first source register tag SRT1 in the reservation entry 506 (see...). Figure 5 The second source register tag SRT2 of the reserved instruction 504 is stored in the register. For example, the first source register tag SRT1 and the second source register tag SRT2 can be obtained by the scheduler circuit 502 from, for example, the first source register tag SRT1 and the second source register tag SRT2. Figure 1 The rename access table circuit 128 shown is accessed for reserved instruction 504.

[0066] The first source register tag field 600 is coupled to the second source register tag input 604 of the second source register tag field 602, and the second source register tag field 602 is coupled to the first source register tag input 606 of the first source register tag field 600 in a cross-coupled arrangement. The first source register tag circuit 508 also includes a first comparator circuit 608 coupled to the first source register tag field 600 and the wake-up bus 314. The first comparator circuit 608 is configured to, in response to a match between the first source register tag SRT1 stored in the first source register tag SRT1 and the register tags 310(0)-310(2) in the wake-up signals 312(0)-312(2) on the wake-up bus 314, pass the first source register tag SRT1 stored in the first source register tag field 600 to the second source register tag input 604 of the second source register tag field 602 to be stored in the first source register tag field 600. In this way, when the register tags 310(0)-310(2) in the wake-up signals 312(0)-312(2) of the first source register tag SRT1 in the first source register tag circuit 508 match, the first source register tag SRT1 and the second source register tag SRT2 are exchanged between the first register tag field 600 and the second source register tag field 602.

[0067] exist Figure 5In this example of the scheduler circuit 502, the operand pool reservation circuit 304(2) in the scheduler circuit 502 is optional because the operand pool reservation circuit 304(3) is capable of reserving instruction 316 with two (2) source operands. However, it may still be desirable to include the operand pool reservation circuit 304(2) in the scheduler circuit 502 because the aforementioned one-clock-cycle loss occurs in the operand pool reservation circuit 304(3) when the two source operands of instruction 316 become available in the same clock cycle. Because both the first source register tag circuits 340(0)-340(P2) and the second source register tag circuits 342(0)-342(P2) are "real-time," meaning both are coupled to the non-delayed wake-up bus 314 to receive non-delayed wake-up signals 312(0)-312(2), the operand pool reservation circuit 304(2) is able to issue reservation instructions 336(0)-336(P2), which have their two source operands available within the same clock cycle, but with a clock cycle loss. However, providing operand pool reservation circuit 304(2) provides additional circuitry in the scheduler circuit 502 and additional capacitive loading on the wake-up bus 314. Therefore, in one example, an operand pool reservation circuit 304(2) can be provided to have fewer reservation entries 338(0)-338(P2) in the third operand pool circuit 304(2) than reservation entries 506(0)-506(P3) (meaning P2 < P3). Therefore, Figure 5 The scheduler circuit 502 in the example can be configured with an allocation strategy to determine where the instruction 316 with two (2) named source operands in this example will be allocated between the operand pool reservation circuit 304 (2) and the third operand pool reservation circuit 304 (3).

[0068] In one allocation strategy, scheduler circuit 502 may be configured with a pool allocation strategy to determine whether the two source operands of the received instruction 316 will be ready to be issued in the same clock cycle. If so, the received instruction 316 can be allocated to operand pool reservation circuit 304 (3) to avoid clock cycle wake-up loss, since the first source register tag circuits 508 (0)-508 (P3) and the second source register tag circuits 510 (0)-510 (P3) are both real-time as described above. For example, instruction 316, which has a single clock cycle delay due to a producer instruction that relies on source operands of instruction 316 to produce instruction 316 in a single clock cycle, will make its two source operands available in the same clock cycle. However, if scheduler circuit 502 determines that the two source operands of the received instruction 316 will not be ready to be issued in the same clock cycle, scheduler circuit 502 can allocate instruction 316 to operand pool reservation circuit 304 (2) and still avoid clock cycle wake-up loss, since only one source operand of instruction 316 will be ready at a time.

[0069] The scheduler circuit 502 can also be configured with a pool allocation strategy to allocate instructions 316 that only have time-critical loads dependent on a single clock cycle producer instruction to the operand pool reservation circuit 304(3). Alternatively, the scheduler circuit 502 can be configured to allocate instructions 316 that do not have time-critical loads (even if dependent on a single clock cycle producer instruction) to the operand pool reservation circuit 304(2). Allocating two source operand instructions to the operand pool reservation circuit 304(2) will not result in failure, but will only result in a clock cycle wake-up penalty if both source operands become available in the same clock cycle.

[0070] In another example, scheduler circuit 502 may also be configured with a pool allocation strategy to allocate instruction 316, which is a branch instruction dependent on a single-clock-cycle producer instruction, to operand pool reservation circuit 304 (3). It may be desirable to issue branch instructions with the shortest possible wake-up latency, as branch instructions may have conditional branches that must be resolved during execution, where reduced latency has a significant impact on refresh operations if the conditional branches are mispredicted. Scheduler circuit 502 may be configured to allocate instruction 316, which is not a branch instruction, to operand pool reservation circuit 304 (2), even if the instruction depends on a single-clock-cycle producer instruction. Allocating two source operand instructions to operand pool reservation circuit 304 (2) will not result in failure, but will only result in a clock-cycle wake-up penalty if both source operands become available in the same clock cycle.

[0071] Figure 7This is a block diagram of an exemplary processor-based system 700 including a processor 702 (e.g., a microprocessor). The processor 702 includes instruction processing circuitry 704, which includes operand pool scheduler circuitry 706. Each operand pool reservation circuit includes multiple operand pool reservation circuits, each configured to group together instruction sets having the same number of source operands. These instructions must be ready to be issued to a release channel by a corresponding pick circuit for execution by the execution circuitry. For example, Figure 7 The processor 702 in the middle can be Figure 1 The processor 102 includes an instruction processing circuit 704, which in turn includes an operand pool scheduler circuit 706. As a non-limiting example, the operand pool scheduler circuit 706 may be... Figure 3 and 5 The processor-based system 700 may be any of the operand pool scheduler circuits 302 and 502. The processor-based system 700 may be one or more circuits included in an electronic board, such as a printed circuit board (PCB), server, personal computer, desktop computer, laptop computer, personal digital assistant (PDA), computing board, mobile device, or any other device, and may represent, for example, a server or a user's computer. In this example, the processor-based system 700 includes a processor 702. Processor 702 represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, etc. More specifically, processor 702 may be an EDGE instruction set microprocessor, or other processor implementing an instruction set that supports explicit consumer naming for communicating the produced values ​​generated by executing producer instructions. Processor 702 is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, processor 702 includes an instruction cache 708, a temporary fast-access memory storage for instructions accessible to instruction processing circuitry 704. Instructions fetched or prefetched from memory (such as system memory 710) via system bus 712 are stored in instruction cache 708. The instruction processing circuit 704 is configured to process instructions fetched into the instruction cache 708 and process the instructions for execution.

[0072] Processor 702 and system memory 710 are coupled to system bus 712 and can interconnect peripheral devices included in processor-based system 700. Processor 702 is known to communicate with these other devices by exchanging address, control, and data information on system bus 712. For example, processor 702 can transmit bus transaction requests to memory controller 714 in system memory 710 (as an example of a slave device). Although Figure 7Not shown, but multiple system buses 712 may be provided, each forming a different architecture. In this example, the memory controller 714 is configured to provide memory access requests to the memory array 716 in the system memory 710. The memory array 716 includes an array of storage bit cells for storing data. The system memory 710 may be a read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), and static memory (e.g., flash memory, static random access memory (SRAM), etc.), as a non-limiting example.

[0073] Other devices can be connected to system bus 712. For example... Figure 7 As shown, as an example, these devices may include system memory 710, one or more input devices 718, one or more output devices 720, modem 722, and one or more display controllers 724. Input devices 718 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 720 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Modem 722 may be any device configured to allow data exchange with network 726. Network 726 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth™ networks, and the Internet. Modem 722 may be configured to support any type of communication protocol required. Processor 702 may also be configured to access display controller 724 via system bus 712 to control information sent to one or more displays 728. Displays 728 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, etc.

[0074] Figure 7 The processor-based system 700 may include a set of instructions 730, which will be executed by the processor 702 for any application required according to the instructions. The instructions 730 may be stored in system memory 710, processor 702, and / or instruction cache 708 (as an example of a non-transitory computer-readable medium 732). The instructions 730 may also reside wholly or at least partially within system memory 710 and / or processor 702 during their execution. The instructions 730 may also be transmitted or received on network 726 via modem 722, such that network 726 includes computer-readable medium 732.

[0075] Although computer-readable medium 732 is shown as a single medium in exemplary embodiments, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more sets of instructions. The term "computer-readable medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processing device and causing the processing device to perform any one or more of the methods of the embodiments disclosed herein. Therefore, the term "computer-readable medium" should include, but is not limited to, solid-state storage, optical media, and magnetic media.

[0076] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor programmed with these instructions to perform these steps. Alternatively, these steps may be performed by a combination of hardware and software.

[0077] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to the embodiments disclosed herein. Machine-readable media include information for storing or transmitting in a machine-readable form (e.g., a computer). For example, machine-readable media include machine-readable storage media (e.g., ROM, random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.).

[0078] Unless otherwise explicitly stated and apparent from the foregoing discussion, it should be understood that throughout the description, discussions using terms such as “processing,” “computing,” “determining,” and “displaying” refer to the actions and processes of a computer system or similar electronic computing device that operate on data and storage represented as physical (electronic) quantities within computer system registers and convert the data and storage into physical quantities within other data storage, transmission, or display devices similar to those represented as computer system memory or registers or other such information.

[0079] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various systems can be used with programs based on the teachings herein, or it can be demonstrated that it is convenient to construct more specialized devices to perform the required method steps. The necessary structures for various such systems will emerge from the above description. Furthermore, the embodiments described herein are not described with reference to any particular programming language. It should be understood that the teachings of the embodiments described herein can be implemented using a variety of programming languages.

[0080] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium, and executed by a processor or other processing device, or a combination of both. As an example, components of the distributed antenna system described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information as required. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Those skilled in the art can implement the described functionality in different ways for each specific application; however, such implementation decisions should not be construed as causing a departure from the scope of this embodiment.

[0081] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein can be implemented using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination designed to perform the functions described herein. Furthermore, the controller can be a processor. The processor can be a microprocessor, but alternatively, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0082] The embodiments disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated into the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0083] It should also be noted that the operational steps described in any exemplary embodiment herein are described as being for the purpose of example and discussion. The described operations may be performed in many different orders other than those shown. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary embodiments may be combined. Those skilled in the art will also understand that information and signals can be represented using any of a variety of techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0084] Unless otherwise expressly stated, no method described herein is intended to be construed as requiring its steps to be performed in a particular order. Therefore, if a method claim does not actually describe the order in which its steps are followed, or if the claims or description do not otherwise specify that these steps will be limited to a particular order, it should not be construed as inferring any particular order.

[0085] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Since modifications, combinations, sub-combinations, and variations of the disclosed embodiments in conjunction with the spirit and essence of the invention will be apparent to those skilled in the art, the invention should be construed as including all contents within the scope of the appended claims and their equivalents.

Claims

1. A scheduler circuit in a processor, configured to receive a plurality of instructions to be scheduled for execution, the plurality of instructions including producer instructions and consumer instructions, the scheduler circuit comprising: At least two (2) operand pool reservation circuits, each allocated to store instructions including a number of allocated source operands, each of the at least two (2) operand pool reservation circuits having a different number of allocated source operands than each of the other operand pool reservation circuits, and including: Multiple reservation entries, each configured to store instructions to be issued for execution, the number of source operands included in the instructions being equal to the number of source operands allocated for the operand pool reservation circuit; and The scheduler circuit is configured as follows: Based on the producer instruction among the plurality of instructions, receive the consumer instruction among the plurality of instructions; and The received consumer instruction is stored in the reserved entries of the plurality of reserved entries in the operand pool reserved circuits of the at least two (2) operand pool reserved circuits, and the at least two (2) operand pool reserved circuits are allocated the same number of source operands as the number of unread source operands in the received consumer instruction. Each of the at least two (2) operand pool reservation circuits is configured as follows: Receive one or more wake-up signals, each wake-up signal being associated with one or more publish channel circuits in the processor, the wake-up signal including at least one register tag indicating at least one source operand of at least one producer instruction published to one or more publish channel circuits in the one or more publish channel circuits; The at least one register tag is compared with the plurality of reserved entries in the operand pool reservation circuit, which is allocated the same number of source operands as the number of unread source operands in the received consumer instruction; and At least one source register in response to a consumer instruction in one of the plurality of reserved entries matches the at least one register label: An instruction ready signal is issued to at least one selection circuit for the consumer instruction in the reserved entry, the at least one selection circuit being configured to issue the consumer instruction to be executed to one of the one or more publication channel circuits.

2. The scheduler circuit according to claim 1, wherein: Each of the plurality of reservation entries in each of the at least two (2) operand pool reservation circuits includes at least one source register tag circuit, the at least one source register tag circuit being configured to store at least one source register tag identifying a source register operand. The scheduler circuit is also configured to: Based on at least one source operand in the received consumer instruction, at least one source register tag is stored in at least one source register tag circuit in one of the multiple reservation entries in the operand pool reservation circuit of the at least one operand pool reservation circuit, and the at least two (2) operand pool reservation circuits are allocated the same number of source operands as the number of source operands in the received consumer instruction; and Each of the at least two (2) operand pool reservation circuits is configured as follows: The at least one register tag in at least one wake-up signal is compared with at least one source register tag in at least one source register tag circuit in each of the plurality of reserved entries in the operand pool reservation circuit, the operand pool reservation circuit being allocated the same number of source operands as the number of unready source operands in the received consumer instruction. as well as In response to at least one source register tag in at least one source register tag circuit of one of the plurality of reserved entries matching at least one register tag in the at least one wake-up signal: An instruction ready signal is issued to the at least one selection circuit for the consumer instruction in the reserved entry, the at least one selection circuit being configured to issue the consumer instruction to be executed to one of the one or more publication channel circuits.

3. The scheduler circuit according to claim 1 further includes: An operand-free pool reservation circuit, allocated to store instructions without source operands, includes: Multiple reserved entries, each reserved entry is configured to store instructions, excluding source operands, to be published for execution; The scheduler circuit is also configured to: The consumer instruction, excluding the source operand, is stored in a reserved entry among the plurality of reserved entries in the operand-free pool reserved circuit; and The no-operand pool reserved circuit is configured as follows: An instruction ready signal is issued to at least one select circuit for the consumer instruction excluding a source operand, the at least one select circuit being configured to issue the consumer instruction excluding a source operand to one of the one or more publish channel circuits.

4. The scheduler circuit according to claim 1, wherein: The at least two (2) operand pool reserved circuits include: The first operand pool reservation circuit is allocated to store instructions comprising one (1) source operands and includes: Multiple first reservation entries, each first reservation entry being configured to store instructions to be published for execution, including one (1) source operand; and The second operand pool reserved circuit is allocated to store instructions comprising two (2) source operands and includes: Multiple second reservation entries, each configured to store instructions to be published for execution, comprising two (2) source operands; and The scheduler circuit is configured as follows: The consumer instructions are stored in a reserved entry by being configured with the following: The first consumer instruction, which includes one (1) source operand, is stored in the first reservation entry of the plurality of first reservation entries in the first operand pool reservation circuit; and The second consumer instruction, which comprises two (2) source operands, is stored in the second reservation entry of the plurality of second reservation entries in the second operand pool reservation circuit.

5. The scheduler circuit according to claim 4, wherein: The second operand pool reserved circuit is configured as follows: The first register tag in at least one wake-up signal is compared with the first source register tag in the first source register tag circuit of each of the multiple second reservation entries in the second operand pool reservation circuit of the received second consumer instruction; The second register tag in the at least one wake-up signal is compared with the second source register tag in the second source register tag circuit of each of the multiple second reserved entries in the second operand pool reserved circuit of the received second consumer instruction; and In response to the first source register tag in the first source register tag circuit of one of the plurality of second reserved entries matching the first register tag in the at least one wake-up signal, and the second source register tag in the second source register tag circuit of the second reserved entry matching the second register tag in the at least one wake-up signal: An instruction ready signal is issued to at least one selection circuit for the second consumer instruction in the second reserved entry, the at least one selection circuit being configured to issue the second consumer instruction to be executed to one of the one or more publication channel circuits.

6. The scheduler circuit according to claim 4, further comprising: The wake-up bus is configured to carry at least one wake-up signal; as well as A delay circuit, coupled to the wake-up bus, is configured to delay the at least one wake-up signal to generate an at least one clock cycle delayed wake-up signal, the at least one clock cycle delayed wake-up signal being derived from the at least one wake-up signal by delaying the clock signal by at least one clock cycle. Each of the plurality of second reservation entries in the second operand pool reservation circuit includes a first source register tag circuit and a second source register tag circuit. The first source register tag circuit is configured to store a first source register tag that identifies a first source register operand. The second source register tag circuit is configured to store a second source register tag that identifies a second source register operand. in: The first source register tag circuitry for each of the plurality of second reserved entries is coupled to the wake-up bus to receive the at least one wake-up signal; and The second source register tag circuitry for each of the plurality of second reserved entries is coupled to the delay circuitry to receive a delayed wake-up signal for at least one clock cycle; and The second operand pool reservation circuit is configured such that, in response to the first source register tag in the first source register tag circuit of one of the plurality of second reservation entries matching the first register tag in the at least one wake-up signal, and the second source register tag in the second source register tag circuit of the second reservation entry matching the second register tag in the at least one wake-up signal: An instruction ready signal is issued to at least one selection circuit for the second consumer instruction in the second reserved entry, the at least one selection circuit being configured to issue the consumer instruction to be executed to one of the one or more publication channel circuits.

7. The scheduler circuit according to claim 6, wherein: The second operand pool reservation circuit is further configured such that: in response to a first source register tag in the first source register tag circuit of one of the plurality of second reservation entries matching the first register tag in the at least one wake-up signal, and a second source register tag in the second source register tag circuit of the second reservation entry not matching the second register tag in the at least one wake-up signal: The first source register tag is stored in the second source register tag circuit, and the second source register tag is stored in the first source register tag circuit.

8. The scheduler circuit according to claim 7, wherein: The first source register tag circuit includes: The first source register label field, including the first source register label field input, The first source register label field is coupled to the second source register label field input and is configured to store the first source register label; The second source register label field, including the second source register label field input, The second source register tag field is coupled to the first source register tag field input and is configured to store the second source register tag; and A first comparator circuit, coupled to the first source register tag field and the wake-up bus, is configured to, in response to a first source register tag stored in the first source register tag field matching at least one register tag in at least one wake-up signal on the wake-up bus, pass the first source register tag stored in the first source register tag field to the second source register tag field input to be stored in the second source register tag field.

9. The scheduler circuit according to claim 5, wherein: The at least two (2) operand pool reserved circuits also include: The third operand pool reserved circuit is allocated to store instructions comprising two (2) source operands and includes: Multiple third-reservation entries, each configured to store instructions to be published for execution, comprising two (2) source operands; and Each of the plurality of third reservation entries in the third operand pool reservation circuit includes a third source register tag circuit and a fourth source register tag circuit. The third source register tag circuit is configured to store a first source register tag that identifies a first source register operand, and the fourth source register tag circuit is configured to store a second source register tag that identifies a second source register operand. The third operand pool reserved circuit is configured as follows: The first register tag in the at least one wake-up signal is compared with the first source register tag in the third source register tag circuit of each of the plurality of third reservation entries in the third operand pool reservation circuit of the received second consumer instruction; The second register tag in the at least one wake-up signal is compared with the second source register tag in the fourth source register tag circuit of each of the plurality of third reserved entries in the third operand pool reserved circuit of the received second consumer instruction; and In response to the first source register tag circuit of one of the plurality of third reserved entries matching the first register tag of the at least one wake-up signal, and the fourth source register tag of the second source register tag circuit of the third reserved entry matching the second register tag of the at least one wake-up signal: An instruction ready signal is issued to the at least one selection circuit for the second consumer instruction in the third reserved entry, the at least one selection circuit being configured to issue the second consumer instruction to be executed to the publication channel circuit of the one or more publication channel circuits.

10. The scheduler circuit according to claim 9, wherein: The number of third reserved entries in the plurality of third reserved entries in the third operand pool reservation circuit is less than the number of second reserved entries in the plurality of second reserved entries in the second operand pool reservation circuit.

11. The scheduler circuit of claim 9, configured to store the received consumer instruction in a reservation entry in one of the at least two (2) operand pool reservation circuits by being configured to: Determine whether the received consumer instruction includes two (2) source operands; In response to determining that the received consumer instruction comprises two (2) source operands: Determine whether the two source operands of the received consumer instruction are ready to be issued within the same clock cycle; and In response to the determination that neither of the two source operands of the received consumer instruction is ready to be issued within the same clock cycle: The consumer instruction is stored in the second reserved entry in the second operand pool reserved circuit.

12. The scheduler circuit according to claim 11, wherein: In response to determining that both source operands of the received consumer instruction are ready to be published within the same clock cycle: The consumer instruction is stored in the third reserved entry in the third operand pool reserved circuit.

13. The scheduler circuit of claim 9, configured to store the received consumer instruction in a reservation entry in one of the at least two (2) operand pool reservation circuits by being configured to: Determine whether the received consumer instruction includes two (2) source operands; In response to determining that the received consumer instruction comprises two (2) source operands: Determine whether the received consumer instruction is a single-cycle delay instruction; and In response to determining that the received consumer instruction is a single-cycle delay instruction: The consumer instruction is stored in the second reserved entry in the second operand pool reserved circuit.

14. The scheduler circuit of claim 9, configured to store the received consumer instruction in a reservation entry in one of the at least two (2) operand pool reservation circuits by being configured to: Determine whether the received consumer instruction includes two (2) source operands; In response to determining that the received consumer instruction comprises two (2) source operands: Determine whether the received consumer instruction depends on a single-cycle delayed producer instruction; and In response to determining that the received consumer instruction depends on a single-cycle delayed producer instruction: The consumer instruction is stored in the second reserved entry in the second operand pool reserved circuit.

15. The scheduler circuit according to claim 1, wherein: Each of the plurality of reservation entries in each of the at least two (2) operand pool reservation circuits is further configured to store at least one source register tag identifying the at least one source operand of the stored instruction. as well as Each of the at least two (2) operand pool reservation circuits is configured as follows: The at least one register tag is compared with the at least one source register tag among the plurality of reservation entries in the operand pool reservation circuit, the operand pool reservation circuit being allocated the same number of source operands as the number of unread source operands in the received consumer instruction; as well as In response to a match between at least one source register tag of the consumer instruction in one of the plurality of reserved entries and the at least one register tag, an instruction ready signal for the consumer instruction is issued to the at least one selection circuit, the at least one selection circuit being configured to issue the consumer instruction to be executed to the publication channel circuit of one or more publication channel circuits.

16. The scheduler circuit according to claim 1, further comprising: The at least one selection circuit is configured to: in response to an instruction ready signal indicating that the consumer instruction is ready to be published, select at least one instruction to be executed from at least one of the plurality of reservation entries stored in the at least two (2) operand pool reservation circuits into the publication channel circuit of the one or more publication channel circuits.

17. The scheduler circuit according to claim 1, wherein: The one or more publishing channel circuits include multiple publishing channel circuits; and The scheduler circuit also includes: Multiple publish arbitration circuits, each of which is coupled to an associated publish channel circuit among the multiple publish channel circuits and to the at least two (2) operand pool reservation circuits, each of which is configured to pass an instruction from a selected consumer instruction to its associated publish channel circuit.

18. The scheduler circuit according to claim 17, further comprising: Each of the plurality of publishing channel circuits is configured to generate a wake-up signal among the one or more wake-up signals in response to a producer instruction published in the publishing channel circuit, and the wake-up signal includes a publishing-ready publishing state.

19. A method for scheduling a plurality of instructions to be executed in an execution circuit in a processor, the plurality of instructions including producer instructions and consumer instructions, the method comprising: According to the producer instruction among the plurality of instructions, receive the consumer instruction among the plurality of instructions; The received consumer instruction is stored in a reserved entry among a plurality of reserved entries in at least two (2) operand pool reservation circuits, wherein the at least two (2) operand pool reservation circuits are allocated a number of source operands equal to the number of unread source operands in the received consumer instruction, and each of the at least two (2) operand pool reservation circuits comprises: Multiple reservation entries, each reservation entry being configured to store instructions to be issued for execution, the number of unread source operands included in the instructions being equal to the number of source operands allocated, the number of source operands allocated being different from each of the other operand pool reservation circuits among the at least two (2) operand pool reservation circuits. Receive one or more wake-up signals, each wake-up signal being associated with one or more publish channel circuits in the processor, the wake-up signal including at least one register tag indicating at least one source operand of at least one producer instruction published to one or more publish channel circuits in the one or more publish channel circuits; The at least one register tag is compared with the plurality of reserved entries in the operand pool reservation circuit, which is allocated the same number of source operands as the number of unready source operands in the received consumer instruction; and In response to at least one source register matching the at least one register tag of a consumer instruction in one of the plurality of reserved entries, an instruction ready signal for the consumer instruction in the reserved entry is issued to at least one select circuit, the at least one select circuit being configured to issue the consumer instruction to be executed to a publish channel circuit among the one or more publish channel circuits.

20. The method of claim 19, further comprising: Consumer instructions excluding source operands are stored in a reserved entry among a plurality of reserved entries in an operand-free pool reserved circuit, the plurality of reserved entries being configured to store instructions excluding source operands to be issued for execution. as well as The at least one select circuit is configured to issue an instruction ready signal for the consumer instruction excluding the source operand to one of the one or more publish channel circuits.

21. The method of claim 19, wherein storing the received consumer instruction comprises: The first consumer instruction, which includes one (1) source operand, is stored in the first reserved entry of a plurality of first reserved entries in the first operand pool reservation circuit of the at least two (2) operand pool reservation circuits, the first operand pool reservation circuit being allocated to store the instruction including one (1) source operand; and The second consumer instruction, which includes two (2) source operands, is stored in the second reservation entry of a plurality of second reservation entries in the second operand pool reservation circuit of the at least two (2) operand pool reservation circuits, the second operand pool reservation circuits being allocated to store the instruction including two (2) source operands.

22. The method of claim 21, further comprising: The first register tag in at least one wake-up signal is compared with the first source register tag in the first source register tag circuit of each of the plurality of second reservation entries in the second operand pool reservation circuit of the received second consumer instruction; The second register tag in the at least one wake-up signal is compared with the second source register tag in the second source register tag circuit of each of the plurality of second reservation entries in the second operand pool reservation circuit of the received second consumer instruction; as well as In response to the first source register tag in the first source register tag circuit of one of the plurality of second reserved entries matching the first register tag in the at least one wake-up signal, and the second source register tag in the second source register tag circuit of the second reserved entry matching the second register tag in the at least one wake-up signal, an instruction ready signal for the second consumer instruction in the second reserved entry is issued to at least one selection circuit, the at least one selection circuit being configured to issue the second consumer instruction to be executed to a publication channel circuit of one or more publication channel circuits.

23. The method of claim 21, further comprising: In response to the first source register tag in the first source register tag circuit of the second reserved entry among the plurality of second reserved entries matching the first register tag in the at least one wake-up signal, and the second source register tag in the second source register tag circuit of the second reserved entry not matching the second register tag in the at least one wake-up signal, the first source register tag is stored in the second source register tag circuit and the second source register tag is stored in the first source register tag circuit.

24. The method of claim 22, further comprising: The first register tag in the at least one wake-up signal is compared with the first source register tag in the third source register tag circuit of each of the plurality of third reservation entries in the third operand pool reservation circuit of the received second consumer instruction, wherein each of the plurality of third reservation entries is configured to store an instruction with two (2) source operands to be issued for execution, and the third operand pool reservation circuit is allocated to store the instruction with two (2) source operands. The second register tag in the at least one wake-up signal is compared with the second source register tag in the fourth source register tag circuit of each of the plurality of third reserved entries in the third operand pool reserved circuit of the received second consumer instruction; and In response to the first source register tag circuit of one of the plurality of third reserved entries matching the first register tag of the at least one wake-up signal, and the fourth source register tag of the second source register tag circuit of the third reserved entry matching the second register tag of the at least one wake-up signal: An instruction ready signal is issued to the at least one selection circuit for the second consumer instruction in the third reserved entry, the at least one selection circuit being configured to issue the second consumer instruction to be executed to the publication channel circuit of the one or more publication channel circuits.

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