Integrated device including a peripheral structure configured as an electrical protection ring and a crack stop

Abstract

An integrated device includes: a substrate; a circuit region located on the substrate; a design-forbidden region located on the substrate; and a peripheral structure located on the substrate. The design-forbidden region laterally surrounds the circuit region. The peripheral structure includes a first plurality of interconnects, the first plurality of interconnects laterally surrounding the design-forbidden region. The peripheral structure is configured to operate as an electrical sealing ring and a mechanical crack stop.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Non-Provisional Application No. 17 / 002,643 filed in the U.S. Patent and Trademark Office on August 25, 2020, and Provisional Application No. 63 / 010,554 filed in the U.S. Patent and Trademark Office on April 15, 2020, which are expressly incorporated herein by reference as if fully set forth in their entireties below for all applicable purposes. Technical Field

[0003] Various features are directed to integrated devices, but more particularly to integrated devices including a peripheral structure configured as an electrical protection ring and crack stop. Background Art

[0004] Figure 1 A package 100 is illustrated that includes a substrate 102 and an integrated device 104. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. A plurality of solder interconnects 144 are coupled to the substrate 102 and the integrated device 104. The plurality of solder interconnects 124 are coupled to the substrate 102. During the period when the integrated device 104 is coupled to the substrate 102, the integrated device 104 may be subjected to significant mechanical stress, which may cause the integrated device 104 to fracture and / or fail. There is a continuing need to provide reliable integrated devices. Summary of the invention

[0005] Various features are directed to integrated devices, but more particularly to integrated devices including a peripheral structure configured as an electrical guard ring and a mechanical crack stop.

[0006] One example provides an integrated device, comprising: a substrate; a circuit region located on the substrate; a design-keep region located on the substrate; and a peripheral structure located on the substrate. The design-keep region laterally surrounds the circuit region. The peripheral structure includes a first plurality of protective interconnects laterally surrounding the design-keep region. The peripheral structure is configured to operate as an electrical sealing ring and a mechanical crack stop.

[0007] Another example provides a device, the device comprising: a substrate; a circuit area located on the substrate; a design-forbidden area located on the substrate; and a component for peripheral protection, which laterally surrounds the design-forbidden area. The design-forbidden area laterally surrounds the circuit area. The component for peripheral protection is configured to operate as an electrical sealing ring and a mechanical crack stop.

[0008] Another example provides a method, the method includes providing a substrate. The method forms a circuit area on the substrate so that there is a design keep-out area on the substrate, wherein the design keep-out area laterally surrounds the circuit area. The method forms a peripheral structure on the substrate, the peripheral structure including a first plurality of protective interconnects, the first plurality of protective interconnects laterally surrounding the design keep-out area, wherein the peripheral structure is configured to operate as an electrical sealing ring and a mechanical crack stop. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various features, properties and advantages will become apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which like reference numerals are correspondingly identified throughout.

[0010] Figure 1 A cross-sectional view of a package including an integrated device and a substrate is illustrated.

[0011] Figure 2 A plan view of an integrated device including a peripheral structure configured to operate as an electrical sealing ring and a crack stopper is illustrated.

[0012] Figure 3 A plan view of an integrated device including another peripheral structure configured to operate as an electrical sealing ring and a crack stopper is illustrated.

[0013] Figure 4 A plan view of an integrated device including another peripheral structure configured to operate as an electrical sealing ring and a crack stopper is illustrated.

[0014] Figure 5 A plan view of a wafer including a plurality of integrated devices, each of which includes a peripheral structure configured to operate as an electrical sealing ring and a crack stopper, is illustrated.

[0015] Figure 6 A cross-sectional view of an integrated device including a peripheral structure configured to operate as an electrical sealing ring and a crack stopper is illustrated.

[0016] Figure 7 A cross-sectional view of an integrated device including another peripheral structure configured to operate as an electrical sealing ring and a crack stopper is illustrated.

[0017] Figure 8 A cross-sectional view of a peripheral structure configured to operate as an electrical sealing ring and a crack stop is illustrated.

[0018] Fig. 9 A cross-sectional view of a peripheral structure configured to operate as an electrical sealing ring and a crack stop is illustrated.

[0019] Fig.10 A cross-sectional view of another peripheral structure configured to operate as an electrical sealing ring and a crack stop is illustrated.

[0020] Fig.11 A cross-sectional view of another peripheral structure configured to operate as an electrical sealing ring and a crack stop is illustrated.

[0021] Fig.12 A plan view of a peripheral structure including a plurality of interconnect components configured to operate as an electrical sealing ring and a crack stopper is illustrated.

[0022] Fig.13 A cross-sectional view of a peripheral structure including a plurality of interconnected components configured to operate as an electrical sealing ring and a crack stopper is illustrated.

[0023] FIG. 14A to FIG. 14G An exemplary sequence for manufacturing a peripheral structure configured to operate as an electrical seal ring and a mechanical crack stop is illustrated.

[0024] Fig.15 An exemplary flow chart of a method for manufacturing a peripheral structure configured to operate as an electrical seal ring and a mechanical crack stop is illustrated.

[0025] FIG. 16A to FIG. 16B An exemplary sequence for fabricating an integrated device including a peripheral structure configured to operate as an electrical sealing ring and a crack stopper is illustrated.

[0026] Fig.17 An exemplary flow chart of a method for fabricating an integrated device including a peripheral structure configured to operate as an electrical sealing ring and a crack stopper is illustrated.

[0027] Fig.18 Various electronic devices are illustrated that may integrate the dies, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION

[0028] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those of ordinary skill in the art that the various aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring these aspects in unnecessary detail. In other cases, well-known circuits, structures, and techniques may not be shown in detail in order not to confuse various aspects of the present disclosure.

[0029] The present disclosure describes an integrated device (e.g., an integrated circuit die) comprising: a substrate; a circuit region located on the substrate; a design forbidden region located on the substrate; and a peripheral structure located on the substrate. The design forbidden region laterally surrounds the circuit region. The peripheral structure includes a first plurality of protective interconnects that laterally surround the design forbidden region. The peripheral structure is configured to operate as an electrical sealing ring and a mechanical crack stop. The first plurality of protective interconnects may be vertically staggered. The peripheral structure may further include a second plurality of protective interconnects that laterally surround the first plurality of protective interconnects. The second plurality of protective interconnects may be laterally staggered with the first plurality of protective interconnects. The first plurality of protective interconnects may be configured to couple to ground. The peripheral structure may be implemented in an interconnect portion of the integrated device. The peripheral structure may be a component that provides at least two functions for the integrated device, namely, an electrical sealing ring and a mechanical crack stop. That is, the peripheral structure may be configured to (i) prevent signals from external devices from interfering with active circuits of the circuit region, and / or (ii) prevent cracks from propagating into the design forbidden region and the circuit region of the integrated device. Furthermore, the location of the peripheral structures provides for more efficient use of space in the integrated device, resulting in a more compact integrated device, which in turn allows more integrated devices to be fabricated per wafer.

[0030] Exemplary integrated device including peripheral structures

[0031] Figure 2 A plan view of an integrated device 200 including a peripheral structure 206 is illustrated. As will be further described below, the peripheral structure 206 can be configured as an electrical seal ring and a mechanical crack stop for the integrated device 200. The peripheral structure 206 can be a protective peripheral structure. The peripheral structure 206 can be a component for peripheral protection. The integrated device 200 can include a die (e.g., an integrated circuit die, a semiconductor bare die).

[0032] The integrated device 200 includes: a substrate (not visible); a circuit region 202 formed and located on the substrate; a design-forbidden region 204 formed and located on the substrate; and a peripheral structure 206 formed and located on the substrate.

[0033] The circuit region 202 may be a region of the integrated device 200 that includes circuit components, such as active devices and passive devices. The circuit region 202 may include an active device, such as at least one transistor. The active device may be formed in a front end of line (FEOL) portion of the integrated device 200. The circuit region 202 may include a plurality of interconnects. The plurality of interconnects may be configured to electrically couple the active devices and / or the passive devices. The plurality of interconnects may be formed on an interconnect portion or a back end of line (BEOL) portion of the integrated device 200, which will be described below at least in Figure 6 and Figure 7Further described in .

[0034] The design-forbidden area 204 laterally surrounds the circuit area 202. The design-forbidden area 204 may be an area on the substrate without any active devices and / or passive devices. The design-forbidden area 204 may be an area on the substrate without an interconnection. The design-forbidden area 204 may be an area on the substrate without any active devices (e.g., transistors), passive devices (e.g., inductors, capacitors), and interconnections. The design-forbidden area 204 may be an area on the substrate (e.g., 620) without a peripheral structure (e.g., 206). The design-forbidden area 204 may be an area on the substrate without an interconnection configured to be electrically coupled to active devices and / or passive devices of an integrated device. Therefore, the design-forbidden area 204 may not include an interconnection configured to be electrically coupled to active devices and / or passive devices of an integrated device. However, the design-forbidden area 204 may include at least one interconnect that is coupled to a peripheral structure (e.g., 206), but the at least one interconnect may be configured not to be electrically coupled to active devices (e.g., transistors) and / or passive devices (e.g., inductors, capacitors) of the integrated device. The design-forbidden area 204 may be an area on the substrate (e.g., 620) that is free of peripheral structures (e.g., 206). The design-forbidden area 204 may include at least one dielectric layer. The design-forbidden area 204 may be a continuous area and / or an adjacent area on the substrate. The design-forbidden area 204 may be used to optically inspect the integrated device 200 for cracks. In some implementations, when the design-forbidden area 204 includes at least one crack, the integrated device 200 may be considered defective and may be discarded. When there are no cracks in the design-forbidden area 204, the integrated device 200 may pass the optical inspection.

[0035] The peripheral structure 206 laterally surrounds the design-forbidden area 204 and the circuit area 202. The peripheral structure 206 includes a first plurality of protection interconnects 260 (e.g., 260a, 260b, 260c) that laterally surround the design-forbidden area 204 and the circuit area 202. The peripheral structure 206 may also include a second plurality of protection interconnects 262 (e.g., 262a, 262b) that laterally surround the design-forbidden area 204 and the circuit area 202. The second plurality of protection interconnects 262 laterally surround the first plurality of protection interconnects 260. The second plurality of protection interconnects 262 may be laterally staggered with the first plurality of protection interconnects 260. The first plurality of protection interconnects 260 and the second plurality of protection interconnects 262 may each be arranged in a dashed pattern on at least one specific metal layer of the integrated device. The first plurality of protection interconnects 260 and the second plurality of protection interconnects 262 may each be arranged in rows (and / or columns) of dashed protection interconnects. Rows of protection interconnects from the first plurality of protection interconnects 260 may be laterally staggered with rows of protection interconnects from the second plurality of protection interconnects 262. The second plurality of protection interconnects 262 may be laterally spaced apart from the first plurality of protection interconnects 260. Different implementations may have different spacings (one or more) between the second plurality of protection interconnects 262 and the first plurality of protection interconnects 260. In some implementations, the second plurality of protection interconnects 262 and the first plurality of protection interconnects 260 may be laterally spaced apart by about 3-4 micrometers (μm) or less. In at least the following embodiments, Figures 8 to 13 More detailed examples of peripheral structures are further illustrated and described in .

[0036] Figure 2One metal layer of the first plurality of protection interconnects 260 and the second plurality of protection interconnects 262 is illustrated. However, the first plurality of protection interconnects 260 and the second plurality of protection interconnects 262 may be formed on more than one metal layer (e.g., M1, M2, M3, M4, M5, M6, M7, M8, M9) of the integrated device 200. The first plurality of protection interconnects 260 and the second plurality of protection interconnects 262 may also include vias (e.g., via bars) that couple interconnects on various metal layers of the integrated device 200. Thus, the first plurality of protection interconnects 260 and the second plurality of protection interconnects 262 may each include traces and / or pads on at least one metal layer of the integrated device 200 and / or vias between metal layers. The design and / or configuration of the first plurality of protection interconnects 260 and the second plurality of protection interconnects 262 may vary with different implementations. As will be further described below, in some implementations, at least some of the protection interconnects from the first plurality of protection interconnects 260 and / or the second plurality of protection interconnects 262 can be coupled to ground. The first plurality of protection interconnects 260 and the second plurality of protection interconnects 262 can be formed on an interconnect portion or a back-end of line (BEOL) portion of the integrated device 200, which will be described below at least in Figure 6 and Figure 7 Further described in .

[0037] As described above, the peripheral structure 206 is configured to operate as an electrical sealing ring and crack stopper for the integrated device 200. Therefore, the first plurality of protective interconnects 260 and / or the second plurality of protective interconnects 262 can be configured individually or collectively to operate as an electrical sealing ring and crack stopper (e.g., a mechanical crack stopper) for the integrated device 200. The peripheral structure 206 can be configured as an electrical sealing ring by providing isolation for the active circuits (e.g., active devices) in the circuit area 202 from external signals (such as signals from other integrated devices). Therefore, the peripheral structure 206 configured as an electrical sealing ring helps to reduce and / or eliminate crosstalk that may occur with other external components near the integrated device 200. To further increase the effectiveness of the peripheral structure 206 as an electrical sealing ring, the peripheral structure 206 can be coupled to ground. In such cases, peripheral structure 206 may be coupled to ground pins and / or solder interconnects configured to be coupled to a ground (eg, an external ground separate from the active devices of circuit region 202 ). Figure 6 and Figure 7206. The peripheral structure 206 is illustrated as how it can be coupled to ground. The peripheral structure 206 can be configured to prevent cracks from propagating into the design forbidden area 204 and the circuit area 202. In some implementations, the first plurality of protection interconnects 260 or the second plurality of protection interconnects 262 can provide an additional electrical sealing ring function and / or an additional crack arresting function for the integrated device 200. The peripheral structure 206 can be located at a position offset from the edge 208 of the integrated device 200. Different implementations can position the peripheral structure 206 to be different from the edge 208 of the integrated device 200. In some implementations, at least some portions of the peripheral structure 206 can be about 15 micrometers (μm) or less (e.g., 10-15 μm) from the edge 208. The edge 208 can define the physical lateral boundary of the integrated device 200.

[0038] The peripheral structure 206 provides a variety of functions and advantages for the integrated device 200. In addition, the location of the peripheral structure 206 is such that the design forbidden area 204 is located between the circuit area 202 and the peripheral structure 206. Such a location of the peripheral structure 206 provides and enables more efficient use of space for the integrated device 200. In other words, the design of the integrated device 200 reduces wasted space, which helps to reduce the size and / or cost of the integrated device 200. In some implementations, the size of the integrated device can be saved by about 8-20%, which means that more integrated devices can be manufactured in a wafer of similar size. This in turn can reduce the cost of manufacturing each integrated device.

[0039] Figure 3 An integrated device 300 is illustrated that includes a peripheral structure 306 configured to operate as an electrical sealing ring and a mechanical crack stop for the integrated device. The integrated device 300 may be similar to Figure 2 The integrated device 300 is an integrated device 200, and thus may include the same or similar components as the integrated device 200. The integrated device 300 includes: a substrate (not visible); a circuit area 202, which is formed and located on the substrate; a design forbidden area 204, which is formed and located on the substrate; and a peripheral structure 306, which is formed and located on the substrate. The peripheral structure 306 may be a component for peripheral protection. The integrated device 300 may include a tube core. The integrated device 300 includes an edge 208, which defines the physical lateral boundary of the integrated device 300.

[0040] like Figure 3As shown in , the peripheral structure 306 includes a first plurality of protective interconnects 360 (e.g., 360a, 360b, 360c), a second plurality of protective interconnects 362 (e.g., 363a, 363b, 362c), and a third plurality of protective interconnects 364 (e.g., 364a, 364b). The first plurality of protective interconnects 360, the second plurality of protective interconnects 362, and the third plurality of protective interconnects 364 may be similar in design, shape, and / or size to the first plurality of protective interconnects 260 and / or the second plurality of protective interconnects 262.

[0041] Peripheral structure 306 laterally surrounds design keep-out region 204 and circuit region 202. First plurality of protection interconnects 360, second plurality of protection interconnects 362, and third plurality of protection interconnects 364 laterally surround design keep-out region 204 and circuit region 202. Third plurality of protection interconnects 364 laterally surrounds second plurality of protection interconnects 362. Second plurality of protection interconnects 362 laterally surrounds first plurality of protection interconnects 360.

[0042] The first plurality of protection interconnects 360, the second plurality of protection interconnects 362, and the third plurality of protection interconnects 364 can each be arranged in a dotted pattern on at least one specific metal layer of the integrated device. The second plurality of protection interconnects 362 can be laterally staggered with the first plurality of protection interconnects 360. The third plurality of protection interconnects 364 laterally surround the second plurality of protection interconnects 362. The third plurality of protection interconnects 364 can be laterally staggered with the second plurality of protection interconnects 362. The first plurality of protection interconnects 360, the second plurality of protection interconnects 362, and the third plurality of protection interconnects 364 can each be arranged in rows (and / or columns) of protection interconnects. The rows of protection interconnects from the first plurality of protection interconnects 360 can be laterally staggered with the rows of protection interconnects from the second plurality of protection interconnects 362. The rows of protection interconnects from the second plurality of protection interconnects 362 can be laterally staggered with the rows of protection interconnects from the third plurality of protection interconnects 364. The second plurality of protection interconnects 362 can be laterally spaced apart from the first plurality of protection interconnects 360. The third plurality of protection interconnects 364 may be laterally spaced apart from the second plurality of protection interconnects 362. Different implementations may have different spacings between (i) the second plurality of protection interconnects 362 and the first plurality of protection interconnects 360, and (ii) the third plurality of protection interconnects 364 and the second plurality of protection interconnects 362. In some implementations, the second plurality of protection interconnects 362 and the first plurality of protection interconnects 360 may be laterally spaced apart by approximately 3-4 microns (μm) or less. In some implementations, the third plurality of protection interconnects 364 and the second plurality of protection interconnects 362 may be laterally spaced apart by approximately 3-4 microns (μm) or less. For the protection interconnects described in the present disclosure, different implementations may have similar or different widths. In addition, different implementations may have similar or different widths across different metal layers and / or vias of the protection interconnects. The protection interconnect may have a width of approximately 9 microns (μm) or less. In at least the following Figures 8 to 13 More detailed examples of peripheral structures are further illustrated and described in .

[0043] Figure 4 An integrated device 400 including a peripheral structure 306 is shown. The integrated device 400 may be similar to Figure 3 The integrated device 400 may include the same or similar components as the integrated device 300. The integrated device 400 includes: a substrate (not visible); a circuit region 202 formed and located on the substrate; a design-forbidden region 204 formed and located on the substrate; and a peripheral structure 306 formed and located on the substrate. The peripheral structure 306 may be a component for peripheral protection. The integrated device 400 may include a die. The integrated device 400 includes an edge 208 that defines the physical lateral boundary of the integrated device 400.

[0044] like Figure 4 As shown in , the peripheral structure 306 includes a plurality of isolation portions 404 (e.g., isolation portion 404a, isolation portion 404b). The isolation portion (e.g., 404a, 404b) can be a portion of the peripheral structure 306 through which a signal can travel. Different implementations can have different numbers of isolation portions. The isolation portion can be located in different portions of the peripheral structure 306. The isolation portion of the peripheral structure 306 can include: at least one protection interconnect portion, the at least one protection interconnect portion being configured to not be electrically coupled to other protection interconnect portions of the peripheral structure 306; and / or at least one protection interconnect portion being configured to not be electrically coupled to ground when other protection interconnect portions are configured to be coupled to ground. For example, the isolation portion (e.g., 404a, 404b) can include at least one protection interconnect portion from the first plurality of protection interconnect portions 360, that is (i) configured to not be electrically coupled to other protection interconnect portions from the first plurality of protection interconnect portions 360, and / or (ii) configured to not be coupled to ground. Similarly, the isolated portion (e.g., 404a, 404b) may include at least one protection interconnect from the second plurality of protection interconnects 362 that is (i) configured not to be electrically coupled to other protection interconnects from the second plurality of protection interconnects 362, and / or (ii) configured not to be coupled to ground. Additionally, the isolated portion (e.g., 404a, 404b) may include at least one protection interconnect from the third plurality of protection interconnects 364 that is (i) configured not to be electrically coupled to other protection interconnects from the second plurality of protection interconnects 364, and / or (ii) configured not to be coupled to ground. Figure 10 to Figure 11 The isolation portion is further described and illustrated in .

[0045] Figure 5 5 shows a portion of a wafer 500 that has been cut (eg, diced) along scribe lines 502 into a plurality of integrated devices 300 (eg, dies). Figure 5 As shown in , the scribe line 502 is positioned adjacent to the peripheral structure 306 of each corresponding integrated device 300. As described above, forming the peripheral structure 306 so that the peripheral structure 306 laterally surrounds the design-forbidden area 204 and the circuit area 202 helps to reduce and / or optimize the size of the integrated device 300. The size of the integrated device can be saved by about 8 to 20%, which means that more integrated devices can be manufactured on a wafer of similar size. This in turn can reduce the cost of manufacturing each integrated device.

[0046] Exemplary integrated device including peripheral structures

[0047] Figure 6 The diagram shows a cross-sectional view of an integrated device 600 including peripheral structures. The integrated device 600 may include a die. The integrated device 600 may represent Figure 2 The integrated device 600 includes a substrate 620 , a plurality of device-level cells 622 (eg, logic cells), an interconnect portion 604 , a circuit region 202 , a design-keep region 204 , a peripheral structure 206 , and an edge 208 .

[0048] A plurality of device-level cells 622 are formed over substrate 620. The plurality of device-level cells 622 can form a device-level layer of integrated device 600. In some implementations, the plurality of device-level cells 622 can include portions of substrate 620. In some implementations, substrate 620, the device-level layer, and the plurality of device-level cells 622 can be referred to as substrate portion 602 of integrated device 600.

[0049] The plurality of device-level units 622 may include one or more transistors. The transistor may include a gate, a source, and a drain. A gate contact may be formed over the gate. A source contact may be formed over the source. A drain contact may be formed over the drain. The contact may be configured to be electrically coupled to an interconnect of the integrated device (e.g., an interconnect of the M1 metal layer). For example, the gate contact may be configured to be electrically coupled to a contact interconnect that is coupled to an M1 layer interconnect.

[0050] The interconnect portion 604 is coupled to the substrate portion 602 and formed on the substrate portion 602. In particular, the interconnect portion 604 is formed on the plurality of device-level cells 622. The interconnect portion 604 includes a routing layer. The interconnect portion 604 includes a plurality of interconnects 640 (e.g., traces, pads, vias) and at least one dielectric layer 642. The interconnect portion 604 may provide interconnects for a plurality of transistors of the device-level cell. The M1 layer interconnect may be part of the interconnect portion 1604. The interconnect portion 604 may include other metal layers (e.g., M2 layer interconnect, M3 layer interconnect, M4 layer interconnect, etc. . . ). For the interconnect portion 604, different implementations may have different numbers of metal layers (e.g., M1, M2, M3, M4, M5, etc.). A passivation layer 660 may be formed and located on the interconnect portion 604. At least one pad 662 may be coupled to the plurality of interconnects 640.

[0051] like Figure 6As shown in , the circuit region 202, the design forbidden area 204 and the peripheral structure 206 are formed and located on the substrate 620. The circuit region 202 can be an area of ​​the integrated device 600 that includes circuit components. For example, the circuit region 202 can include a device-level unit 622, which can include at least one transistor. The circuit region 202 can also include a plurality of interconnects 640 and at least one pad 662. The plurality of interconnects 640 can be configured to electrically couple active devices and / or passive devices. The plurality of interconnects 640 can be formed on a back-end-of-line (BEOL) portion of the integrated device 600.

[0052] The design-forbidden area 204 may be an area on the substrate 620 without any active devices and / or passive devices. The design-forbidden area 204 may be an area on the substrate 620 without an interconnection (e.g., without the plurality of interconnections 640). The design-forbidden area 204 may be an area on the substrate 620 without any active devices, passive devices, and interconnections. The design-forbidden area 204 may be an area on the substrate 620 without a peripheral structure (e.g., 206). The design-forbidden area 204 may be an area on the substrate (e.g., 620) without a peripheral structure (e.g., 206). The design-forbidden area 204 may be an area on the substrate without an interconnection configured to be electrically coupled to an active device and / or a passive device of an integrated device. Therefore, the design-forbidden area 204 may not include an interconnection configured to be electrically coupled to an active device and / or a passive device of an integrated device. However, the design-keep region 204 may include at least one interconnect that is coupled to the peripheral structure (e.g., 206), but the at least one interconnect may be configured not to be electrically coupled to active devices (e.g., transistors) and / or passive devices (e.g., inductors, capacitors) of the integrated device. Note that the design-keep region 204 may include an interconnect 650 that is configured to be coupled to ground, but without any active devices and / or passive devices. In an example, the peripheral structure 206 may be coupled to the interconnect 650 that is configured to be coupled to ground. The first plurality of protection interconnects 260 and / or the second plurality of protection interconnects 262 may be coupled to the interconnect 650. The first plurality of protection interconnects 260 may be coupled to the second plurality of protection interconnects 262. The interconnect 650 may be coupled to an interconnect of the plurality of interconnects 640 that is configured to be coupled to ground (e.g., external ground, ground separated from the active devices of the circuit region 202). Interconnect 650 may be configured to be not electrically coupled to active devices and / or passive devices of integrated device 600. For example, pad 662 may be considered a pin coupled to ground, and interconnect 650 is coupled to at least one interconnect coupled to pad 662.

[0053] The peripheral structure 206 includes a first plurality of protection interconnects 260 and a second plurality of protection interconnects 262. The first plurality of protection interconnects 260 and the second plurality of protection interconnects 262 include five (5) metal layers. However, different implementations of the first plurality of protection interconnects 260 and the second plurality of protection interconnects 262 may include different numbers of metal layers (e.g., at least one metal layer, more than 5 metal layers). The first plurality of protection interconnects 260 and the second plurality of protection interconnects 262 may be located at least in the interconnect portion 604. As described below, at least in Figure 8 As further described in , the peripheral structure 206 may include a substrate via. Thus, a portion of the peripheral structure 206 (and / or any peripheral structure) may be located in and / or on a substrate (eg, 620) of an integrated device.

[0054] Figure 7 The integrated device 700 includes a cross-sectional view of a peripheral structure. The integrated device 600 may include a wafer level package (WLP). The integrated device 700 may represent Figure 2 The integrated device 700 may be similar to the cross-section AA of the integrated device 200. Figure 6 The integrated device 700 is an integrated device 600 and thus may include the same or similar components as the integrated device 600. The integrated device 700 includes a substrate 620, a plurality of device-level units 622 (e.g., logic units), an interconnect portion 604, and a packaging portion 706. The plurality of device-level units 622 are located and formed on the substrate 620. The plurality of device-level units 622 may form a device-level layer of the integrated device 700. In some implementations, the plurality of device-level units 622 may include portions of the substrate 620. In some implementations, the substrate 620, the device-level layer, and the plurality of device-level units 622 may be referred to as the substrate portion 602 of the integrated device 700.

[0055] The packaging portion 706 is formed on the interconnection portion 604 and is coupled to the interconnection portion. The packaging portion 706 includes a passivation layer 660, an under bump metallization (UBM) layer 762, and a solder interconnection 764. It should be noted that the size and shape of the integrated device 700 are exemplary. In addition, the components of the integrated device 700 shown may not be to scale.

[0056] As described above, the peripheral structure 206 can be coupled to ground. In one example, the peripheral structure 206 can be coupled to an interconnect 650 that is configured to be coupled to ground. The first plurality of protection interconnects 260 and / or the second plurality of protection interconnects 262 can be coupled to the interconnect 650. The first plurality of protection interconnects 260 can be coupled to the second plurality of protection interconnects 262. The interconnect 650 can be coupled to an interconnect in the plurality of interconnects 640 that is configured to be coupled to ground (e.g., an external ground, a ground separated from the active devices of the circuit area 202). For example, the UBM layer 762 and the solder interconnect 764 can be considered to be bumps coupled to ground, and the interconnect 650 is coupled to at least one interconnect that is coupled to the UBM layer 762 and the solder interconnect 764.

[0057] The integrated device (e.g., 200, 300, 400, 600, 700) may include a die (e.g., a bare die). The integrated device may include a radio frequency (RF) device, an analog device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a GaAs-based integrated device, a GaN-based integrated device, a memory, a power management processor, and / or a combination thereof.

[0058] The integrated device 600 and / or 700 may be implemented with a peripheral structure 306. Thus, the integrated device 600 and / or 700 may include a peripheral structure 306 including a first plurality of protection interconnects 360, a second plurality of protection interconnects 362, and a third plurality of protection interconnects 364, such as Figure 3 and / or Figure 4 as described.

[0059] Figure 8 A portion of a peripheral structure including a plurality of protective interconnects is illustrated. Figure 8 Peripheral structure 206 may be illustrated along cross section BB of integrated device 200. Peripheral structure 206 includes a plurality of protection interconnects 860. Plurality of protection interconnects 860 may represent first plurality of protection interconnects 260 and / or second plurality of protection interconnects 262.

[0060] Peripheral structure 206 is formed and located on substrate 620. Peripheral structure 206 can be part of an integrated device. Multiple protection interconnects 860 include interconnects located on substrate 620. For example, multiple protection interconnects 860 include multiple protection interconnects 801. Protection interconnects 801 include substrate vias, interconnects on various metal layers (e.g., M1, M2, M3, M4), and interconnects (e.g., vias, V1 vias, V2 vias, V3 vias) located between metal layers of integrated device 600. A buried oxide (BOX) layer 802 can be located on substrate 620 and coupled to substrate 620. A shallow trench isolation (STI) layer 804 can be located on BOX layer 802 and coupled to BOX layer 802. BOX layer 802 and STI layer 804 can be located in the lateral direction of multiple protection interconnects 801. Multiple protection interconnects 860 can be arranged in rows (and / or columns) of protection interconnects. Multiple protection interconnects 860 can be vertically staggered and / or offset. At least some of the protection interconnects 860 can be configured to be electrically coupled to each other. At least some of the protection interconnects 860 can be configured to be electrically coupled to ground. Various protection interconnects can each have similar or different lengths, widths, and / or thicknesses. For example, protection interconnects on different metal layers can have different thicknesses. At least one dielectric layer 642 can be formed around multiple protection interconnects 860.

[0061] Fig. 9 A portion of a peripheral structure including a plurality of protective interconnects is illustrated. Fig. 9 Peripheral structure 206 may be illustrated along cross section BB of integrated device 200. Peripheral structure 206 includes a plurality of protection interconnects 860 and a plurality of protection interconnects 960. A plurality of protection interconnects 860 may represent a first plurality of protection interconnects 260, and a plurality of protection interconnects 960 may represent a second plurality of protection interconnects 262. A plurality of protection interconnects 960 may be similar to a plurality of protection interconnects 860. Fig. 9 As shown in , the plurality of guarding interconnects 960 are staggered or offset from the plurality of guarding interconnects 860 .

[0062] As described above, some portions of the peripheral structure may be configured to: (i) not be electrically coupled to other portions of the peripheral structure; and / or (ii) not be coupled to ground when other portions of the peripheral structure may be configured to be coupled to ground.

[0063] Fig.10 A peripheral structure 1006 is illustrated, which includes a first portion 1002, a second portion 1003, and a third portion 1004. The peripheral structure 1006 may be located over the substrate 620. Fig.10 It can be expressed along Figure 2BB cross-sectional view of the peripheral structure 1006. The peripheral structure 1006 may include a plurality of protective interconnects 1060. The first portion 1002 of the peripheral structure 1006 may include a first plurality of protective interconnects 1020. The second portion 1003 of the peripheral structure 1006 may include a second plurality of protective interconnects 1030. The third portion 1004 of the peripheral structure 1006 may include a third plurality of protective interconnects 1040. The second portion 1003 is located between the first portion 1002 and the third portion 1004. The first plurality of protective interconnects 1020, the second plurality of protective interconnects 1030, and the third plurality of protective interconnects 1040 may be part of the plurality of protective interconnects 1060.

[0064] The first plurality of protection interconnects 1020 and the third plurality of protection interconnects 1040 can be configured to be electrically coupled to each other and / or to ground. The second plurality of protection interconnects 1030 are located between the first plurality of protection interconnects 1020 and the third plurality of protection interconnects 1040. The second plurality of protection interconnects 1030 can be configured to: (i) not be electrically coupled to the first plurality of protection interconnects 1020 and the third plurality of protection interconnects 1040; and / or (ii) not be electrically coupled to ground. In some implementations, at least one signal may be able to pass through the second portion 1003 of the peripheral structure 1006. Figure 4 As described in , the second portion 1003 may be an isolated portion of the peripheral structure 1006. The second portion 1003 may represent the isolated portion 404a or 404b.

[0065] Fig.11 Peripheral structure 1106 is illustrated as including at least one resistor. Peripheral structure 1106 is similar to peripheral structure 1006 and thus may include the same or similar components as peripheral structure 1006. Fig.11 It can be expressed along Figure 2BB cross-sectional view of the peripheral structure 1106. The peripheral structure 1106 includes at least one polysilicon layer 1102. The polysilicon layer 1102 can be coupled to the STI layer 804 and located above the STI layer 804. The peripheral structure 1106 can be tuned and / or modified by coupling or including at least one polysilicon layer 1102 to multiple protection interconnects 1060. Adding more polysilicon layers 1102 to the multiple protection interconnects 1060 and / or coupling more polysilicon layers 1102 to the multiple protection interconnects 1060 can increase the effective resistance of the peripheral structure 1006. At least one polysilicon layer 1102 can be used to provide a polysilicon resistor for changing the impedance of an electrical seal ring that may be required by a radio frequency (RF) circuit. In some implementations, the peripheral structure 1106 can be configured to be electrically coupled to at least one resistive region (e.g., a region of silicon) of the substrate to provide a resistor (e.g., a silicon resistor) for the electrical seal ring. The resistive region can include components of a transistor. In some implementations, the peripheral structure 1106 can be configured to be electrically coupled to at least one resistive region of the substrate and / or polysilicon layer 1102. At least one polysilicon layer 1102 and / or silicon resistor can be used to provide a resistor to change the impedance of an electrical seal ring that may be required by a radio frequency (RF) circuit. In some implementations, increasing the resistivity of the peripheral structure 1006 can help the peripheral structure 1006 be configured as a radio frequency (RF) decoupler. The polysilicon layer 1102 can include: a polysilicon layer including a p-dopant or a polysilicon layer including an N-dopant.

[0066] Note that the polysilicon layer 1102 can be part of or coupled to any peripheral structure described in the present disclosure. Figures 8 to 11 Peripheral structure 206 and / or peripheral structure 306 may be illustrated.

[0067] Fig.12 A plan view of a peripheral structure 1206 including three rows of multiple protection interconnects is shown. Fig.12 , the peripheral structure 1206 includes a first row of the first plurality of protection interconnects 1202, a second row of the second plurality of protection interconnects 1203, and a third row of the third plurality of protection interconnects 1204. The second row of the second plurality of protection interconnects 1203 can be laterally staggered with the first row of the first plurality of protection interconnects 1202. The third row of the third plurality of protection interconnects 1204 can be laterally staggered with the second row of the second plurality of protection interconnects 1203.

[0068] A first row of the first plurality of protection interconnects 1202 includes a plurality of protection interconnects 1220 (e.g., 1220a, 1220b, 1220c, 1220d), a plurality of protection interconnects 1222 (e.g., 1222a, 1222b, 1222c, 1222d), and a plurality of protection vias 1221. A second row of the second plurality of protection interconnects 1203 includes a plurality of protection interconnects 1230 (e.g., 1230a, 1230b, 1230c, 1230d), a plurality of protection interconnects 1232 (e.g., 1232a, 1232b, 1232c, 1232d), and a plurality of protection vias 1231. The third row of the third plurality of protection interconnects 1204 includes a plurality of protection interconnects 1240 (eg, 1240 a , 1240 b , 1240 c , 1240 d ), a plurality of protection interconnects 1242 (eg, 1242 a , 1242 b , 1242 c , 1242 d ), and a plurality of protection vias 1241 .

[0069] Fig.13 A side cross-sectional view of a first row of the first plurality of protection interconnects 1202 is shown. Fig.13 As shown in , the first row of the first plurality of protection interconnects 1202 includes vertically staggered protection interconnects. The first row of the first plurality of protection interconnects 1202 includes a plurality of protection interconnects 1220 (e.g., 1220a, 1220b, 1220c, 1220d), a plurality of protection interconnects 1222 (e.g., 1222a, 1222b, 1222c, 1222d), a plurality of protection interconnects 1224 (e.g., 1224a, 1224b, 1224c, 1224d), a plurality of protection vias 1221, a plurality of protection vias 1223, and a plurality of protection vias 1225.

[0070] A plurality of protection interconnects 1220, a plurality of protection interconnects 1222, a plurality of protection interconnects 1224, a plurality of protection vias 1221, a plurality of protection vias 1223, and a plurality of protection vias 1225 are coupled to each other. A plurality of protection interconnects 1220, a plurality of protection interconnects 1222, and a plurality of protection interconnects 1224 are vertically staggered. In some implementations, at least one via of the plurality of protection vias 1221, the plurality of protection vias 1223, and / or the plurality of protection vias 1225 may be a via bar (e.g., a protection via bar). Fig.13 A via 1223a from a plurality of protection vias 1223 is illustrated, the plurality of protection vias being configured as a via bar. A via bar can be coupled to two different interconnects on the same metal layer. Fig.13 In the example of FIG. 1 , via 1223a is coupled to protection interconnect 1222b, protection interconnect 1222c, and protection interconnect 1224b. The plurality of protection vias 1225 may be substrate vias (eg, substrate protection vias).

[0071] The second row of the second plurality of protection interconnects 1203 and the third row of the third plurality of protection interconnects 1204 may be arranged in a similar manner as the first row of the first plurality of protection interconnects 1202 .

[0072] Exemplary sequence for fabricating a peripheral structure over a substrate

[0073] In some implementations, manufacturing the peripheral structure includes several processes. FIG. 14A to FIG. 14G An exemplary sequence for providing or manufacturing a peripheral structure on a substrate is illustrated. In some implementations, FIG. 14A to FIG. 14G The sequence can be used to provide or make Fig.11 The peripheral structure 1106. However, FIG. 14A to FIG. 14G The process can be used to manufacture any peripheral structure described in this disclosure. FIG. 14A to FIG. 14G The process can be used to manufacture peripheral structures in integrated devices.

[0074] It should be noted that FIG. 14A to FIG. 14G The sequence of steps may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing the peripheral structure. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the spirit of the present disclosure.

[0075] like Fig.14A As shown in FIG. 6 , stage 1 illustrates a state after providing a substrate 620. The substrate 620 may include silicon (Si).

[0076] Stage 2 illustrates a state after forming a BOX layer 802 and a shallow trench isolation (STI) layer 804 over the substrate 620. The BOX layer 802 may include a buried oxide. The BOX layer 802 is formed over and coupled to the substrate 620. The STI layer 804 is formed over and coupled to the BOX layer 802. The BOX layer 802 and the STI layer 804 may be formed using a deposition process.

[0077] Stage 3 illustrates a state after polysilicon layer 1102 is formed over and coupled to STI layer 804. A deposition process may be used to form polysilicon layer 1102. Polysilicon layer 1102 may be optional.

[0078] like Fig. 14B As shown in FIG. 1 , stage 4 illustrates a state after forming a cavity 1402 in the BOX layer 802, the STI layer 804, and the polysilicon layer 1102. A laser process or / and an etching process may be used to form the cavity 1402.

[0079] Stage 5 illustrates a state after forming a plurality of protection interconnects 801 in cavity 1402. An electroplating process may be used to form the plurality of protection interconnects 801. The plurality of protection interconnects 801 may include substrate vias (eg, protection substrate vias). A portion of the plurality of protection interconnects 801 may be formed on top of polysilicon layer 1102.

[0080] Stage 6 illustrates a state after a dielectric layer 1410 is formed on the polysilicon layer 1102. If there is no polysilicon layer 1102, the dielectric layer 1410 can be formed on the STI layer 804. Different implementations can use different materials for the dielectric layer. The dielectric layer can be formed using a deposition process or a coating process.

[0081] like Fig. 14C As shown in , stage 7 illustrates a state after forming multiple protection interconnects 1412 over multiple protection interconnects 801 and dielectric layer 1410. An electroplating process can be used to form multiple protection interconnects 1412. Multiple protection interconnects 1412 may include traces and / or pads. Multiple protection interconnects 1412 may be coupled to multiple protection interconnects 801. Multiple protection interconnects 1412 may be coupled to polysilicon layer 1102. Multiple protection interconnects 1412 may be configured to be electrically coupled to polysilicon layer 1102 (e.g., through multiple protection interconnects 801). Multiple protection interconnects 1412 may include interconnects on M1 layer.

[0082] Stage 8 illustrates a state after a dielectric layer 1420 is formed over the plurality of protection interconnects 1412 and the dielectric layer 1410. Different implementations may use different materials for the dielectric layer. The dielectric layer may be formed using a deposition process or a coating process.

[0083] like Fig.14D As shown in FIG. 1 , stage 9 illustrates a state after a plurality of cavities 1421 are formed in the dielectric layer 1420. The plurality of cavities 1421 may be formed using an etching process (eg, a photo-etching process) or a laser process.

[0084] Stage 10 illustrates a state after forming a plurality of protection interconnects 1422 over the cavity 1421 and the dielectric layer 1420. An electroplating process may be used to form the plurality of protection interconnects 1422. The plurality of protection interconnects 1422 may include traces, pads, and / or vias. The plurality of protection interconnects 1422 may be coupled to the plurality of protection interconnects 1412. The plurality of protection interconnects 1422 may include interconnects on the M2 layer.

[0085] Stage 11 illustrates a state after a dielectric layer 1430 is formed over the plurality of protection interconnects 1422 and the dielectric layer 1420. Different implementations may use different materials for the dielectric layer. The dielectric layer may be formed using a deposition process or a coating process.

[0086] like Fig.14E As shown in FIG. 1 , stage 12 illustrates a state after a plurality of cavities 1431 are formed in the dielectric layer 1430. The plurality of cavities 1431 may be formed using an etching process (eg, a photolithography process) or a laser process.

[0087] Stage 13 illustrates a state after forming a plurality of protection interconnects 1432 over the cavity 1431 and the dielectric layer 1430. An electroplating process may be used to form the plurality of protection interconnects 1432. The plurality of protection interconnects 1432 may include traces, pads, and / or vias. The plurality of protection interconnects 1432 may be coupled to the plurality of protection interconnects 1422. The plurality of protection interconnects 1432 may include interconnects on the M3 layer.

[0088] like Fig.14F As shown in , stage 14 illustrates a state after a dielectric layer 1440 is formed over a plurality of protection interconnects 1432 and dielectric layer 1430. Different implementations may use different materials for the dielectric layer. The dielectric layer may be formed using a deposition process or a coating process.

[0089] Stage 15 illustrates a state after a plurality of cavities 1441 are formed in the dielectric layer 1440. The plurality of cavities 1441 may be formed using an etching process (eg, a photo-etching process) or a laser process.

[0090] like Figure 14G As shown in , stage 16 illustrates a state after forming a plurality of protection interconnects 1442 over the cavity 1441 and the dielectric layer 1440. An electroplating process may be used to form the plurality of protection interconnects 1442. The plurality of protection interconnects 1442 may include traces, pads, and / or vias. The plurality of protection interconnects 1442 may be coupled to the plurality of protection interconnects 1432. The plurality of protection interconnects 1442 may include interconnects on the M4 layer.

[0091] Stage 17 illustrates a state after dielectric layer 1450 is formed over multiple protection interconnects 1442 and dielectric layer 1440. Different implementations may use different materials for the dielectric layer. A deposition process or a coating process may be used to form the dielectric layer. Dielectric layers 1410, 1420, 1430, 1440, and / or 1450 may be represented by dielectric layer 642.

[0092] Stage 17 may illustrate a peripheral structure 1106 including a plurality of protection interconnects 1060 (eg, 206). The plurality of protection interconnects 1060 may include a plurality of protection interconnects 801, 1412, 1422, 1432, and / or 1442.

[0093] Notice that FIG. 14A to FIG. 14G The process can be used to fabricate peripheral structures including various numbers of metal layers, including peripheral structures having less than 4 metal layers or more than 4 metal layers.

[0094] Different implementations may use different processes to form the metal layer. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process are used to form the metal layer. For example, a sputtering process, a spraying process, and / or an electroplating process may be used to form the metal layer.

[0095] Exemplary flow chart of a method for fabricating a peripheral structure on a substrate

[0096] In some implementations, manufacturing the peripheral structure includes several processes. Fig.15 An exemplary flow chart of a method 1500 for providing or manufacturing a peripheral structure configured to operate as an electrical ring seal and a mechanical crack stop is illustrated. In some implementations, Fig.15 The method 1500 can be used to provide or manufacture Figure 2 For example, Fig.15 The method 1500 may be used to fabricate the peripheral structure 206. However, the method 1500 may be used to fabricate any peripheral structure described in the present disclosure and / or peripheral structures having a different number of metal layers.

[0097] It should be noted that Fig.15 The sequence of one or more processes may be combined to simplify and / or clarify the method for providing or manufacturing a peripheral structure. In some implementations, the order of the processes may be changed or modified.

[0098] The method provides (at 1505) a substrate 620. The substrate 620 may include silicon (Si). Fig.14A Stage 1 of the diagram illustrates an example of a provided substrate.

[0099] The method forms (at 1510) a BOX layer 802 and a shallow trench isolation (STI) layer 804 over the substrate 620. The BOX layer 802 may include a buried oxide. The BOX layer 802 is formed over the substrate 620. The STI layer 804 is formed over the BOX layer 802. The BOX layer 802 and the STI layer 804 may be formed using a deposition process. Fig.14A Stage 2 of FIG. 1 illustrates an example of a BOX layer and an STI layer formed over a substrate.

[0100] The method optionally forms (at 1515) a polysilicon layer 1102 over the STI layer 804. The polysilicon layer 1102 may be formed using a deposition process. Fig.14A Stage 3 of FIG. 1 illustrates an example of forming a polysilicon layer over the STI layer.

[0101] The method forms (at 1520) a plurality of protection interconnects 801. The plurality of protection interconnects 801 may be protection substrate vias. The plurality of protection interconnects 801 may be formed in cavities of the BOX layer 802, the STI layer 804, and the polysilicon layers 1102, 1402. An electroplating process may be used to form the plurality of protection interconnects 801. The plurality of protection interconnects 801 may be coupled to the polysilicon layer 1102. Forming the plurality of protection interconnects 801 may include forming cavities in the BOX layer, the STI layer, and the polysilicon layer. Fig. 14B Stages 4-5 illustrate an example of forming a protection interconnect, such as a protection substrate via.

[0102] The method forms (at 1525) at least one protective interconnect (e.g., 1412) and at least one dielectric layer (e.g., 1410, 1420). The dielectric layer may be formed using a deposition process or a coating process. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1412) in the dielectric layer (e.g., 1410). An etching process (e.g., photoetching) or a laser process may be used to form the plurality of cavities. An electroplating process may be used to form the protective interconnects (e.g., 1412, 1422). Forming the protective interconnect may include providing a patterned metal layer on and / or in the dielectric layer. Forming the protective interconnect may include forming a plurality of protective vias. In some implementations, the dielectric layer and the protective interconnect may be formed alternatively. FIG. 14C to FIG. 14G Stages 6-16 illustrate an example of forming at least one protective interconnect and at least one dielectric layer.

[0103] Different implementations may use different processes to form the metal layer. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process is used to form the metal layer(s). For example, a sputtering process, a spraying process, and / or an electroplating process may be used to form the metal layer.

[0104] Exemplary sequence for fabricating an integrated device including peripheral structures

[0105] In some implementations, fabricating an integrated device including a peripheral structure includes several processes. FIG. 16A to FIG. 16B An exemplary sequence for providing or manufacturing an integrated device including a peripheral structure configured to operate as an electrical ring seal and a mechanical crack stop is illustrated. In some implementations, FIG. 16A to FIG. 16BThe sequence can be used to provide or make Figure 7 integrated devices and / or other integrated devices described in the present disclosure.

[0106] It should be noted that FIG. 16A to FIG. 16B The sequence of steps may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing an integrated device including peripheral structures. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the spirit of the present disclosure.

[0107] like Fig.16A As shown in , stage 1 illustrates a state after providing a substrate 620. Different implementations may provide different materials for the substrate 620. In some implementations, the substrate 620 may include silicon (Si). The substrate 620 may be doped or undoped. The substrate 620 may be a semi-insulating substrate.

[0108] Stage 2 illustrates a state after a device level layer is formed on substrate 1620. The device level layer includes a plurality of device level cells 622. Therefore, stage 2 illustrates a state after a plurality of device level cells 622 are formed on substrate 620. In some implementations, a front end of line (FEOL) process can be used to manufacture the device level layer (e.g., a plurality of device level cells 622). One or more cells from the plurality of device level cells can include transistors and / or gate contacts. In some implementations, an interconnect can be formed on the gate, source, and / or drain of one or more transistors. A plurality of device level cells 622 can be formed in circuit region 202.

[0109] Stage 3 illustrates a state after forming interconnect portion 604. Interconnect portion 604 may include multiple interconnects 640 (located on different metal layers) and at least one dielectric layer 642. Multiple interconnects 640 may be formed and located in circuit region 202. In some implementations, a back-end of line (BEOL) process may be used to manufacture interconnect portion 604. Interconnect portion 604 may be configured to electrically couple one or more transistors. Forming interconnect portion 604 may include forming peripheral structures (e.g., 206) that include multiple protection interconnects 260 and multiple protection interconnects 262. Although not shown in stage 3, interconnect portion 604 may include interconnect 650 that is configured to couple to ground and peripheral structures, such as Figure 6 and Figure 7 As shown in .

[0110] like Fig. 16BAs shown in FIG. 4 , stage 4 illustrates a state after forming a passivation layer 660 and an under bump metallization (UBM) layer 762 over the interconnection portion 604. The passivation layer 660 may be formed using a deposition process. The UBM layer 762 may be formed using an electroplating process.

[0111] Stage 5 illustrates a state after the solder interconnect 764 is coupled to the under bump metallization (UBM) layer 762. A reflow process may be used to couple the solder interconnect 764 to the UBM layer 762. Stage 5 may illustrate the integrated device 700 including the peripheral structure 206 configured to operate as an electrical sealing ring and crack stopper for the integrated device.

[0112] Exemplary flow chart of a method for manufacturing an integrated device including a peripheral structure

[0113] In some implementations, providing an integrated device including a peripheral structure includes several processes. Fig.17 An exemplary flow chart of a method 1700 for providing or manufacturing an integrated device including a peripheral structure configured to operate as an electrical sealing ring and a mechanical crack stop is illustrated. In some implementations, Fig.17 The method 1700 can be used to provide or manufacture Figure 7 integrated devices and / or other integrated devices described in the present disclosure.

[0114] It should be noted that Fig.17 The method may combine one or more processes to simplify and / or clarify a method for providing or manufacturing an integrated device including a peripheral structure configured to operate as an electrical sealing ring and a crack stopper. In some implementations, the order of the processes may be changed or modified.

[0115] The method provides (at 1705) a substrate (e.g., 620). Different implementations may provide different materials for the substrate. In some implementations, the substrate may include silicon (Si). The substrate may be doped with an N-type dopant or a P-type dopant. The substrate may be a semi-insulating substrate. Fig.16A Stage 1 of the diagram illustrates an example of providing a substrate.

[0116] The method forms (at 1710) a device-level layer (e.g., a plurality of device-level cells 622) over a substrate. In some implementations, a front-end-of-line (FEOL) process may be used to fabricate the device-level layer (e.g., a plurality of device-level cells 622). The device-level layer may include a plurality of device-level cells. The device-level cell may include one or more active devices. One or more device-level cells may include transistors. Forming the device-level layer may include forming one or more transistors. In some implementations, forming the device-level layer includes forming transistors over a substrate. The device-level layer may be formed within a circuit region over a substrate such that a design-forbidden region is formed or defined over the substrate, wherein the design-forbidden region laterally surrounds the circuit region. Fig.16A Stage 2 of FIG. 1 illustrates an example of forming device level layers.

[0117] The method forms (at 1715) an interconnect 604 over a device-level layer (e.g., a plurality of device-level cells 622) and / or a substrate 620. The interconnect 604 may include a plurality of interconnects 1640 and at least one dielectric layer 642. In some implementations, a back-end-of-line (BEOL) process may be used to form the interconnect 604. The interconnect 604 may include an M1 layer. The interconnect 604 may be configured to electrically couple one or more transistors. Forming the interconnect 604 may also include forming a peripheral structure including a plurality of protective interconnects (e.g., a first plurality of protective interconnects) laterally surrounding a design-keep region, wherein the peripheral structure is configured to operate as an electrical sealing ring and a mechanical crack stop. Fig.16A Stage 3 of illustrative embodiments illustrates an example of forming an interconnect portion 604 that includes a peripheral structure including a plurality of protective interconnects.

[0118] The method forms (at 1720) a package portion 706 over the interconnect portion 604. The package portion 706 may include a passivation layer 660 and an under bump metallization (UBM) layer 762. The passivation layer 660 and the under bump metallization (UBM) layer 762 are formed over the interconnect portion 604. Fig. 16B Stage 4 of the diagram illustrates an example of forming a package portion.

[0119] The method provides (at 1725) a solder interconnect 764. In some implementations, the solder interconnect 764 is coupled to an under bump metallization (UBM) layer 762 by a solder reflow process. Fig. 16B Stage 5 of illustrates an example of coupling a solder interconnect to a package portion.

[0120] Also note that Fig.17The method 1700 can be used to manufacture (e.g., simultaneously manufacture) several integrated devices on a wafer. The wafer is then singulated (e.g., cut) into individual integrated devices. These singulated integrated devices can then be coupled to other integrated devices and / or a printed circuit board (PCB).

[0121] Exemplary Electronic Devices

[0122] Fig.18 Various electronic devices are illustrated that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1802, a laptop computer device 1804, a fixed location terminal device 1806, a wearable device 1808, or a motor vehicle 1810 can include a device 1800 as described herein. The device 1800 can be, for example, any device and / or integrated circuit (IC) package described herein. Fig.18 Devices 1802, 1804, 1806, and 1808 and vehicle 1810 illustrated in the figure are exemplary only. Other electronic devices may also feature device 1800, including but not limited to the group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0123] Figures 2 to 13 , FIG. 14A to FIG. 14G , Fig.15 , FIG. 16A to FIG. 16B and / or Figure 17 to Figure 18 One or more components, processes, features, and / or functions illustrated in the drawings may be rearranged and / or combined into a single component, process, feature, or function, or implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figures 2 to 13 , 14A to Figure 14G , Fig.15 , FIG. 16A to FIG. 16B and / or Figure 17 to Figure 18and its corresponding description in this disclosure are not limited to die and / or IC. In some implementations, Figures 2 to 13 , FIG. 14A to FIG. 14G , Fig.15 , FIG. 16A to FIG. 16B and / or Figure 17 to Figure 18 The invention and its corresponding description may be used to manufacture, create, provide and / or produce a device and / or an integrated device. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink and / or an interposer.

[0124] Note that the drawings in this disclosure may represent actual representations and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits and / or transistors. In some cases, the drawings may not be drawn to scale. In some cases, for clarity, not all components and / or parts may be shown. In some cases, the positions, locations, sizes and / or shapes of various components and / or parts in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0125] The term "exemplary" as used herein means "serving as an example, instance or illustration". Any implementation or aspect described herein as "exemplary" is not necessarily to be interpreted as being more preferred or advantageous than other aspects of the present disclosure. Likewise, the term "aspect" does not require that all aspects of the present disclosure include the features, advantages or modes of operation discussed. The term "coupling" as used herein refers to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, then objects A and C can still be considered to be coupled to each other - even if they are not in direct physical contact with each other. The term "electrical coupling" may mean that two objects are coupled together directly or indirectly so that an electric current (e.g., signal, power supply, ground) can travel between the two objects. Two electrically coupled objects may or may not have an electric current traveling between the two objects. Electromagnetic coupling may mean that a signal from one circuit and / or component affects a signal from another circuit and / or component. Electromagnetic coupling may cause crosstalk. Electromagnetic coupling may be a form of signal coupling. The use of the terms "first", "second", "third" and "fourth" (and / or any higher than fourth) is arbitrary. Any component described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may be a first component, a second component, a third component, or a fourth component. The terms "top" and "bottom" are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may be considered a bottom component, and vice versa. The term "encapsulate" means that the object may partially encapsulate or completely encapsulate another object. The term "surrounding" means that an object may partially surround or completely surround another object. It is also noted that the term "above" as used in the context of one component being above another component in this application may be used to indicate a component that is above another component and / or in another component (e.g., above the surface of a component or embedded in a component). Thus, for example, a first component above a second component may mean (1) that the first component is above the second component, but does not directly contact the second component, (2) that the first component is above the second component (e.g., above its surface), and / or (3) that the first component is in the second component (e.g., embedded therein). The term "about 'value X'" or "approximately value X" as used in the present disclosure means within 10% of "value X". For example, a value of about 1 or a value approximately 1 means a value in the range of 0.9 to 1.1.

[0126] In some implementations, the interconnect is an element or component of a device or package that allows or facilitates electrical connection between two points, elements and / or components. In some implementations, the interconnect may include traces, vias, pads, columns, redistributed metal layers and / or under bump metallization (UBM) layers. In some implementations, the interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), grounding and / or power supply. The interconnect may be part of a circuit. The interconnect may include more than one element or component. The interconnect may be defined by one or more interconnects. Different implementations may use different processes and / or sequences to form the interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spraying process and / or an electroplating process may be used to form the interconnect.

[0127] In addition, it should be noted that the various disclosures contained herein can be described as processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although a job chart can describe an operation as a sequential process, many operations can be performed in parallel or simultaneously. In addition, the order of the operations can be rearranged. When the operations of a process are completed, the process terminates.

[0128] Without departing from the present disclosure, the various features of the present disclosure described herein can be implemented in different systems. It should be noted that the foregoing aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to illustrate, rather than to limit the scope of the claims. Therefore, the present teachings can be easily applied to other types of devices, and many replacements, modifications, and variations are apparent to those skilled in the art.

Claims

1. An integrated device comprising: substrate; A circuit region, located on the substrate; A design forbidden area, located on the substrate, the design forbidden area laterally surrounding the circuit area; as well as a peripheral structure over the substrate, the peripheral structure comprising a first plurality of peripheral protection interconnects laterally surrounding the design keep-out area, wherein the peripheral structure is configured to operate as an electrical sealing ring and a mechanical crack stop, wherein the first plurality of peripheral protection interconnects include (i) a plurality of first protection interconnects located on a first metal layer, and (ii) a plurality of second protection interconnects located on a second metal layer, wherein the second metal layer is located above the first metal layer, wherein the plurality of first protection interconnects comprises a first interconnect, wherein the plurality of second protection portion interconnections include a second interconnection portion and a third interconnection portion, wherein the second interconnect on the second metal layer vertically overlaps the first interconnect on the first metal layer, wherein the third interconnect on the second metal layer vertically overlaps the first interconnect on the first metal layer, wherein the second interconnect is offset from the first interconnect along a length of the first interconnect, and Wherein the third interconnect is offset from the first interconnect along a length of the first interconnect. 2 . The integrated device according to claim 1 , wherein the plurality of second protection interconnects on the second metal layer are vertically staggered with the plurality of first protection interconnects on the first metal layer. 3 . The integrated device of claim 1 , wherein the peripheral structure further comprises a second plurality of peripheral protection interconnects, the second plurality of peripheral protection interconnects laterally surrounding the first plurality of peripheral protection interconnects. 4 . The integrated device of claim 3 , wherein the second plurality of peripheral protection interconnects are laterally staggered from the first plurality of peripheral protection interconnects. 5 . The integrated device of claim 1 , wherein the first plurality of peripheral protection interconnects are configured to be coupled to ground.

6. The integrated device according to claim 1, wherein at least one protection interconnect from the first plurality of peripheral protection interconnects is configured to be coupled to ground; and Wherein at least one protection interconnect from the first plurality of peripheral protection interconnects is configured to not be electrically coupled to ground.

7. The integrated device according to claim 1, wherein the integrated device comprises at least one shallow trench isolation layer located in the substrate, wherein the first plurality of peripheral protection interconnects include substrate vias, and The substrate via is positioned transversely to the at least one shallow trench isolation layer.

8. The integrated device of claim 1, wherein the first plurality of peripheral protection interconnects are coupled to a polysilicon layer.

9. The integrated device according to claim 1, wherein the circuit area includes a plurality of circuit components, and There are no active components in the design-forbidden area.

10. The integrated device of claim 1, wherein the integrated device is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

11. The integrated device according to claim 1, wherein the first plurality of peripheral protection interconnects further comprises a plurality of third protection interconnects located on a third metal layer, wherein the third metal layer is located above the second metal layer, wherein the plurality of third protection interconnects include a fourth interconnect, wherein the fourth interconnect on the third metal layer vertically overlaps the first interconnect on the first metal layer, wherein the fourth interconnect on the third metal layer vertically overlaps (i) a portion of the second interconnect on the second metal layer and (ii) a portion of the third interconnect on the second metal layer, wherein the fourth interconnect is offset from the second interconnect, and Wherein the fourth interconnect is offset from the third interconnect.

12. An apparatus comprising: substrate; A circuit region, located on the substrate; A design forbidden area, located on the substrate, the design forbidden area laterally surrounding the circuit area; as well as a component for peripheral protection laterally surrounding the design keep-out area, the component for peripheral protection comprising a first plurality of peripheral protection interconnects, wherein the component for peripheral protection is configured to operate as an electrical sealing ring and a mechanical crack stop, wherein the component for peripheral protection includes (i) a plurality of first protection interconnects located on a first metal layer, (ii) a plurality of second protection interconnects located on a second metal layer, and (iii) a plurality of vias coupled to the plurality of first protection interconnects and the plurality of second protection interconnects, wherein the second metal layer is located above the first metal layer, wherein the plurality of vias are located between the first metal layer and the second metal layer, wherein the plurality of first protection interconnects comprises a first interconnect, wherein the plurality of second protection interconnects include a second interconnect and a third interconnect, wherein the plurality of vias include a first via and a second via, wherein the second interconnect on the second metal layer vertically overlaps the first interconnect on the first metal layer, wherein the third interconnect on the second metal layer vertically overlaps the first interconnect on the first metal layer, wherein the second interconnect is offset from the first interconnect along the length of the first interconnect, wherein the third interconnect is offset from the first interconnect along the length of the first interconnect, wherein the first via is coupled to the first interconnect and the second interconnect, and Wherein the second via is coupled to the first interconnect and the third interconnect. 13 . The device of claim 12 , wherein the plurality of second protection interconnects on the second metal layer are vertically staggered with the plurality of first protection interconnects on the first metal layer.

14. The apparatus of claim 13, wherein the means for peripheral protection further comprises a second plurality of peripheral protection interconnects laterally surrounding the first plurality of peripheral protection interconnects.

15. The apparatus of claim 14, wherein the second plurality of peripheral protection interconnects are laterally staggered from the first plurality of peripheral protection interconnects. The apparatus of claim 13 , wherein the first plurality of peripheral protection interconnects are configured to be coupled to ground.

17. The device according to claim 12, wherein at least one protection interconnect from the first plurality of peripheral protection interconnects is configured to be coupled to ground; and Wherein at least one protection interconnect from the first plurality of peripheral protection interconnects is configured to not be electrically coupled to ground.

18. The device according to claim 12, wherein the substrate comprises at least one shallow trench isolation layer, The components for peripheral protection include substrate vias, and The substrate via is positioned transversely to the at least one shallow trench isolation layer.

19. The device of claim 12, wherein the means for peripheral protection is coupled to a polysilicon layer.

20. The device according to claim 12, wherein the circuit area includes a plurality of circuit components, and There are no active components in the design-forbidden area.

21. The apparatus of claim 12, wherein the apparatus is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

22. A method comprising: providing a substrate; forming a circuit region on the substrate so that a design-forbidden region exists on the substrate, wherein the design-forbidden region laterally surrounds the circuit region; as well as forming a peripheral structure over the substrate, the peripheral structure comprising a first plurality of peripheral protection interconnects laterally surrounding the design keep-out area, wherein the peripheral structure is configured to operate as an electrical seal ring and a mechanical crack stop, wherein the first plurality of peripheral protection interconnects include (i) a plurality of first protection interconnects located on a first metal layer, and (ii) a plurality of second protection interconnects located on a second metal layer, wherein the second metal layer is located above the first metal layer, wherein the plurality of first protection interconnects comprises a first interconnect, wherein the plurality of second protection portion interconnections include a second interconnection portion and a third interconnection portion, wherein the second interconnect on the second metal layer vertically overlaps the first interconnect on the first metal layer, wherein the third interconnect on the second metal layer vertically overlaps the first interconnect on the first metal layer, wherein the second interconnect is offset from the first interconnect along the length of the first interconnect, Wherein the third interconnect is offset from the first interconnect along a length of the first interconnect. 23 . The method of claim 22 , wherein the plurality of second protection interconnects on the second metal layer are vertically staggered with the plurality of first protection interconnects on the first metal layer.

24. The method of claim 22, wherein the peripheral structure further comprises a second plurality of peripheral protection interconnects laterally surrounding the first plurality of peripheral protection interconnects.

25. The method of claim 24, wherein the second plurality of peripheral protection interconnects are laterally staggered from the first plurality of peripheral protection interconnects.

26. The method of claim 22, wherein the peripheral structure is coupled to a polysilicon layer.

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