Display substrate, manufacturing method thereof, and display device

Abstract

A display substrate, a manufacturing method thereof, and a display device, belonging to the field of display technology. The display substrate includes a base substrate (00) having a first display area (A1) and a second display area (A2). In a pixel circuit (10) included in a pixel (P1) within the second display area (A2), a conductive line connected to a metal layer (101, 104) is a transparent conductive line (L1), and the transparent conductive line (L1) is located between two existing insulating layers (102, 103). In this way, compared to a display substrate in which the transparent conductive line (L1) is located at other positions, not only is the light transmittance of the second display area (A2) better, but the structure is also simpler and the manufacturing cost is lower.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] Under-screen camera technology is a new technology proposed to increase the screen-to-body ratio of display devices.

[0003] In related art, a display substrate with an under-display camera typically includes a light-transmitting display area for mounting the camera, and this light-transmitting display area includes multiple pixels. Furthermore, to ensure the transmittance of the light-transmitting display area, the connecting lines within each pixel in the light-transmitting display area need to use transparent conductive traces.

[0004] However, the structure of the display substrate in the related art is relatively complex and the manufacturing cost is relatively high. Summary of the Invention

[0005] This application provides a display substrate and a manufacturing method thereof, and a display device. The technical solution is as follows:

[0006] In one aspect, a display substrate is provided, comprising:

[0007] A base substrate having a first display area and a second display area, wherein the first display area at least partially surrounds the second display area;

[0008] Multiple pixels, each pixel includes a pixel circuit and a target electrode connected to each other, the pixel circuit is located in the first display area or the second display area, and the target electrode is located in the second display area; the pixel circuit includes: a first metal layer, a first insulating layer, at least one transparent conductive line, a second insulating layer, and a second metal layer, which are located on one side of the base substrate and are stacked in sequence, and each of the transparent conductive lines is connected to a metal layer in the pixel circuit.

[0009] Optionally, the first metal layer is a first source-drain metal layer, the second metal layer is a second source-drain metal layer, the first insulating layer is a passivation layer, and the second insulating layer is a first planarization layer.

[0010] Optionally, the material of each transparent conductive line is indium tin oxide.

[0011] Optionally, the target electrode is an anode.

[0012] Optionally, the pixel circuit is located in the second display area, and an orthographic projection of the pixel circuit on the base substrate at least partially overlaps with an orthographic projection of the target electrode on the base substrate.

[0013] Optionally, the pixel circuit is located in the first display area, and the pixel circuit is connected to the target electrode through the transparent conductive line.

[0014] Optionally, the at least one transparent conductive line includes: a first transparent conductive line;

[0015] The first transparent conductive line is connected to the first metal layer and is configured to transmit a power signal. The first transparent conductive lines in two adjacent pixel circuits located in the same column form an integrated structure.

[0016] Optionally, the at least one transparent conductive line includes: a second transparent conductive line;

[0017] The second transparent conductive line is connected to the second metal layer and is configured to transmit a data signal. The second transparent conductive lines in two adjacent pixel circuits located in the same column form an integrated structure.

[0018] Optionally, the pixel circuit also includes: a third insulating layer located on the side of the second metal layer away from the base substrate, and a transistor pattern layer, a third metal layer, a fourth metal layer and a fourth insulating layer located between the base substrate and the first metal layer and stacked in sequence in a direction away from the base substrate.

[0019] Optionally, the third insulating layer is a second planar layer, the third metal layer is a first gate metal layer, the fourth metal layer is a second gate metal layer, and the fourth insulating layer is an interlayer dielectric layer.

[0020] Optionally, the third metal layer includes a first portion, a second portion, and a third portion; the at least one transparent conductive line includes: a third transparent conductive line, a fourth transparent conductive line, and a fifth transparent conductive line;

[0021] The third transparent conductive line is connected to the first portion and is configured to transmit a light emitting control signal, wherein the third transparent conductive lines in two adjacent pixel circuits located in the same row form an integrated structure;

[0022] The fourth transparent conductive line is connected to the second portion and is configured to transmit a gate drive signal, wherein the fourth transparent conductive lines in two adjacent pixel circuits located in the same row form an integrated structure;

[0023] The fifth transparent conductive line is connected to the third portion and is configured to transmit a reset signal. The fifth transparent conductive lines in two adjacent pixel circuits located in the same row are an integrated structure.

[0024] Optionally, the at least one transparent conductive line includes: a sixth transparent conductive line;

[0025] The sixth transparent conductive line is connected to the fourth metal layer and is configured to transmit an initial signal. The sixth transparent conductive lines in two adjacent pixel circuits located in the same row are an integrated structure.

[0026] Optionally, the second display area is a light-transmitting display area.

[0027] Optionally, the resolution of the first display area is greater than or equal to the resolution of the second display area.

[0028] Optionally, each of the transparent conductive lines is connected to a metal layer in the pixel circuit through a via.

[0029] In another aspect, a method for manufacturing a display substrate is provided, the method comprising:

[0030] Providing a base substrate, the base substrate having a first display area and a second display area, wherein the first display area at least partially surrounds the second display area;

[0031] forming a plurality of pixels on one side of the substrate, each of the pixels comprising a pixel circuit and a target electrode connected to each other;

[0032] The pixel circuit is located in the first display area or the second display area, and the target electrode is located in the second display area; the pixel circuit includes a first metal layer, a first insulating layer, at least one transparent conductive line, a second insulating layer and a second metal layer stacked in sequence in a direction away from the base substrate, and each of the transparent conductive lines is connected to a metal layer in the pixel circuit.

[0033] In another aspect, a display device is provided, comprising: an integrated circuit, and the display substrate according to the above aspect;

[0034] The integrated circuit is electrically connected to a transparent conductive line included in a pixel circuit in the display substrate, and the integrated circuit is used to provide a signal to the transparent conductive line.

[0035] Optionally, the display device further includes a photosensor, and the photosensor is located in the second display area of ​​the display substrate.

[0036] Optionally, the second display area is rectangular, and the orthographic projection area of ​​the photosensor on the base substrate is smaller than or equal to the area of ​​the inscribed circle of the second display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0038] Figure 1 This is a schematic structural diagram of a display substrate provided in an embodiment of the present application;

[0039] Figure 2 is a schematic structural diagram of another display substrate provided in an embodiment of the present application;

[0040] Figure 3 This is a schematic structural diagram of another display substrate provided in an embodiment of the present application;

[0041] Figure 4 1 is a schematic diagram of a hierarchical structure of a pixel circuit provided in an embodiment of the present application;

[0042] Figure 5 is a schematic diagram of the hierarchical structure of another pixel circuit provided in an embodiment of the present application;

[0043] Figure 6 is a schematic diagram of a hierarchical structure of another pixel circuit provided in an embodiment of the present application;

[0044] Figure 7 This is a schematic structural diagram of another display substrate provided in an embodiment of the present application;

[0045] Figure 8 This is a schematic structural diagram of another display substrate provided in an embodiment of the present application;

[0046] Figure 9 1 is a schematic diagram of a hierarchical structure of a pixel circuit including a via hole provided in an embodiment of the present application;

[0047] Figure 10 This is another schematic diagram of a pixel circuit hierarchical structure including a via provided in an embodiment of the present application;

[0048] Figure 11 This is another schematic diagram of a pixel circuit hierarchical structure including a via provided in an embodiment of the present application;

[0049] Figure 12 This is a schematic structural diagram of another display substrate provided in an embodiment of the present application;

[0050] Figure 13 This is a flow chart of a method for manufacturing a display substrate provided in an embodiment of the present application;

[0051] Figure 14is a flow chart of another method for manufacturing a display substrate provided in an embodiment of the present application;

[0052] Figure 15 A display substrate structure layout including a transistor pattern layer provided in an embodiment of the present application;

[0053] Figure 16 The embodiment of the present application provides a display substrate structure layout including a transistor pattern layer and a first gate metal layer;

[0054] Figure 17 The embodiment of the present application provides a display substrate structure layout including a transistor pattern layer, a first gate metal layer, and a second gate metal layer;

[0055] Figure 18 The embodiment of the present application provides a display substrate structure layout including a transistor pattern layer, a first gate metal layer, a second gate metal layer and a via hole;

[0056] Figure 19 The embodiment of the present application provides a display substrate structure layout including a transistor pattern layer, a first gate metal layer, a second gate metal layer, a via hole, and a first source and drain metal layer;

[0057] Figure 20 Another display substrate structure provided by an embodiment of the present application includes a transistor pattern layer, a first gate metal layer, a second gate metal layer, a via, and a first source and drain metal layer;

[0058] Figure 21 The embodiment of the present application provides a display substrate structure layout including a transistor pattern layer, a first gate metal layer, a second gate metal layer, a via, a first source and drain metal layer, and a transparent conductive line;

[0059] Figure 22 Another display substrate structure provided by an embodiment of the present application includes a transistor pattern layer, a first gate metal layer, a second gate metal layer, a via, a first source and drain metal layer, and a transparent conductive line;

[0060] Figure 23 The present invention provides a display substrate structure layout including a transistor pattern layer, a first gate metal layer, a second gate metal layer, a via, a first source-drain metal layer, a transparent conductive line, and a second source-drain metal layer.

[0061] Figure 24 Another display substrate structure provided by an embodiment of the present application includes a transistor pattern layer, a first gate metal layer, a second gate metal layer, a via, a first source and drain metal layer, a transparent conductive line, and a second source and drain metal layer;

[0062] Figure 25 The present invention provides a display substrate structure layout including a transistor pattern layer, a first gate metal layer, a second gate metal layer, a via, a first source-drain metal layer, a transparent conductive line, a second source-drain metal layer, and an anode.

[0063] Figure 26 It is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0064] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0065] Figure 1 Schematic diagram of the structure of a display substrate provided in an embodiment of the present application. Figure 1 As shown, the display substrate may include: a base substrate 00 , the base substrate 00 may have a first display area A1 and a second display area A2 , and the first display area A1 may at least partially surround the second display area A2 .

[0066] For example, reference Figure 1 , the second display area A2 shown is located in the middle of the top of the base substrate 00. Accordingly, the four sides of the rectangular second display area A2 can be surrounded by the first display area A1, that is, the second display area A2 can be surrounded by the first display area A1.

[0067] In some embodiments, the second display area A2 may not be located at Figure 1 The substrate 00 is not located at the top center position, but is located at other positions. Figure 1 , the second display area A2 may be located at the upper left corner or the upper right corner of the base substrate 00. This embodiment of the present application does not limit this.

[0068] Alternatively, the first display area A1 can be configured as a non-transparent display area, while the second display area A2 can be configured as a translucent display area. That is, the first display area A1 is opaque, while the second display area A2 is translucent. This eliminates the need for a hole in the display substrate, allowing the required hardware, such as the light sensor, to be placed directly within the second display area A2, laying a solid foundation for achieving a true full display.

[0069] Figure 2 This is a schematic structural diagram of another display substrate provided in an embodiment of the present application. Figure 3 This is a structural diagram of another display substrate provided in an embodiment of the present application. Figures 1 to 3It can be seen that the display substrate may further include: a plurality of pixels P1, and each pixel P1 may include a pixel circuit 10 and a target electrode 20 connected to each other. Optionally, the pixel circuit 10 may provide a driving signal to the target electrode 20, so that a potential difference is formed between the target electrode 20 and another electrode included in the pixel P1, and the pixel P1 emits light.

[0070] Optional, reference Figure 2 and Figure 3 , the target electrode 20 included in each pixel P1 can be located in the second display area A2, thereby determining that the multiple pixels P1 all belong to the second display area A2, that is, all are pixels in the second display area A2. Figure 2 , the pixel circuit 10 included in each pixel P1 can be located in the second display area A2, that is, the pixel circuit 10 included in each pixel P1 can be built into the second display area A2 together with the connected target electrode 20, which can also be called pixel circuit built-in. Or, refer to Figure 3 The pixel circuit 10 included in each pixel P1 can be located in the first display area A1, that is, the pixel circuit 10 included in each pixel P1 can be individually placed outside the first display area A1, which can also be called external pixel circuit. Of course, some pixel circuits can also be built in and some pixel circuits can be external.

[0071] Combining the above description of the first display area A1 and the second display area A2, it can be seen that if the pixel circuit 10 is placed outside the first display area A1, the light transmittance of the second display area A2 can be improved. Of course, if the pixel circuit 10 is built into the second display area A2, the wiring process can be simplified and costs can be saved.

[0072] Figure 4 1 is a schematic diagram of the structure of a pixel circuit 10 provided in an embodiment of the present application. Figure 4 As shown, the pixel circuit 10 may include: a first metal layer 101, a first insulating layer 102, at least one transparent conductive line L1 ( Figure 4 The transparent conductive line L1 is connected to a metal layer in the pixel circuit 10, forming a signal line for connection to a signal terminal. Thus, the pixel circuit 10 can transmit a driving signal to the connected target electrode 20 under the control of the signal provided by each signal terminal. Furthermore, the target electrode 20 is generally disposed on a side of the second metal layer 104 away from the second insulating layer 103, with an insulating layer disposed between the target electrode 20 and the second metal layer 104.

[0073] It should be noted that Figures 1 to 3Only pixel P1 within the second display area A2 is shown. To ensure proper operation of the display substrate, the first display area A1 also includes multiple pixels. Furthermore, the first metal layer 101, first insulating layer 102, second insulating layer 103, and second metal layer 104 are essential layers of the pixel circuitry within any pixel within the display area. Specifically, the first insulating layer 102 and the second insulating layer 103 are two existing insulating layers between the first metal layer 101 and the second metal layer 104. The transparent conductive line L1 is a newly added layer to ensure light transmittance in the second display area A2.

[0074] In order to avoid signal interference between two adjacent conductive layers, at least one insulating layer is generally required between the two adjacent conductive layers. Therefore, in combination with the setting position of the target electrode 20 and the second metal layer 104, if the transparent conductive line L1 is set on the side of the second metal layer 104 away from the base substrate 00, it is necessary to set an additional insulating layer to separate the target electrode from the transparent conductive line L1, or to separate the second metal layer 104 from the transparent conductive line L1. In the embodiment of the present application, since the transparent conductive line L1 is set between the two existing insulating layers, at least one insulating layer can be saved. And since each layer is generally made using a mask process, at least one MASK process can be saved. It can be determined from this that the display substrate provided by the embodiment of the present application has a simple structure and a low manufacturing cost.

[0075] In summary, the embodiments of the present application disclose a display substrate comprising a base substrate having a first display area and a second display area. In the pixel circuits included in the pixels within the second display area, the conductive lines connected to the metal layer are transparent conductive lines, and these transparent conductive lines are located between two existing insulating layers. As a result, compared to display substrates with transparent conductive lines located elsewhere, the display substrate provided by the embodiments of the present application not only ensures better light transmittance in the second display area, but also has a simpler structure and lower manufacturing costs.

[0076] Optionally, the target electrode 20 described in the embodiment of the present application can be an anode. Accordingly, the other electrode described in the above embodiment can be a cathode. Of course, the target electrode 20 can also be a cathode, and accordingly, the other electrode described in the above embodiment can be an anode.

[0077] Optionally, the material of each transparent conductive line L1 described in the embodiments of the present application can be indium tin oxide (ITO). In this case, each transparent conductive line L1 can also be referred to as an ITO trace. In some embodiments, the material of the transparent conductive line L1 can also be other transparent and conductive materials such as indium gallium zinc oxide (IGZO). The following embodiments of the present application are all described using the transparent conductive line L1 as an ITO trace.

[0078] Figure 5 This is a schematic diagram of another pixel circuit provided by an embodiment of the present application. Figure 4 and Figure 5 It can be seen that the first metal layer 101 described in the embodiment of the present application can be a first source and drain (SD) metal layer, referred to as SD1. The second metal layer 104 can be a second source and drain metal layer SD2. The first insulating layer 102 can be a passivation layer (PVX). The second insulating layer 103 can be a first planarization layer (PLN), referred to as PLN1. In other words, the at least one transparent conductive line L1 described in the embodiment of the present application can be located between the passivation layer PVX and the first planarization layer PLN1.

[0079] Since each layer structure is generally formed in sequence in a direction away from the base substrate 00 during the process, it can be determined that at least one transparent conductive line L1 described in the embodiment of the present application is formed on the side of the passivation layer PVX away from the first source / drain metal layer SD1 after the first source / drain metal layer SD1 and the passivation layer PVX are formed, and before the first flat layer PLN1 is formed. That is, the transparent conductive line L1 manufacturing process can be performed after the passivation layer PVX is formed and before the first flat layer PLN1 is formed. In addition, in combination with Figure 5 , an ITO layer may be formed first, and then one or more ITO traces may be obtained through a patterning process.

[0080] Optional, Figure 6 This is a structural diagram of another pixel circuit provided by an embodiment of the present application. Figure 6 As shown, the pixel circuit 10 may further include: a third insulating layer 105 located on the side of the second metal layer 104 away from the base substrate 00, and a transistor pattern layer 106, a third metal layer 107, a fourth metal layer 108 and a fourth insulating layer 109 located between the base substrate 00 and the first metal layer 101 and stacked in sequence in a direction away from the base substrate 00.

[0081] Optional, continue to refer to Figure 6The transistor pattern layer 106 may be a polysilicon (poly) material layer, referred to as a POLY layer. The third insulating layer 105 may be a second planar layer PLN2. The third metal layer 107 may be a first gate metal layer, referred to as GATE1. The fourth metal layer 108 may be a second gate metal layer GATE2, and the fourth insulating layer 109 may be an interlayer dielectric (ILD). Furthermore, an insulating layer is generally included between the first gate metal layer GATE1 and the second gate metal layer GATE2.

[0082] Optional, continue to refer to Figure 6 Since the transistor pattern layer 106, the third metal layer 107 and the fourth metal layer 108 are all conductive materials, in order to avoid mutual interference of signals between two adjacent conductive layers, the pixel circuit 10 may further include: an insulating layer 110 located between the transistor pattern layer 106 and the third metal layer 107 (i.e., the first gate metal layer GATE1), and an insulating layer 111 located between the third metal layer 107 and the fourth metal layer 108 (i.e., the second gate metal layer GATE2).

[0083] Optional, Figure 7 This is a schematic diagram of the structure of another display substrate provided in an embodiment of the present application. Figure 7 As shown, the first gate metal layer GATE1 may include a first portion B1, a second portion B2, and a third portion B3. The at least one transparent conductive line L1 may include a first transparent conductive line L11, a second transparent conductive line L12, a third transparent conductive line L13, a fourth transparent conductive line L14, a fifth transparent conductive line L15, and a sixth transparent conductive line L16.

[0084] The first transparent conductive line L11 can be connected to the first metal layer 101 (ie, the first source-drain metal layer SD1), and is configured to transmit a power signal. Figure 7 As shown, the first transparent conductive line L11 can also be used to connect to the power supply terminal VDD. The power supply terminal VDD can transmit a power signal to the first source-drain metal layer SD1 through the first transparent conductive line L11. In other words, the first transparent conductive line L11 and the first source-drain metal layer SD1 can be connected to form a power signal line, and the pixel circuit 10 can receive the power signal from the power signal line.

[0085] Optional, combined Figure 8 As can be seen from another display substrate, the first transparent conductive line L11 in two adjacent pixel circuits 10 in the same column can be an integrated structure. In other words, the pixel circuits 10 in the same column can share the same power signal line, that is, connected to the same DC power supply terminal VDD.

[0086] The second transparent conductive line L12 can be connected to the second metal layer 104 (ie, the second source-drain metal layer SD2) and is configured to transmit data signals. Figure 7 As shown, the second transparent conductive line L12 can also be used to connect to the data signal terminal DATA. The data signal terminal DATA can transmit a data signal to the second source-drain metal layer SD2 via the second transparent conductive line L12. In other words, the second transparent conductive line L12 and the second source-drain metal layer SD2 can be connected to form a data signal line, and the pixel circuit 10 can receive a data signal from the data signal line.

[0087] Optional, still combined Figure 8 It can be seen that the second transparent conductive lines L12 in two adjacent pixel circuits 10 in the same column can be an integrated structure. In other words, the pixel circuits 10 in the same column can share the same data signal line, that is, connected to the same data signal terminal DATA.

[0088] The third transparent conductive line L13 may be connected to the first portion B1 of the first gate metal layer GATE1 and configured to transmit a light emitting control signal. Figure 7 As shown, the third transparent conductive line L13 can also be used to connect to the light-emitting control signal terminal EM. The light-emitting control signal terminal EM can transmit the light-emitting control signal to the first gate metal layer GATE1 through the third transparent conductive line L13. In other words, the third transparent conductive line L13 is connected to the first portion B1 of the first gate metal layer GATE1 to form a light-emitting control signal line, and the pixel circuit 10 can receive the light-emitting control signal from the light-emitting control signal line.

[0089] Optional, combined Figure 8 As can be seen from another display substrate, the third transparent conductive line L13 in two adjacent pixel circuits 10 in the same row can be an integrated structure. In other words, the pixel circuits 10 in the same row can share the same light-emitting control signal line, that is, connected to the same light-emitting control signal terminal EM.

[0090] The fourth transparent conductive line L14 may be connected to the second portion B2 of the first gate metal layer GATE1 and configured to transmit a gate driving signal. Figure 7 As shown, the fourth transparent conductive line L14 can also be used to connect to the gate signal terminal G1. The gate signal terminal G1 can transmit a gate drive signal to the first gate metal layer GATE1 through the fourth transparent conductive line L14. In other words, the fourth transparent conductive line L14 is connected to the second portion B2 of the first gate metal layer GATE1 to form a gate line, and the pixel circuit 10 can receive the gate drive signal from the gate line.

[0091] Optional, combined Figure 8As can be seen from another display substrate, the fourth transparent conductive line L14 in two adjacent pixel circuits 10 in the same row can be an integrated structure. In other words, the pixel circuits 10 in the same row can share the same gate line, ie, connected to the same gate signal terminal G1.

[0092] The fifth transparent conductive line L15 may be connected to the third portion B3 of the first gate metal layer GATE1 and configured to transmit a reset signal. Figure 7 As shown, the fifth transparent conductive line L15 can also be used to connect to the reset signal terminal RST. The reset signal terminal RST can transmit a reset signal to the first gate metal layer GATE1 through the fifth transparent conductive line L15. In other words, the fifth transparent conductive line L15 is connected to the third portion B3 of the first gate metal layer GATE1 to form a reset signal line, and the pixel circuit 10 can receive the reset signal from the reset signal line.

[0093] Optional, combined Figure 8 As can be seen from another display substrate, the fifth transparent conductive line L15 in two adjacent pixel circuits 10 in the same row can be an integrated structure. In other words, the pixel circuits 10 in the same row can share the same reset signal line, that is, connected to the same reset signal terminal RST.

[0094] The sixth transparent conductive line L16 may be connected to the fourth metal layer 108 (ie, the second gate metal layer GATE2), and is configured to transmit an initial signal. Figure 7 As shown, the sixth transparent conductive line L16 can also be used to connect to the initial signal terminal Vinit. The initial signal terminal Vinit can transmit an initial signal to the second gate metal layer GATE2 via the sixth transparent conductive line L16. In other words, the sixth transparent conductive line L16 and the second gate metal layer GATE2 can be connected to form an initial signal line, and the pixel circuit 10 can receive the initial signal from the initial signal line.

[0095] Optional, combined Figure 8 As can be seen from another display substrate, the sixth transparent conductive line L16 in two adjacent pixel circuits 10 in the same row can be an integrated structure. In other words, the pixel circuits 10 in the same row can share the same initial signal line, that is, connected to the same initial signal terminal Vinit. In some embodiments, the pixel circuits 10 included in all pixels P1 in the second display area A2 can be connected to the same initial signal terminal Vinit.

[0096] It should be noted that, combined with Figure 7 and Figure 8The pixel circuit 10 may actually include multiple transistors. The pixel circuit 10 receiving signals in the above embodiments refers to the transistor receiving the signal. Driven by the above signal, the pixel circuit 10 can work reliably and transmit the driving signal to the connected target electrode 20.

[0097] It should also be noted that, combined with Figure 8 In order to further ensure the transmittance of the second display area A2, the rows and columns in the second display area A2 are not strictly aligned side by side. In addition, since a pixel circuit 10 may be adjacent to another pixel circuit 10 on the top, bottom, left, and right sides, the combination Figure 7 and Figure 8 It can be seen that each type of transparent conductive line can be divided into two parts, one part is integrally formed with the corresponding type of transparent conductive line of an adjacent pixel circuit 10, and the other part is integrally formed with the corresponding type of transparent conductive line of another adjacent pixel circuit 10.

[0098] For example, taking the first transparent conductive line L11 as an example, refer to Figure 7 and Figure 8 As can be seen, the first transparent conductive line L11 of the pixel circuit 10 located at the center can include an upper portion L11_1 and a lower portion L11_2. The upper portion L11_1 is integrally formed with the lower portion L11_2 of the first transparent conductive line L11 of the adjacent pixel circuit 10 above it, while the lower portion L11_2 is integrally formed with the upper portion L11_1 of the first transparent conductive line L11 of the adjacent pixel circuit 10 below it.

[0099] Optionally, in the embodiment of the present application, each transparent conductive line L1 may be connected to a metal layer in the pixel circuit 10 through a via.

[0100] For example, taking the transparent conductive line L1 connected to the first source-drain metal layer SD1 and the second source-drain metal layer SD2 as an example, Figure 9 The structure layout including the via K1 is shown. Figure 9 It can be seen that both the passivation layer PVX and the first flat layer PLN1 include vias K1, and the transparent conductive line L1 and the first source and drain metal layer SD1 can be connected through the vias K1 opened in the passivation layer PVX; the transparent conductive line L1 and the second source and drain metal layer SD2 can be connected through the vias K1 opened in the first flat layer PLN1.

[0101] For another example, taking the transparent conductive line L1 connected to the first gate metal layer GATE1 as an example, Figure 10 The structure layout including the via K1 is shown. Figure 10As can be seen, a via K1 is provided in the passivation layer PVX, the first source / drain metal layer SD1, the interlayer dielectric layer ILD, and the second gate metal layer GATE2 between the transparent conductive line L1 and the first gate metal layer GATE1. This via K1 penetrates the passivation layer PVX, the first source / drain metal layer SD1, the interlayer dielectric layer ILD, and the second gate metal layer GATE2. The transparent conductive line L1 and the first gate metal layer GATE1 can be connected via this via K1.

[0102] For another example, taking the connection between the transparent conductive line L1 and the second gate metal layer GATE2 as an example, Figure 11 The structure layout including the via K1 is shown. Figure 11 As can be seen, a via K1 is provided in the passivation layer PVX, the first source / drain metal layer SD1, and the interlayer dielectric layer ILD between the transparent conductive line L1 and the second gate metal layer GATE2. This via K1 penetrates the passivation layer PVX, the first source / drain metal layer SD1, and the interlayer dielectric layer ILD. The transparent conductive line L1 and the second gate metal layer GATE2 can be connected via this via K1.

[0103] Combined with the above embodiment records, it can be seen that since the transparent conductive line L1 recorded in the embodiment of the present application is located between the passivation layer PVX and the first flat layer PLN1, the depth of each via K1 opened above is relatively shallow, which is easy to form a good contact and ensure connection reliability.

[0104] Optional, combined Figure 2 The pixel circuit 10 may be located in the second display area A2, that is, the pixel circuit 10 may be built-in. In this way, the orthographic projection of the pixel circuit 10 on the base substrate 00 and the orthographic projection of the target electrode 20 on the base substrate 00 may at least partially overlap. Accordingly, the pixel circuit 10 and the target electrode 20 may be connected through a via.

[0105] For example, Figure 7 In the display substrate shown, the orthographic projection of the pixel circuit 10 on the base substrate 00 covers the orthographic projection of the target electrode 20 on the base substrate 00 .

[0106] Optional, combined Figure 3 , the pixel circuit 10 can be located in the first display area A1. In this way, the pixel circuit 10 can be connected to the target electrode 20 via the transparent conductive line L1. For example, the second source / drain metal layer SD2 can be connected to the transparent conductive line L1 via a via, and the transparent conductive line L1 can be connected to the target electrode 20. This ensures a reliable connection between the second source / drain metal layer SD2 and the target electrode 20.

[0107] Optionally, in the embodiment of the present application, since the base substrate 00 has a light-transmissive display area, namely the second display area A2, Figure 12 As shown, the light sensor 001 (e.g., camera) in the display module included in the display device can be directly set in the second display area A2, that is, no additional hole is needed on the display panel. This lays a solid foundation for the realization of full-screen display panels.

[0108] Optionally, the second display area A2 may be rectangular, and the area of ​​the positive projection of the light sensor 001 on the substrate 00 may be smaller than or equal to the area of ​​the inscribed circle of the second display area A2. That is, the size of the area where the light sensor 001 is located may be smaller than or equal to the size of the inscribed circle of the second display area A2. For example, Figure 12 In the display panel shown, the size of the area where the light sensor 001 is located is equal to the size of the inscribed circle Y0 of the second display area A2. That is, the shape of the area where the light sensor 001 is located can be circular. Accordingly, the area where the light sensor 001 is located can also be called a light-transmitting hole. Of course, in some embodiments, the second display area A2 can also have other shapes besides rectangles, such as circles or ellipses.

[0109] Optionally, the resolution of the first display area A1 can be greater than that of the second display area A2. That is, the area of ​​the first display area A1 is larger than that of the second display area A2, and the number of pixels included in the first display area A1 is greater than that of the second display area A2. Furthermore, the density of the multiple pixels P1 located in the second display area A2 can be different from that of the multiple pixels located in the first display area A1. That is, the number of pixels per inch in the first display area A1 and the second display area A2 is different.

[0110] In some embodiments, the resolution of the first display area A1 can be less than or equal to the resolution of the second display area A2. For example, the area of ​​the first display area A1 can be the same as the area of ​​the second display area A2, and the number of pixels per unit area of ​​the first display area A1 and the number of pixels per unit area of ​​the second display area A2 can be the same. Alternatively, the area of ​​the first display area A1 can be smaller than the area of ​​the second display area A2, and the number of pixels per unit area of ​​the first display area A1 is smaller than the number of pixels per unit area of ​​the second display area A2.

[0111] In summary, the embodiments of the present application disclose a display substrate comprising a base substrate having a first display area and a second display area. In the pixel circuits included in the pixels within the second display area, the conductive lines connected to the metal layer are transparent conductive lines, and these transparent conductive lines are located between two existing insulating layers. As a result, compared to display substrates with transparent conductive lines located elsewhere, the display substrate provided by the embodiments of the present application not only ensures better light transmittance in the second display area, but also has a simpler structure and lower manufacturing costs.

[0112] Figure 13 This is a flow chart of a method for manufacturing a display substrate provided in an embodiment of the present application. The method can be used to manufacture Figures 1 to 3 、 Figure 7 、 Figure 8 and Figure 12 Any of the display substrates shown. Figure 13 As shown, the method may include:

[0113] Step 1301: Provide a substrate.

[0114] Among them, combined with the above Figure 1 The base substrate may have a first display area A1 and a second display area A2, and the first display area A1 may at least partially surround the second display area A2.

[0115] Step 1302: Form a plurality of pixels on one side of the base substrate.

[0116] Among them, combined Figure 2 and Figure 3 , each pixel P1 may include a pixel circuit 10 and a target electrode 20 connected to each other. The pixel circuit 10 may be located in the first display area A1 or the second display area A2, and the target electrode 20 may be located in the second display area A2. Figure 4 The pixel circuit 10 may include a first metal layer 101, a first insulating layer 102, at least one transparent conductive line L2, a second insulating layer 103 and a second metal layer 104 stacked in sequence in a direction away from the base substrate 00, and each transparent conductive line L1 can be connected to a metal layer in the pixel circuit 10.

[0117] Optional, with Figure 6 and Figure 7 In the pixel circuit 10 shown, the target electrode is the anode, and the pixel circuit is built as an example. Figure 14 FIG1 shows a flow chart of another method for manufacturing a display substrate provided by an embodiment of the present application. Figure 14 As shown, the method may include:

[0118] Step 1401: Provide a substrate.

[0119] Optionally, a base substrate may be provided as a carrier, and the base substrate may have at least a first display area and a second display area at least partially surrounded by the first display area. The base substrate may be a glass substrate or a flexible substrate.

[0120] Step 1402: forming a transistor pattern layer on one side of the base substrate.

[0121] Optionally, after obtaining the base substrate, a transistor pattern layer may be formed on one side of the base substrate by a patterning process. Optionally, the patterning process may include: coating, exposure, development, and etching.

[0122] For example, Figure 15 FIG. 1 shows a schematic structural diagram of a base substrate 00 on which a transistor pattern layer, ie, a POLY layer, is formed.

[0123] Step 1403 : forming a first gate metal layer on a side of the transistor pattern layer away from the base substrate.

[0124] Optionally, after forming the transistor pattern layer, a first gate metal layer may be formed on a side of the transistor pattern layer away from the base substrate.

[0125] For example, Figure 16 FIG. 1 shows a schematic structural diagram of a substrate 00 on which a first gate metal layer GATE1 is formed.

[0126] Step 1404 : forming a second gate metal layer on a side of the first gate metal layer away from the transistor pattern layer.

[0127] Optionally, after forming the first gate metal layer, a second gate metal layer may be further formed on a side of the first gate metal layer away from the transistor pattern layer.

[0128] For example, Figure 17 FIG. 1 shows a structural schematic diagram of a substrate 00 on which a second gate metal layer GATE2 is formed.

[0129] Step 1405 : forming an interlayer dielectric layer on a side of the second gate metal layer away from the first gate metal layer.

[0130] Optionally, after forming the second gate metal layer, an interlayer dielectric layer may be further formed on a side of the second gate metal layer away from the first gate metal layer. Furthermore, after forming the interlayer dielectric layer, the interlayer dielectric layer may be processed to form a plurality of connecting vias.

[0131] For example, Figure 18 A structural schematic diagram of a substrate 00 is shown with a via K1 formed on the second gate metal layer GATE2.

[0132] Step 1406: Form a first source and drain metal layer on a side of the interlayer dielectric away from the second gate metal layer.

[0133] Optionally, after the interlayer dielectric layer is formed, a first source and drain metal layer may be further formed on a side of the interlayer dielectric layer away from the second gate metal layer.

[0134] For example, Figure 19 A schematic structural diagram of a base substrate 00 is shown with a first source-drain metal layer SD1 formed on a via hole K1.

[0135] Step 1407: forming a passivation layer on a side of the first source / drain metal layer away from the interlayer dielectric layer.

[0136] Optionally, after forming the first source / drain metal layer, a passivation layer may be further formed on a side of the first source / drain metal layer away from the interlayer dielectric layer. After forming the passivation layer, the passivation layer may be processed to obtain a plurality of connecting vias.

[0137] For example, Figure 20 A schematic structural diagram of a base substrate 00 is shown with a via K1 formed on the first source / drain metal layer SD1 .

[0138] Step 1408 : forming at least one transparent conductive line on a side of the passivation layer away from the first source / drain metal layer.

[0139] Optionally, after forming the passivation layer, a transparent conductive layer may be further formed on a side of the passivation layer away from the first source and drain metal layer, and then the transparent conductive layer may be processed to obtain one or more transparent conductive lines.

[0140] For example, Figure 21 A schematic structural diagram of a base substrate 00 is shown, showing a plurality of first transparent conductive lines L1 formed on a via hole K1.

[0141] Step 1409 : forming a first planarization layer on a side of at least one transparent conductive line away from the passivation layer.

[0142] Optionally, after forming at least one transparent conductive line, a first flat layer may be formed on a side of the at least one transparent conductive line away from the passivation layer. Furthermore, after forming the first flat layer, the first flat layer may be processed to obtain a plurality of connecting vias.

[0143] For example, Figure 22 A schematic structural diagram of a base substrate 00 is shown with a via hole K1 formed on at least one transparent conductive line L1.

[0144] Step 14010: forming a second source-drain metal layer on a side of the first planar layer away from at least one transparent conductive line.

[0145] Optionally, after forming the first planarization layer, a second source-drain metal layer may be further formed on a side of the first planarization layer away from the at least one transparent conductive line.

[0146] For example, Figure 23 A schematic structural diagram of a base substrate 00 is shown with a second source-drain metal layer SD2 formed on the via hole K1.

[0147] Step 14011: Form a second source / drain metal layer on a side of the second planar layer away from the first planar layer.

[0148] Optionally, after forming the second source and drain metal layer, a second planar layer may be further formed on a side of the second source and drain metal layer away from the first planar layer. Furthermore, after forming the second planar layer, the second planar layer may be processed to obtain a plurality of connecting vias.

[0149] For example, Figure 24 A schematic structural diagram of a base substrate 00 is shown with a via K1 formed on the second source / drain metal layer SD2 .

[0150] Step 14012: Form an anode on a side of the second planar layer away from the second source / drain metal layer.

[0151] Optionally, after forming the second planar layer, an anode may be further formed on a side of the second planar layer away from the second source / drain metal layer.

[0152] For example, Figure 25 The schematic structural diagram of the substrate 00 shows an anode ANODE formed on the via K1. The anode ANODE can be connected to the second source-drain metal layer SD2 through the via K1.

[0153] That is, based on Figures 14 to 25 It can be determined that the process sequence for manufacturing the display substrate in the embodiment of the present application is: POLY-GATE1-GATE2-ILD-SD1-PVX-ITO-PLN1-SD2-PLN2-ANODE.

[0154] It should be noted that for each hierarchical structure, Figures 15 to 25 Only one label is marked in each, and the same filling color belongs to the same level.

[0155] It should also be noted that, combined with Figure 6Because an insulating layer is included between the transistor pattern layer 106 and the first gate metal layer GATE1, and between the first gate metal layer GATE1 and the second gate metal layer GATE2, before executing step 1403, a step of forming an insulating layer on a side of the transistor pattern layer away from the substrate may be further included. Furthermore, before executing step 1404, a step of forming an insulating layer on a side of the first gate metal layer away from the transistor pattern layer may be further included.

[0156] In summary, the embodiments of the present application disclose a method for manufacturing a display substrate. In this method, transparent conductive lines are formed after forming the passivation layer and before forming the first planar layer. Because the passivation layer and the first planar layer are two existing insulating layers, compared to forming the transparent conductive lines at other locations, the method provided by the embodiments of the present application not only ensures better light transmittance in the second display area, but also results in a simpler display substrate structure and lower manufacturing costs.

[0157] Optional, Figure 26 Schematic diagram of a display device provided in an embodiment of the present application. Figure 26 As shown, the display device may include: an integrated circuit 100, and Figures 1 to 3 、 Figure 7 、 Figure 8 and Figure 12 Any of the display substrates 200 shown.

[0158] As can be seen from the above drawings, the integrated circuit 100 can be electrically connected to the transparent conductive line L1 included in the pixel circuit 10 in the display substrate 200 , and the integrated circuit 100 can be used to provide signals to the transparent conductive line L1 .

[0159] Example, combined Figure 7 The integrated circuit 100 can be electrically connected to the signal terminals connected to each transparent conductive line L1 and provide signals to the signal terminals, thereby indirectly providing signals to the transparent conductive line L1.

[0160] It should be noted that Figure 26 The position of the integrated circuit 100 is only schematically shown. The integrated circuit 100 may be located on the right side of the display substrate 200, or on both the left and right sides of the display substrate 200. Alternatively, it may be located on the upper side and / or the lower side of the display substrate 200.

[0161] Optionally, the display device can be: an organic light-emitting diode (AMOLED) display device, a liquid crystal display device, a mobile phone, a computer, a television, a monitor, an electronic paper, a digital photo frame or a navigator, or any other product or component with a display function.

[0162] It should be understood that the term "and / or" used herein indicates that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0163] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display substrate, wherein: The display substrate comprises: A base substrate having a first display area and a second display area, wherein the first display area at least partially surrounds the second display area, and a light sensor is disposed in the second display area; A plurality of pixels, each of the pixels comprising an interconnected pixel circuit and a target electrode, the pixel circuit being located in the second display area, the target electrode being located in the second display area, the orthographic projection of the pixel circuit on the base substrate at least partially overlapping with the orthographic projection of the target electrode on the base substrate; the pixel circuit comprising: a first metal layer, a first insulating layer, at least one transparent conductive line, a second insulating layer, and a second metal layer being stacked in sequence and located on one side of the base substrate, each transparent conductive line being connected to a metal layer in the pixel circuit; and two adjacent pixel circuits being electrically connected via the transparent conductive line.

2. The display substrate according to claim 1, wherein The first metal layer is a first source-drain metal layer, the second metal layer is a second source-drain metal layer, the first insulating layer is a passivation layer, and the second insulating layer is a first planarization layer.

3. The display substrate according to claim 1, wherein The material of each transparent conductive line is indium tin oxide.

4. The display substrate according to claim 1, wherein: The target electrode is an anode.

5. The display substrate according to any one of claims 1 to 4, wherein: The at least one transparent conductive line includes: a first transparent conductive line; The first transparent conductive line is connected to the first metal layer and is configured to transmit a power signal. The first transparent conductive lines in two adjacent pixel circuits located in the same column form an integrated structure.

6. The display substrate according to any one of claims 1 to 4, wherein: The at least one transparent conductive line includes: a second transparent conductive line; The second transparent conductive line is connected to the second metal layer and is configured to transmit a data signal. The second transparent conductive lines in two adjacent pixel circuits located in the same column form an integrated structure.

7. The display substrate according to any one of claims 1 to 4, wherein: The pixel circuit also includes: a third insulating layer located on the side of the second metal layer away from the base substrate, and a transistor pattern layer, a third metal layer, a fourth metal layer and a fourth insulating layer located between the base substrate and the first metal layer and stacked in sequence in a direction away from the base substrate.

8. The display substrate according to claim 7, wherein: The third insulating layer is a second planar layer, the third metal layer is a first gate metal layer, the fourth metal layer is a second gate metal layer, and the fourth insulating layer is an interlayer dielectric layer.

9. The display substrate according to claim 8, wherein: The third metal layer includes a first portion, a second portion and a third portion; The at least one transparent conductive line includes: a third transparent conductive line, a fourth transparent conductive line and a fifth transparent conductive line; The third transparent conductive line is connected to the first portion and is configured to transmit a light emitting control signal, wherein the third transparent conductive lines in two adjacent pixel circuits located in the same row form an integrated structure; The fourth transparent conductive line is connected to the second portion and is configured to transmit a gate drive signal, wherein the fourth transparent conductive lines in two adjacent pixel circuits located in the same row form an integrated structure; The fifth transparent conductive line is connected to the third portion and is configured to transmit a reset signal. The fifth transparent conductive lines in two adjacent pixel circuits located in the same row are an integrated structure.

10. The display substrate according to claim 9, wherein: The at least one transparent conductive line includes: a sixth transparent conductive line; The sixth transparent conductive line is connected to the fourth metal layer and is configured to transmit an initial signal. The sixth transparent conductive lines in two adjacent pixel circuits located in the same row are an integrated structure.

11. The display substrate according to any one of claims 1 to 4 and 8 to 10, wherein: The second display area is a light-transmitting display area.

12. The display substrate according to any one of claims 1 to 4 and 8 to 10, wherein: The resolution of the first display area is greater than or equal to the resolution of the second display area.

13. The display substrate according to any one of claims 1 to 4 and 8 to 10, wherein: Each of the transparent conductive lines is connected to a metal layer in the pixel circuit through a via.

14. The display substrate according to claim 9, wherein: The first metal layer is a first source-drain metal layer, the second metal layer is a second source-drain metal layer, the first insulating layer is a passivation layer, and the second insulating layer is a first planarization layer; The material of each transparent conductive line is indium tin oxide; The target electrode is an anode; The at least one transparent conductive line includes: a first transparent conductive line, a second transparent conductive line and a sixth transparent conductive line; the first transparent conductive line is connected to the first metal layer and is configured to transmit a power signal, and the first transparent conductive line in the two adjacent pixel circuits located in the same column is an integrated structure; the second transparent conductive line is connected to the second metal layer and is configured to transmit a data signal, and the second transparent conductive line in the two adjacent pixel circuits located in the same column is an integrated structure; the sixth transparent conductive line is connected to the fourth metal layer and is configured to transmit an initial signal, and the sixth transparent conductive line in the two adjacent pixel circuits located in the same row is an integrated structure; the second display area is a light-transmitting display area; the resolution of the first display area is greater than or equal to the resolution of the second display area; each of the transparent conductive lines is connected to a metal layer in the pixel circuit through a via.

15. A method for manufacturing a display substrate, wherein: The method comprises: Providing a base substrate, the base substrate having a first display area and a second display area, wherein the first display area at least partially surrounds the second display area, and a light sensor is disposed in the second display area; forming a plurality of pixels on one side of the substrate, each of the pixels comprising a pixel circuit and a target electrode connected to each other; In which, the pixel circuit is located in the second display area, the target electrode is located in the second display area, and the orthographic projection of the pixel circuit on the base substrate at least partially overlaps with the orthographic projection of the target electrode on the base substrate; the pixel circuit includes a first metal layer, a first insulating layer, at least one transparent conductive line, a second insulating layer and a second metal layer stacked in sequence in a direction away from the base substrate, each of the transparent conductive lines is connected to a metal layer in the pixel circuit; two adjacent pixel circuits are electrically connected through the transparent conductive line.

16. A display device, wherein: The display device comprises: an integrated circuit, and a display substrate according to any one of claims 1 to 14; The integrated circuit is electrically connected to a transparent conductive line included in a pixel circuit in the display substrate, and the integrated circuit is used to provide a signal to the transparent conductive line.

17. The display device according to claim 16, wherein: The display device further includes the light sensor, and the light sensor is located in the second display area of ​​the display substrate.

18. The display device according to claim 17, wherein: The second display area is rectangular, and the orthographic projection area of ​​the photosensor on the base substrate is smaller than or equal to the area of ​​the inscribed circle of the second display area.

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