Eye diagram generation system and method for high-resolution oscilloscope

Abstract

The present invention discloses an eye diagram generation system and method for a high-resolution oscilloscope, the system comprising the following components: a data sampling module, a bit rate calculation module, a real number multiple interpolation module, a software phase-locked loop clock recovery and data resampling module, a phase-locked loop lock judgment module, a resampled waveform data superposition module, a waveform data statistics and frequency calculation module, and a fluorescent image generation module. The method of the present invention performs clock recovery based on a software phase-locked loop, and realizes accurate cutting and superposition of eye diagrams based on the recovered clock, and then performs frequency calculation and eye diagram fluorescent image generation. The method has the advantages of high eye diagram generation efficiency, zero trigger jitter, zero jitter of clock recovery, offline analysis, and the ability to achieve tracking and positioning.

Description

Technical Field

[0001] The present invention relates to the technical field of oscilloscopes, and in particular to an eye diagram generation system and method for a high-resolution oscilloscope. Background Art

[0002] With the advancement of technology, the effective number of bits (i.e. resolution) of oscilloscopes is getting higher and higher. For high-resolution oscilloscopes, embedded clock recovery, eye diagram analysis, and jitter analysis of serial bus signals can be fully realized, which is also an indispensable function of high-end oscilloscopes. It can provide users with means of serial bus signal eye diagram and jitter analysis, without the need to purchase special instruments, and an oscilloscope can handle it.

[0003] The eye diagram is the result of accumulating and superimposing the bits of the acquired serial signal in an afterglow manner. The superimposed figure looks like an eye, hence the name eye diagram. With the continuous increase in serial data rates, eye diagram testing is an essential test item and has become the most commonly used method to measure the quality of high-speed signals.

[0004] Eye diagram generation methods are generally divided into traditional eye diagram generation methods (TEP) and real-time eye diagram generation methods (RTE). The traditional eye diagram generation method uses the trigger function and fluorescent function of the oscilloscope to continuously synchronize the trigger and superimpose the display. This method not only introduces the trigger jitter of the oscilloscope, but also has low efficiency. It takes 1 million triggers to measure 1 million UI. With the advancement of technology, traditional eye diagram generation methods are generally no longer used. The real-time eye diagram generation method is currently mainly based on the eye diagram and jitter analysis of the hardware clock recovery method.

[0005] The hardware-based clock and data recovery (CDR) circuit requires an external clock signal. These additional electronic devices increase the noise or jitter of the system, which in turn reduces the accuracy of the eye diagram analysis. The synchronous cutting of the eye diagram based on hardware clock recovery will also introduce jitter. For high-speed serial signals, this jitter is already too large to be ignored. Moreover, the hardware clock and data recovery (CDR) circuit can only detect continuous serial signals to work properly. If the measured signal is not continuous, for example, there is a low level between two consecutive bits, the hardware CDR cannot recover the correct clock. Therefore, the eye diagram analysis based on hardware clock and data recovery (CDR) still has the problem of large intermittent. Finally, the eye diagram analysis based on hardware clock and data recovery (CDR) is based on physical layer signals, and cannot analyze the historical data sampled by the oscilloscope, which has application limitations. Summary of the invention

[0006] To solve the above technical problems, the present invention provides an eye diagram generation system and method for a high-resolution oscilloscope, which performs clock recovery based on a software phase-locked loop, and realizes accurate cutting and superposition of the eye diagram based on the recovered clock, and then performs frequency calculation and eye diagram fluorescent image generation. The method has the advantages of high eye diagram generation efficiency, zero trigger jitter, zero jitter of clock recovery, offline analysis and tracking and positioning.

[0007] To achieve the above object, the technical solution of the present invention is as follows:

[0008] An eye diagram generation system for a high-resolution oscilloscope includes the following components:

[0009] Data sampling module: used to realize the acquisition, analog-to-digital conversion and storage of serial bus signals of high-resolution oscilloscope;

[0010] Bit rate calculation module: used to calculate the bit rate of the serial bus signal;

[0011] Real-number multiple interpolation module: used to perform real-number multiple interpolation on the collected serial bus signal to obtain real-number multiple variable sampling data;

[0012] Software phase-locked loop clock recovery and data resampling module: used to perform software phase-locked loop clock recovery and data resampling on real-number multiple sampling data to obtain resampled waveform data;

[0013] Phase-locked loop lock judgment module: used to judge whether the phase-locked loop is in a locked state;

[0014] Resampled waveform data superposition module: When the phase-locked loop is locked, the resampled waveform data superposition module is used to superimpose the resampled waveform data according to the set number of eye diagram UIs;

[0015] Waveform data statistics and frequency calculation module: used to calculate the maximum frequency value and waveform gray value of the waveform based on the superimposed waveform data;

[0016] Fluorescence image generation module: used to calculate the pixel color value according to the calculated gray value and generate a fluorescence image.

[0017] In the above solution, the software phase-locked loop clock recovery and data resampling module includes an interpolation module, a phase detector, a loop filter and an interpolation control module.

[0018] In the above scheme, the phase detector adopts a multi-sampling bang-bang phase detector, the interpolator of the interpolation module adopts a polynomial interpolation filter with a Farrow structure, the loop filter adopts a low-pass filter, and the interpolation control module adopts a Mod-1 counting interpolation controller.

[0019] A method for generating an eye diagram for a high-resolution oscilloscope, using an eye diagram generation system for a high-resolution oscilloscope as described above, includes the following steps:

[0020] Step 1: The data sampling module collects the serial bus signal of the high-resolution oscilloscope through a high-resolution ADC, performs analog-to-digital conversion, and stores it in the memory module;

[0021] Step 2: The bit rate calculation module calculates the bit rate of the serial bus signal;

[0022] Step 3: The real-number multiple interpolation module performs real-number multiple interpolation on the collected serial bus signal to obtain real-number multiple variable sampling data;

[0023] Step 4: The software phase-locked loop clock recovery and data resampling module performs software phase-locked loop clock recovery and data resampling on the real-number multiple variable sampling data to obtain resampled waveform data;

[0024] Step 5: The phase-locked loop locking judgment module judges the state of the phase-locked loop. When the phase-locked loop is in the locked state, go to Step 6. When the phase-locked loop is in the unlocked state, return to Step 4;

[0025] Step 6: The resampled waveform data superposition module is used to superpose the resampled waveform data according to the set number of eye diagram UIs;

[0026] Step 7: The waveform data statistics and frequency calculation module calculates the maximum frequency value and waveform gray value of the waveform according to the superposed waveform data;

[0027] Step 8: The fluorescence image generation module calculates the pixel point color value according to the calculated gray value and generates a fluorescence image.

[0028] In a further technical solution, in Step 2, the bit rate calculation module accepts the setting of the bit rate acquisition method. If the bit rate acquisition method is set to a fixed value, there is no need to calculate anymore. If the bit rate acquisition method is set to automatic, it is necessary to perform a histogram statistics on the collected data, find the maximum level with the largest number of points and the minimum level with the largest number of points. The average value of the maximum level and the minimum level is the intermediate level value of the serial bus signal. Then, according to the intermediate level value, calculate the minimum pulse value of the collected data, and this value is considered to be the bit rate of the serial bus signal.

[0029] In a further technical solution, in Step 3, assume that each bit of the serial bus signal requires N sampling points when displayed in the eye diagram, the sampling rate of the oscilloscope is S, and the bit rate of the serial bus signal is R. If N*R > S, interpolation with a factor of L = N*R / S is required. If N*R < S, decimation with a factor of L = S / N*R is required; the interpolation and decimation algorithms use the sine interpolation method of formula (1);

[0030]

[0031] In the formula, x(t) represents the sample value after interpolation or decimation, x n Represents the original sampling value of the nth sampling period, Sa is the sinc function, f s1 Represents the angular velocity of the original sample value, T s1 Represents the period of the original sampling value, and n represents the nth sampling period.

[0032] In a further technical solution, in step four, software phase-locked loop clock recovery and data resampling are implemented in one process, the phase detector obtains the phase error by calculating the resampled data of the interpolation module, and sends it to the interpolation control module after passing through the loop filter, the interpolation control module generates an interpolation control factor and sends it to the interpolation module, the interpolation module resamples the real number multiple variable sampling data according to the interpolation control factor to generate resampled data.

[0033] In a further technical solution, the phase detector first performs sign bit judgment on the real number multiple sampling data, and a sign bit greater than the intermediate level is 1, and a sign bit less than the intermediate level is -1, and the phase error is obtained by formula (2):

[0034]

[0035] In the formula, e represents the phase error, a1 represents the value of the first sign bit, and a l Indicates the value of the lth sign bit, a 2L+1 Represents the value of the 2L+1th sign bit, l represents the lth sign bit, and L represents the interpolation multiple.

[0036] In a further technical solution, in step five, the phase-locked loop lock judgment module calculates the mean and variance of the phase error calculated by the phase detector of a certain length in a sliding manner. When the variance of the mean is less than the set value, the phase-locked loop is considered to be in a locked state; when the variance of the mean is greater than the set value, the phase-locked loop is considered to be in an unlocked state.

[0037] In a further technical solution, in step seven, the calculation method of the waveform grayscale value is as shown in formula (3):

[0038]

[0039] In the formula, P represents the frequency value, P max Represents the maximum frequency value.

[0040] Through the above technical solution, the eye diagram generation system and method for a high-resolution oscilloscope provided by the present invention have the following beneficial effects:

[0041] The present invention performs clock recovery based on a software phase-locked loop (PLL), and realizes accurate cutting and superposition of eye diagrams based on the recovered clock, and then performs frequency calculation and eye diagram fluorescent image generation. The clock recovered by the software phase-locked loop (PLL) is calculated from the sampling data of a high-resolution oscilloscope, without jitter or noise introduced by the hardware circuit, and without the trigger jitter of the clock and data recovery (CDR) circuit, that is, the trigger jitter is zero. The clock recovery method of the software phase-locked loop (PLL) can also output the clock normally when the sampling data is continuous and unchanged, and can also realize waveform superposition with a short dead time. The method can not only analyze the serial bus sampling data of a high-resolution oscilloscope in real time, but also perform offline analysis based on historical acquisition data.

[0042] Therefore, the method of the present invention adopts the method of using a software phase-locked loop to output clock synchronous cutting and superposition display. This method has the advantages of high eye diagram generation efficiency, zero trigger jitter, zero jitter of clock recovery, offline analysis and tracking and positioning. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0044] Figure 1 A schematic flow chart of a method for generating an eye diagram for a high-resolution oscilloscope disclosed in an embodiment of the present invention;

[0045] Figure 2 A schematic diagram of a software phase-locked loop clock recovery and data resampling module disclosed in an embodiment of the present invention;

[0046] Figure 3 The present invention is a schematic diagram of an eye diagram generation system for a high-resolution oscilloscope disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0048] The present invention provides an eye diagram generation system for a high-resolution oscilloscope, such as Figure 3 As shown, it includes the following components:

[0049] Data sampling module: used to realize the acquisition, analog-to-digital conversion and storage of serial bus signals of high-resolution oscilloscope;

[0050] Bit rate calculation module: used to calculate the bit rate of the serial bus signal;

[0051] Real-number multiple interpolation module: used to perform real-number multiple interpolation on the collected serial bus signal to obtain real-number multiple variable sampling data;

[0052] Software phase-locked loop clock recovery and data resampling module: used to perform software phase-locked loop clock recovery and data resampling on real-number multiple sampling data to obtain resampled waveform data;

[0053] Phase-locked loop lock judgment module: used to judge whether the phase-locked loop is in a locked state;

[0054] Resampled waveform data superposition module: When the phase-locked loop is locked, the resampled waveform data superposition module is used to superimpose the resampled waveform data according to the set number of eye diagram UIs;

[0055] Waveform data statistics and frequency calculation module: used to calculate the maximum frequency value and waveform gray value of the waveform based on the superimposed waveform data;

[0056] Fluorescence image generation module: used to calculate the pixel color value according to the calculated gray value and generate a fluorescence image.

[0057] In this embodiment, the software phase-locked loop clock recovery and data resampling module includes an interpolation module, a phase detector, a loop filter and an interpolation control module. The phase detector adopts a multi-sampling bang-bang phase detector, the interpolator of the interpolation module adopts a polynomial interpolation filter with a Farrow structure, the loop filter adopts a low-pass filter, and the interpolation control module adopts an interpolation controller with Mod-1 counting.

[0058] A method for generating eye diagrams for high-resolution oscilloscopes, such as Figure 1 As shown, an eye diagram generation system for a high-resolution oscilloscope as described above is used, comprising the following steps:

[0059] Step 1: The data sampling module collects the serial bus signal of the high-resolution oscilloscope through the high-resolution ADC, performs analog-to-digital conversion, and stores it in the memory stick;

[0060] Step 2, the bit rate calculation module calculates the bit rate of the serial bus signal;

[0061] The bit rate calculation module accepts the bit rate acquisition mode setting. If the bit rate acquisition mode is set to a fixed value, no further calculation is required. If the bit rate acquisition mode is set to automatic, it is necessary to make a histogram statistics of the collected data to find the maximum level with the most points and the minimum level with the most points. The average of the maximum level and the minimum level is the middle level value of the serial bus signal. Then, the minimum pulse value of the collected data is calculated based on the middle level value. This value is considered to be the bit rate of the serial bus signal.

[0062] Step 3: The real-number multiple interpolation module performs real-number multiple interpolation on the collected serial bus signals to obtain real-number multiple variable sampling data;

[0063] Since the bit rate calculated according to Step 2 and the sampling rate of the high-resolution oscilloscope are not necessarily in an integer multiple relationship, real-number multiple interpolation of the collected data is required. Assume that each bit of the serial bus signal requires N sampling points for eye diagram display, the sampling rate of the oscilloscope is S, and the bit rate of the serial bus signal is R. If N*R > S, interpolation by a factor of L = N*R / S is required. If N*R < S, decimation by a factor of L = S / N*R is required; the interpolation and decimation algorithms use the sine interpolation method of formula (1);

[0064]

[0065] where x(t) represents the sampled value after interpolation or decimation, x n represents the original sampled value at the nth sampling period, Sa is the sinc function, f s1 represents the angular velocity of the original sampled value, T s1 represents the period of the original sampled value, and n represents the nth sampling period.

[0066] Step 4: The software phase-locked loop clock recovery and data resampling module performs software phase-locked loop clock recovery and data resampling on the real-number multiple variable sampling data to obtain resampled waveform data;

[0067] As Figure 2 shown, the software phase-locked loop clock recovery and data resampling are implemented in one process. The phase detector obtains the phase error by calculating the resampled data of the interpolation module, which is sent to the interpolation control module after passing through the loop filter. The interpolation control module generates an interpolation control factor and sends it to the interpolation module. The interpolation module resamples the real-number multiple variable sampling data according to the interpolation control factor to generate resampled data. The process of the interpolation control module generating the interpolation control factor is the process of clock recovery, and no external clock is required.

[0068] The phase detector first determines the sign bit of the real-number multiple variable sampling data. If it is greater than the middle level, it is 1; if it is less than the middle level, it is -1. The phase error is obtained through formula (2):

[0069]

[0070] where e represents the phase error, a1 represents the value of the first sign bit, a l represents the value of the lth sign bit, a 2L+1 represents the value of the (2L + 1)th sign bit, l represents the lth sign bit, and L represents the interpolation multiple.

[0071] Step 5: The phase-locked loop lock judgment module judges the phase-locked loop state. When the phase-locked loop is in a locked state, step 6 is performed. When the phase-locked loop is in an unlocked state, the module returns to step 4.

[0072] The phase-locked loop lock judgment module calculates the mean and variance of the phase error calculated by the phase detector of a certain length in a sliding manner. When the variance of the mean is less than the set value, the phase-locked loop is considered to be in a locked state. When the variance of the mean is greater than the set value, the phase-locked loop is considered to be in an unlocked state.

[0073] Step 6, the resampled waveform data superposition module is used to superimpose the resampled waveform data according to the set number of eye diagram UIs;

[0074] Step 7, the waveform data statistics and frequency calculation module calculates the maximum frequency value and waveform gray value of the waveform according to the superimposed waveform data;

[0075] The calculation method of the waveform gray value is shown in formula (3):

[0076]

[0077] In the formula, P represents the frequency value, P max Represents the maximum frequency value.

[0078] Step eight, the fluorescence image generation module calculates the pixel color value according to the calculated gray value and generates a fluorescence image.

[0079] go through Figure 2 and Figure 3 After the process shown, a fluorescent image of the eye diagram is obtained. The user can also use the image to calculate some parameters of the eye diagram and observe the brightness of the image to determine the trajectory of the physical layer signal of the serial bus.

[0080] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An eye diagram generation system for a high-resolution oscilloscope, characterized in that: It includes the following components: Data sampling module: used to implement the acquisition, analog-to-digital conversion and storage of serial bus signals of a high-resolution oscilloscope; Bit rate calculation module: used to calculate the bit rate of serial bus signals; Real number multiple interpolation module: used to perform real number multiple interpolation on the acquired serial bus signals to obtain real number multiple variable sampling data; Software phase-locked loop clock recovery and data resampling module: used to perform software phase-locked loop clock recovery and data resampling on the real number multiple variable sampling data to obtain resampled waveform data; Phase-locked loop locking judgment module: used to judge whether the phase-locked loop is in a locked state; Resampled waveform data superposition module: after the phase-locked loop is locked, the resampled waveform data superposition module is used to superimpose the resampled waveform data according to the set number of eye diagram UIs; Waveform data statistics and frequency calculation module: used to calculate the maximum frequency value and waveform gray value of the waveform according to the superimposed waveform data; Fluorescent image generation module: used to calculate the pixel point color value according to the calculated gray value and generate a fluorescent image; The software phase-locked loop clock recovery and data resampling module includes an interpolation module, a phase detector, a loop filter and an interpolation control module; The phase detector adopts a multi-sampling bang-bang phase detector, the interpolator of the interpolation module adopts a polynomial interpolation filter with a Farrow structure, the loop filter adopts a low-pass filter, and the interpolation control module adopts an interpolation controller with Mod-1 counting; Assume that each bit of the serial bus signal requires N sampling points when displayed in the eye diagram, the sampling rate of the oscilloscope is S, and the bit rate of the serial bus signal is R. If N*R > S, then interpolation with a factor of L = N*R / S is required. If N*R < S, then decimation with a factor of L = S / N*R is required; The interpolation and decimation algorithms adopt the sine interpolation method of formula (1); （1） Where x(t) represents the sample value after interpolation or decimation. x n Indicates n The original sampling value of the sampling period, Sa is the sinc function, f s1 Represents the angular velocity of the original sample value, T s1 Represents the period of the original sampling value, n Indicates n Sampling period; The phase detector first judges the sign bit of the real number multiple variable sampling data, greater than the middle level is 1, less than the middle level is -1, and obtains the phase error through formula (2): （2） In the formula, represents the phase error, Indicates the value of the first sign bit, Indicates The value of the sign bit, Indicates The value of the sign bit, Indicates Sign bit, Indicates the interpolation multiple.

2. A method for generating an eye diagram for a high-resolution oscilloscope, using the eye diagram generating system for a high-resolution oscilloscope as claimed in claim 1, characterized in that: It includes the following steps: Step 1, the data sampling module collects the serial bus signal of the high-resolution oscilloscope through a high-resolution ADC, performs analog-to-digital conversion and stores it in the memory module; Step 2, the bit rate calculation module calculates the bit rate of the serial bus signal; Step 3, the real number multiple interpolation module performs real number multiple interpolation on the acquired serial bus signal to obtain real number multiple variable sampling data; Step 4, the software phase-locked loop clock recovery and data resampling module performs software phase-locked loop clock recovery and data resampling on the real number multiple variable sampling data to obtain resampled waveform data; Step 5, the phase-locked loop locking judgment module judges the state of the phase-locked loop. When the phase-locked loop is in the locked state, go to Step 6. When the phase-locked loop is in the unlocked state, return to Step 4; Step 6, the resampled waveform data superposition module is used to superimpose the resampled waveform data according to the set number of eye diagram UIs; Step 7, the waveform data statistics and frequency calculation module calculates the maximum frequency value and waveform gray value of the waveform according to the superimposed waveform data; Step eight, the fluorescence image generation module calculates the pixel color value according to the calculated gray value and generates a fluorescence image.

3. The eye diagram generation method for a high-resolution oscilloscope according to claim 2, characterized in that: In the step 2, the bit rate calculation module accepts the bit rate acquisition mode setting. If the bit rate acquisition mode is set to a fixed value, no further calculation is required; if the bit rate acquisition mode is set to automatic, it is necessary to make a histogram statistics of the collected data to find the maximum level with the most points and the minimum level with the most points. The average of the maximum level and the minimum level is the middle level value of the serial bus signal, and then the minimum pulse value of the collected data is calculated based on the middle level value, and this value is considered to be the bit rate of the serial bus signal.

4. The eye diagram generation method for a high-resolution oscilloscope according to claim 2, characterized in that: In the step 4, the software phase-locked loop clock recovery and data resampling are implemented in one process, the phase detector obtains the phase error by calculating the resampled data of the interpolation module, and sends it to the interpolation control module after passing through the loop filter, the interpolation control module generates an interpolation control factor and sends it to the interpolation module, the interpolation module resamples the real number multiple variable sampling data according to the interpolation control factor to generate resampled data.

5. The eye diagram generation method for a high-resolution oscilloscope according to claim 2, characterized in that: In the step 5, the phase-locked loop lock judgment module calculates the mean and the variance of the phase error calculated by the phase detector of a certain length in a sliding manner. When the variance of the mean is less than the set value, the phase-locked loop is considered to be in a locked state; when the variance of the mean is greater than the set value, the phase-locked loop is considered to be in an unlocked state.

6. The eye diagram generation method for a high-resolution oscilloscope according to claim 2, characterized in that: In step 7, the calculation method of the waveform gray value is shown in formula (3): （3） In the formula, represents the frequency value, Represents the maximum frequency value.

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