An 8-channel high-speed synchronous broadband signal acquisition and processing module

Abstract

The present invention discloses an 8-channel high-speed synchronous broadband signal acquisition and processing module, which relates to the technical field of high-speed broadband signal acquisition. It mainly consists of 6 functional units, namely: a high-speed broadband signal acquisition functional unit, a multi-signal synchronization and signal processing functional unit, an external interface and communication control functional unit, a clock management functional unit, a power management functional unit, and a health management functional unit. Its main framework is: 2 pieces of V7 FPGA + 1 piece of K7 FPGA + 1 piece of MCU + 8-channel high-speed AD + 6U VPX module. The present invention can be applied to radar reconnaissance and radar countermeasure aspects, and can complete the acquisition, synchronization, detection, parameter measurement, phase discrimination and direction finding of two groups of 4-channel or one group of 8-channel intermediate frequency signals. Moreover, it has the characteristics of high bandwidth, high dynamic range and high sensitivity.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed broadband signal acquisition, and particularly relates to an 8-channel high-speed synchronous broadband signal acquisition and processing module. Background Art

[0002] The statements in this section only provide background information related to the present disclosure and may not constitute prior art.

[0003] For a multi-channel high-speed synchronous broadband signal acquisition and processing module to achieve signal measurement, direction finding, and cooperative positioning functions, the most critical technical indicators mainly include sensitivity, number of effective bits, spurious-free dynamic range, and phase synchronization.

[0004] The sampling frequency and resolution of the ADC are the most important indicators in high-speed acquisition and are the most critical factors affecting sensitivity and the number of effective bits. Among them, the sampling frequency and the operating rate of the ADC generally need to satisfy the Nyquist sampling theorem to avoid signal spectrum aliasing. According to the Nyquist sampling theorem, it is required that the sampling frequency f s ≥2f max , where f max is the highest frequency of the signal to be sampled. The Nyquist sampling theorem only discusses the sampling problem of signals with spectral distributions in (0, f max ). Now, it is necessary to sample bandpass signals distributed in a certain finite frequency band (f L , f H ). Although the Nyquist sampling theorem f s ≥2f max can also be used, but f H >>(f H -f L ) = B, that is, the highest frequency of the signal is much greater than the signal bandwidth, which makes it difficult to implement high-speed ADC devices, requires a high speed for subsequent digital signal processing, and is difficult for real-time processing.

[0005] In the multi-channel phase synchronization technology, in order to ensure the same layout and wiring for each channel, a common-source and common-phase clock is one of the key technologies. Currently, the analog clock of the common-source and common-phase clock is the same as the digital clock in system processing, resulting in an increase in spurious signals in the AD acquisition signal. In addition, the traditional data transmission bus of the ADC is a parallel LVDS bus. The chips using this ADC bus are large in volume and high in power consumption, increasing the complexity of the circuit. Summary of the Invention

[0006] The purpose of the present invention is to provide an 8-channel high-speed synchronous broadband signal acquisition and processing module for the current technical requirements and problems of multi-channel high-speed synchronous broadband signal acquisition and processing modules, which reduces the complexity and power consumption of the module circuit and can miniaturize the module, thus solving the above problems.

[0007] The technical solution of the present invention is as follows:

[0008] An 8-channel high-speed synchronous broadband signal acquisition and processing module, comprising:

[0009] A high-speed broadband signal acquisition functional unit, the high-speed broadband signal acquisition functional unit includes 8 ADC channels, which are respectively used to acquire broadband signals of 8 channels, the sampling frequency range is 2 GHz to 18 GHz, the sampling rate is 2.4 GHz, and the resolution is 12 bits;

[0010] A multi-signal synchronization and signal processing functional unit, the multi-signal synchronization and signal processing functional unit includes two FPGAs, and the two FPGAs respectively complete the digital signal processing of 4 ADC channels;

[0011] An external interface and communication control functional unit, the external interface and communication control functional unit is used to realize data fusion, clock configuration, ADC configuration, management control, external interface communication and control of the two FPGAs;

[0012] A health management functional unit, the health management functional unit realizes the health status monitoring and management of each module;

[0013] A clock circuit functional unit, the clock circuit functional unit provides a working clock for each module;

[0014] A power management functional unit, the power management functional unit provides power for each module.

[0015] Further, the ADC chip model in the ADC channel is AD9625BBPZ-2.5, and the SPI configuration interface of the AD9625BBPZ-2.5 chip is a 3-wire interface with a maximum rate of 25 MHz to realize the configuration of working parameters.

[0016] Further, a band-pass filter is provided in the ADC channel, and the band-pass filter model is BFCN5032-1800A01;

[0017] A 33-ohm resistor is connected in series in the ADC channel to reduce bandwidth peaking and minimize the impact of the back-off of the ADC sampling capacitor.

[0018] Further, the digital signal processing includes: ADC acquisition and synchronization, frequency-domain preprocessing, threshold generation and over-threshold detection, time-frequency correlation, parameter extraction, and multi-channel amplitude-phase information extraction.

[0019] Further, the multi-signal synchronization and signal processing functional unit includes: FPAG1 and FPGA2; the chip models of FPAG1 and FPGA2 are XC7VX690TFFG1927I.

[0020] Furthermore, the health management functional unit includes: an STM32, which is connected to a VPX connector through a CAN bus; the STM32 performs voltage detection, PCB board temperature detection, and ADC chip operating temperature detection.

[0021] Furthermore, the external interface and communication control functional unit includes: an FPGA3; the model of the FPGA3 chip is XC7K325T-2FFG900I;

[0022] The external interfaces of the FPGA3 are uniformly external through the VPX connector interface;

[0023] The FPGA3 is provided with 4 RS422 interfaces for fast attenuation control;

[0024] The FPGA3 is provided with 2 RS232 interfaces, one for communicating with the STM32 and one for debugging;

[0025] The FPGA3 is provided with 2 groups of 8 LVTTL interfaces, which are output after being buffered by a driver chip; the model of the driver chip is SN74LVC16T245DGGR;

[0026] The FPGA3 outputs 2 groups of 4 MLVDS buses through an MLVDS transceiver chip; the model of the MLVDS transceiver chip is DS91M040TSQ, and each MLVDS transceiver chip outputs 4 MLVDS buses.

[0027] Furthermore, two groups of DDR3 chips are externally connected to both the FPAG1 and FPGA2 to achieve real-time storage of 1-channel AD high-speed acquisition data and data caching of 1-channel AD data for 130 ms;

[0028] One Nor Flash is attached to each of the FPAG1, FPGA2, and FPGA3.

[0029] Furthermore, a group of 8 GTX interfaces are reserved between the FPGA1 and FPGA2;

[0030] Forty-eight pairs of LVDS interfaces are reserved between the FPGA1 and FPGA2, including 2 pairs of LVDS clock signals;

[0031] A group of 4 GTX interfaces are reserved between the FPGA1 and FPGA3;

[0032] Twenty-four pairs of LVDS interfaces are reserved between the FPGA1 and FPGA3, including 2 pairs of LVDS clock signals;

[0033] A group of 4 GTX interfaces are reserved between the FPGA2 and FPGA3;

[0034] There are 24 pairs of LVDS interfaces reserved between FPGA2 and FPGA3, including 2 pairs of LVDS clock signals.

[0035] There is a reserved SPI bus interface and a reserved UART interface between FPGA3 and STM32.

[0036] Furthermore, the clock circuit functional unit includes: a PPL chip, a clock BUFFER chip, a 50M active crystal oscillator, and a 10M VCXO.

[0037] Compared with the existing technology, the beneficial effects of the present invention are:

[0038] An 8-channel high-speed synchronous broadband signal acquisition and processing module can be applied to radar reconnaissance and radar countermeasure fields, and can complete the acquisition, synchronization, detection, parameter measurement, phase discrimination, and direction finding of two groups of 4-channel or one group of 8-channel intermediate frequency signals; and it has the characteristics of high bandwidth, high dynamic range, and high sensitivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a principle block diagram of an 8-channel high-speed synchronous broadband signal acquisition and processing module;

[0040] Figure 2 It is a block diagram of the high-speed broadband signal acquisition functional unit;

[0041] Figure 3 It is a principle design block diagram of the high-speed broadband signal acquisition functional unit;

[0042] Figure 4 It is a block diagram of the multi-signal synchronization and signal processing functional unit;

[0043] Figure 5 It is a schematic diagram of the STM32 power supply and bypass filter circuit;

[0044] Figure 6 It is a schematic diagram of the ADC voltage acquisition circuit;

[0045] Figure 7 It is a block diagram of the health management functional unit;

[0046] Figure 8 It is a schematic diagram of the application circuit of MAX3232ESE+;

[0047] Figure 9 It is a block diagram of the external interface and communication control functional unit;

[0048] Figure 10 It is a schematic diagram of the application circuit of MAX3491ESD+;

[0049] Figure 11Schematic diagram of the principle of DS91M040TSQ;

[0050] Figure 12 Schematic block diagram of the principle of the FPGA memory expansion circuit;

[0051] Figure 13 Schematic diagram of the configuration circuit of FPGA1;

[0052] Figure 14 Schematic diagram of the wiring relationship of daisy-chain loading FPGA;

[0053] Figure 15 Schematic block diagram of the principle of the clock circuit functional unit;

[0054] Figure 16 Power topology diagram of the power management functional unit. Specific implementation manners

[0055] It should be noted that relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0056] The features and performance of the present invention will be further described in detail below in conjunction with embodiments.

[0057] Embodiment 1

[0058] The multi-channel high-speed synchronous broadband signal acquisition and processing module needs to implement signal measurement, direction finding and cooperative positioning functions. The most critical technical indicators mainly include sensitivity, number of effective bits, spurious-free dynamic range and phase synchronization.

[0059] The sampling frequency and resolution of the ADC are the most important indicators in high-speed acquisition and the most critical factors affecting sensitivity and number of effective bits. The sampling frequency and the working rate of the ADC generally need to satisfy the Nyquist sampling theorem to avoid signal spectrum aliasing. According to the Nyquist sampling theorem, the sampling frequency f s ≥2f max , where f max is the highest frequency of the signal to be sampled. The Nyquist sampling theorem only discusses the spectrum distribution in (0, f max) The problem of signal sampling on [topic], now it is necessary to sample the band-pass signal distributed in a certain finite frequency band (f L , f H ). Although the Nyquist sampling theorem f s ≥ 2f max can also be used, but f H >> (f H - f L ) = B, that is, the highest frequency of the signal is much greater than the signal bandwidth, which makes it difficult to implement high-speed ADC devices, requires high speed for subsequent digital signal processing, and is difficult for real-time processing.

[0060] In this embodiment, to solve this problem, band-pass sampling is adopted in an 8-channel high-speed synchronous broadband signal acquisition and processing module to avoid signal spectrum aliasing. The formula for estimating the sampling frequency of band-pass sampling is as follows:

[0061]

[0062] In the formula:

[0063] f i is the center frequency of the band-pass signal; m is the largest positive integer (0, 1, 2...) that makes f s satisfy f s ≥ 2B, where B is the bandwidth.

[0064] An 8-channel high-speed synchronous broadband signal acquisition and processing module adopts band-pass sampling, which reduces the sampling frequency. The ADC chip can select a higher resolution, thereby improving its sensitivity and effective number of bits.

[0065] The ADC resolution generally refers to its number of bits. The ADC resolution of traditional broadband signal acquisition is 8 bits. In this embodiment, the ADC resolution is increased to 12 bits, which can greatly improve the effective number of bits and sensitivity of the module.

[0066] And an 8-channel high-speed synchronous broadband signal acquisition and processing module replaces the traditional overlapping sampling mode. Since the overlapping sampling is composed of spliced sampling signals, slightly different DC offsets will bring signal spurs; after replacing the overlapping sampling, the spurious-free dynamic range of the module can be improved.

[0067] In the multi-channel phase synchronization technology, to ensure the same layout and wiring for each channel; the same-source and same-phase clock is one of the key technologies. Currently, the analog clock of the same-source and same-phase clock and the digital clock in system processing are the same clock, resulting in an increase in spurious signals in the AD acquisition signal.

[0068] In this embodiment, an 8-channel high-speed synchronous broadband signal acquisition and processing module proposed adopts digital clock isolation from the analog clock and can ensure clock homology and sample clock in the same direction; improving the performance index of the module.

[0069] In addition, the data transmission bus of the traditional ADC is a parallel LVDS bus. The chip using this ADC bus has a large volume and high power consumption, increasing the complexity of the circuit.

[0070] In this embodiment, an ADC using the JESD204B interface is adopted in an 8-channel high-speed synchronous broadband signal acquisition and processing module.

[0071] JESD204B is a new type of data interface based on high-speed SERDES. The Lane rate can reach 12.5 Gbps. The timing control of this interface is simple, without worrying about channel offset, and the wiring is convenient. The ADC device with the JESD204B interface has a small volume, saving PCB layout space. Thus, it reduces the complexity and power consumption of the module circuit and enables the miniaturization of the module.

[0072] Meanwhile, the 8-channel high-speed synchronous broadband signal acquisition and processing module belongs to an electronic countermeasure system.

[0073] Among them, the required frequency band is 2 GHz to 18 GHz, the intermediate frequency center frequency is 1.8 GHz, and the instantaneous bandwidth is 1 GHz (1.3 GHz to 2.3 GHz); the single-tone dynamic range is greater than 40 dB, and the detection range is not less than 300 kilometers; the system sensitivity in the 8 GHz to 12 GHz frequency band range is not greater than -77 dBm, and the system sensitivity in the 2 GHz to 8 GHz and 12 GHz to 18 GHz frequency band ranges is not greater than -70 dBm.

[0074] The pulse width adaptation range is 200 nanoseconds to 2 milliseconds, and the measurement error is not greater than (0.1 + 5% PW) microseconds; the pulse repetition interval adaptation range is 2 microseconds to 2 milliseconds, and the measurement error is not greater than (0.1 + 5% PRI) microseconds; the root mean square error of the operating frequency measurement is not greater than 1 MHz, the amplitude measurement accuracy is not greater than ±1 dB, the root mean square error of the direction finding is not greater than 2°, and the collaborative positioning error is not greater than 3% of the actual target distance. The multi-signal processing ability can handle 4 signals simultaneously.

[0075] In this embodiment, an 8-channel high-speed synchronous broadband signal acquisition and processing module mainly consists of 6 functional units, namely: high-speed broadband signal acquisition functional unit, multi-signal synchronization and signal processing functional unit, external interface and communication control functional unit, clock management functional unit, power management functional unit, and health management functional unit; its main framework is: 2 V7 FPGAs + 1 K7 FPGA + 1 MCU + 8-channel high-speed AD + 6U VPX module.

[0076] Please refer to Figure 1 , an 8-channel high-speed synchronous broadband signal acquisition and processing module, specifically including:

[0077] High-speed broadband signal acquisition functional unit, the high-speed broadband signal acquisition functional unit includes 8 ADC channels, which are respectively used to acquire broadband signals of 8 channels, the sampling frequency range is 2 GHz to 18 GHz, the sampling rate is 2.4 GHz, and the resolution is 12 bits;

[0078] Multi-signal synchronization and signal processing functional unit, the multi-signal synchronization and signal processing functional unit includes two FPGAs, and the two FPGAs respectively complete the digital signal processing of 4 ADC channels; preferably, the digital signal processing includes: ADC acquisition and synchronization, frequency-domain preprocessing, threshold generation and over-threshold detection, time-frequency correlation, parameter extraction, and multi-channel amplitude-phase information extraction and other processing processes;

[0079] External interface and communication control functional unit, the external interface and communication control functional unit is used to realize data fusion, clock configuration, ADC configuration, management control, external interface communication, and control of the two FPGAs;

[0080] Health management functional unit, the health management functional unit realizes the health status monitoring and management of each module;

[0081] Clock circuit functional unit, the clock circuit functional unit provides working clocks for each module;

[0082] Power management functional unit, the power management functional unit provides power for each module; Figure 16 The power topology diagram of the power management functional unit is given.

[0083] In this embodiment, specifically, the block diagram of the high-speed broadband signal acquisition functional unit is as Figure 2 shown; the high-speed broadband signal acquisition functional unit mainly completes the acquisition of 8-channel high-speed signals; the ADC chip model in the ADC channel is AD9625BBPZ-2.5, and the SPI configuration interface of the AD9625BBPZ-2.5 chip is a 3-wire interface with a maximum rate of 25 MHz to realize the configuration of working parameters; that is, the ADC chip selects the AD9625BBPZ-2.5 chip of AD company.

[0084] The indicators of the AD9625BBPZ-2.5 chip are as follows:

[0085] Resolution 12 bits, sampling rate 2.5 GSPS, no missing codes

[0086] SFDR = 79 dBc, AIN up to 1 GHz (-1 dBFS, 2.5 GSPS)

[0087] SFDR = 75 dBc, AIN up to 1.8 GHz (-1 dBFS, 2.5 GSPS)

[0088] SNR = 57.6 dBFS, AIN up to 1 GHz (-1 dBFS, 2.5 GSPS)

[0089] SNR = 56.7 dBFS, AIN up to 1.8 GHz (-1 dBFS, 2.5 GSPS)

[0090] Noise spectral density = -150 dBFS / Hz (2.5 GSPS)

[0091] Power consumption: 3.8 W (2.5 GSPS)

[0092] Differential analog input: 1.1 Vp-p

[0093] Differential clock input

[0094] High-speed 6 or 8-channel JESD204B serial output

[0095] Two independent 1 / 8 decimation or 1 / 16 decimation filters and 10-bit NCO

[0096] Supply voltage: 1.3 V, 2.5 V

[0097] Serial port control.

[0098] It should be noted that the digital output of AD9625BBPZ-2.5 complies with the JEDEC standard (Standard No.: JESD204B, Serial Interface for Data Converters); JESD204B is the protocol for AD9625BBPZ-2.5 to connect to the FPGA through the serial interface (maximum link speed of 6.5 Gbps); compared with LVDS, the advantages of the JESD204B interface include: less circuit board space required for data interface routing, and smaller packages for converters and logic devices; AD9625 supports 1, 2, 4, 6 or 8 output channels; the output interface of AD9625BBPZ-2.5 uses an AC coupling method with a capacitance of 0.1 uf.

[0099] In this embodiment, specifically, Figure 3 is the principle design block diagram of the high-speed broadband signal acquisition functional unit. A band-pass filter is provided in the ADC channel, and the model of the band-pass filter is BFCN5032-1800A01; that is, the band-pass filter selects BFCN5032-1800A01 of Guiyang Sunlord Xunda, and the performance indicators are as follows.

[0100] Table 1 Performance Indicators of BFCN5032-1800A01

[0101]

[0102]

[0103] A 33-ohm resistor is connected in series in the ADC channel to reduce bandwidth peaking and minimize the back-off effect of the ADC sampling capacitor. Preferably, filtering and single-ended to differential Balun need to be considered for the analog input, and the Balun selects the B0430J50100AHF of Anaren.

[0104] It should be noted that the sampling clock of the ADC is a 2.4G differential clock, and the peak-to-peak level is 250mVpp to 1800mVpp. In this embodiment, the LVPECL differential clock is output by ADCLK950 to drive the AD clock. When the 2.4G differential clock is output, the LVPECL peak-to-peak level is 1400mVpp, which can meet the ADC clock driving requirements.

[0105] The ADC requires two power supplies of 2.5V and 1.3V, and the total power consumption of a single chip is 3.8W. The power consumption requirements for the two power supplies are 392mA and 1986mA respectively. To achieve good analog performance, except for the transfer power supply, all the power supplies of the ADC are powered by LDO, and the analog and digital are powered by different LDOs respectively.

[0106] The output voltage of the AD temperature monitoring is connected to the AD pin of FPGA3 to realize AD temperature monitoring.

[0107] In this embodiment, specifically, the block diagram of the multi-signal synchronization and signal processing functional unit is as Figure 4 shown. The multi-signal synchronization and signal processing functional unit includes: FPAG1 and FPGA2; FPGA1 and FPGA2 are the main processing chips for receiving and processing, mainly completing the acquisition, synchronization, detection, parameter measurement, phase discrimination and direction finding of two groups of 4-channel intermediate frequency signals. Therefore, the FPAG1 and FPGA2 chips need to have strong processing capabilities; thus, the FPAG1 and FPGA2 are planned to use the Virtex7 series of Xilinx, with the model number XC7VX690TFFG1927I; this chip has a total of 600 available IOs, 80 high-speed GTH interfaces, and 3600 multiplier resources; this chip has rich resources and strong signal processing capabilities.

[0108] In this embodiment, specifically, the principle block diagram of the health management functional unit is as Figure 7 shown; the health management functional unit includes: STM32, and the STM32 mainly realizes the monitoring of 1 CAN bus and the working states of each module, that is, the STM32 is connected to the VPX connector through the CAN bus, and the STM32 performs voltage detection, PCB board temperature detection, and ADC chip working temperature detection; preferably, the specific model of the STM32 is: STM32F407VET6; the reference design of the STM32 power supply and bypass filtering circuit is asFigure 5 as shown

[0109] The ADC voltage acquisition circuit is as Figure 6 shown; The STM32 has a built-in single-channel ADC with a sampling rate of 2Msps, a resolution of 12 bits, an input voltage range of 3.3VDC. The capacitor C is selected as 5pf, and R is calculated by the following formula. A size not exceeding 10K can meet the requirements.

[0110]

[0111] In this embodiment, preferably, please refer to Figure 7 , the CAN bus chip selects the TJA1050T of PHILIPS; its data rate can reach 1M, is compatible with 3.3V and 5.0V levels, and supports at least 110 CAN bus nodes, meeting the ISO11898 standard.

[0112] The health management functional unit includes 2 RS232s. One serial port each from FPGA3 and STM32 is used for debugging; among them, the debugging serial chip MAXIM selects the MAX3232ESE+; using this chip can directly convert it into a standard serial port and isolate the external operation IO from the MCU IO port; The application circuit of MAX3232ESE+ is as Figure 8 shown

[0113] In this embodiment, specifically, please refer to Figure 9 , the external interface and communication control functional unit includes: FPGA3; that is, the FPGA3 is mainly used for co-processing and external interface functions; preferably, the FPGA3 selects the XC7K325T-2FFG900I of Xilinx; that is, the FPGA3 chip model is XC7K325T-2FFG900I; preferably, the 7-series FPGA supports loading methods such as master serial, slave serial, master SPI, master BPI, JTAG, etc. The Master BPI loading method has the fastest loading speed and large capacity, and can pre-store 3 software versions. Therefore, in this embodiment, both XC7K325T-2FFG900I and XC7VX690TFFG1927I select the Master BPI loading method;

[0114] The external interface of the FPGA3 is uniformly external through the VPX connector interface; preferably, the VPX connector selects the VPX-61T8aAA8NNDD8-A-02 (plug) / VPX-61Z8eIJ8NNDD8-A (socket) of Factory 158; among them, the statistics and pin descriptions of the external interface of the VPX connector are shown in the following table.

[0115] Table Statistics and Pin Descriptions of the External Interface of the VPX Connector

[0116]

[0117]

[0118]

[0119] The FPGA3 is provided with 4 RS422 interfaces for fast attenuation control; preferably, the RS422 chip is selected as MAX3491ESD+ of MAXIM Corporation. This chip has the characteristics of simple peripheral circuit, mature and reliable technology, etc. Therefore, this chip is selected for RS422 level conversion. This chip has low power consumption, supports 3.3V power supply, and the maximum transmission rate can reach 12Mbps; this chip has ±15kV ESD protection; the application circuit of MAX3491ESD+ is as Figure 10 shown.

[0120] The FPGA3 is provided with 2 RS232 interfaces. One is used for communication with STM32, and this interface can be directly connected through LVTTL level. The other is used for debugging; preferably, the debugging serial chip MAXIM is selected as MAX3232ESE+. Using this chip can directly convert it into a standard serial port and isolate the external operation IO from the FPGA IO port;

[0121] The FPGA3 is provided with 2 groups of 8 LVTTL interfaces, which are output after being buffered by a driver chip; the model of the driver chip is SN74LVC16T245DGGR; that is, SN74LVC16T245DGGR is divided into two groups, with 8 channels in each group to achieve controllable direction; one group of 8 LVTTL interfaces is used as signal input, and the other group of 8 LVTTL interfaces is used as signal output;

[0122] The FPGA3 outputs 2 groups of 4-channel MLVDS buses through an MLVDS transceiver chip; the model of the MLVDS transceiver chip is DS91M040TSQ. Each MLVDS transceiver chip outputs 4-channel MLVDS buses. Therefore, two such chips are required in total; it should be noted that DS91M040TSQ has 8KV ESD protection, and the data transmission rate reaches 250Mbps. The principle design of DS91M040TSQ is as Figure 11 shown.

[0123] In this embodiment, two groups of DDR3 chips are externally connected to both the FPAG1 and FPGA2 to achieve real-time storage of 1-channel AD high-speed acquisition data and data caching of 1-channel AD data for 130 ms. Preferably, when selecting the DDR3 chips, compatibility with XC7VX690TFFG1927I, technological maturity, capacity, and data bandwidth need to be considered. Finally, the MT41K128M16HA-107IT chip of MICRON Company is determined to be selected to achieve memory expansion. The storage capacity of this chip is as high as 2 Gb, and the maximum read / write rate can reach 1866 MTS. Two groups of DDR3 chips are connected to each V7 chip, and the capacity of each V7 chip reaches 4 Gb, and the data bandwidth is 1866 MTS * 32 = 58.3125 Gbit / s, which realizes real-time storage of 1-channel AD high-speed acquisition data and data caching of 1-channel AD data for 130 ms, and the capacity and data bandwidth can meet the design requirements.

[0124] The working voltage and reference voltage of the MT41K128M16HA-107IT type DDR3 memory are VDD = 1.35V and VTT = 0.675V respectively. Regarding the difference in working voltage, it is found from the device manual that the MT41K series is upward compatible with the 1.5V design application. Therefore, in this embodiment, the design idea of being compatible with both 1.5V and 1.35V is still adopted. The power supply can achieve voltage switching between 1.35V and 1.5V by changing the resistor.

[0125] The DDR3 controller operates at a relatively high speed and has high requirements for the quality of the power supply. Generally, the tolerance error of the working voltage and reference voltage of the DDR3 controller is ±1%. Therefore, in this embodiment, a dedicated linear voltage regulator needs to be selected to provide the voltage required by the DDR3 controller.

[0126] Compared with the SDRAM memory, using the DDR3 memory will greatly improve the data processing rate and memory expansion capacity. There is no DDR3 controller inside the XC7VX690TFFG1927I, and a corresponding DDR3 controller soft core needs to be used to achieve FPGA memory expansion. The DDR3 controller soft core can be pre-configured in the Xilinx development environment to generate a pin assignment table for the principle design. The BANK used for the DDR3 controller shall not be connected to other signals. The principle block diagram of the FPGA memory expansion circuit is as Figure 12 shown; preferably, the memory expansion circuits of FPGA1 and FPGA2 are the same.

[0127] One Nor Flash is connected to each of the FPAG1, FPGA2, and FPGA3. Preferably, the Nor Flash is selected as BPIFlash, and the BPI Flash chip model is S29GL01GP13TFIV10 of SPANSION. The main features of the chip are as follows:

[0128] Supports 3V (2.7~3.6V) read / program / erase operations;

[0129] 90nm microprocessor technology;

[0130] 8-word / 16-byte page read cache;

[0131] 32-word / 64-byte write cache;

[0132] Unified 64Kword / 128Kbyte sector architecture;

[0133] 100,000 erasable;

[0134] 20-year data retention;

[0135] 56-pin TSOP package.

[0136] In this embodiment, preferably, the loading of BPI Flash is designed with reference to the official recommended design circuit. The configuration circuits of FPGA1 and FPGA2 are the same, as Figure 13 shown.

[0137] In this embodiment, specifically, a group of 8-channel GTX interfaces (8 receive and 8 transmit) are reserved between FPGA1 and FPGA2;

[0138] 48 pairs of LVDS interfaces are reserved between FPGA1 and FPGA2, including 2 pairs of LVDS clock with data, connected to the MRCC or SRCC pins;

[0139] A group of 4-channel GTX interfaces are reserved between FPGA1 and FPGA3;

[0140] 24 pairs of LVDS interfaces are reserved between FPGA1 and FPGA3, including 2 pairs of LVDS clock with data, connected to the MRCC or SRCC pins;

[0141] A group of 4-channel GTX interfaces are reserved between FPGA2 and FPGA3;

[0142] 24 pairs of LVDS interfaces are reserved between FPGA2 and FPGA3, including 2 pairs of LVDS clock with data, connected to the MRCC or SRCC pins;

[0143] A SPI bus interface and a UART interface are reserved between FPGA3 and STM32.

[0144] In this embodiment, the JTAG and debug interfaces are placed on the front panel of the module, mainly for debugging. Among them, the pin definitions of the JTAG and debug interfaces are shown in the following table.

[0145] Table 3 Performance Index of BFCN5032-1800A01

[0146]

[0147]

[0148] In this embodiment, preferably, FPGA1, FPGA2, and FPGA3 adopt the daisy-chain loading mode; the wiring relationship of the daisy-chain loaded FPGA is as Figure 14 shown.

[0149] In this embodiment, please refer to Figure 15 , Figure 15 which gives the functional block diagram of the clock circuit; the functional unit of the clock circuit includes: a PPL chip, a clock BUFFER chip, a 50M active crystal oscillator, and a 10M VCXO;

[0150] It should be noted that the clock requirements of an 8-channel high-speed synchronous broadband signal acquisition and processing module proposed in this embodiment are shown in the following table.

[0151] Table 4 Clock Requirements of an 8-channel High-speed Synchronous Broadband Signal Acquisition and Processing Module

[0152]

[0153]

[0154] As can be seen from Table 4, a total of 43 clocks are required, which are derived from 5 different clock sources (100 MHz, 2.4 GHz, 2 VCXOs, 50 MHz crystal oscillator).

[0155] For the JESD204B clock, AD clock, GTX&SRIO, DDR3, and STM32 clock, the PLL chip LMK04828BISQ / NOPB is selected; this chip supports 14 differential clock outputs and supports level standards such as LVDS and LVPECL. The main features of the chip are as follows:

[0156] Supports JESD204B;

[0157] Ultra-low clock jitter and noise;

[0158] Outputs 14 pairs of differential clocks;

[0159] Dual PLL structure;

[0160] The maximum clock output frequency can reach 3.1 GHz;

[0161] The output differential clock level standard is programmable, including LVPECL, LVDS, HSDS, and LCPECL;

[0162] 3.3V operating voltage

[0163] QFN package

[0164] Operating temperature: -45°C to +85°C

[0165] For the 10M VCXO crystal oscillator, select the VC75TAGCP10.0MHz from Jingyu Xing Co., Ltd.; 2 VCXO chips are required; frequency accuracy ±15PPM; voltage control range 0.3 - 3V·50PPM, operating temperature is -40°C to +85°C

[0166] For the 50M active crystal oscillator, select the XO32 - YAGQC - 50MHz from Jingyu Xing Co., Ltd., frequency accuracy and frequency stability ±20PPM. Operating temperature is -40°C to +85°C

[0167] Select the ADCLK950BCPZ from ADI for the clock BUFFER chip; a total of 3 such chips are required, and the technical specifications of this chip are as follows

[0168] 2 selectable differential inputs

[0169] 4.8GHz operating frequency

[0170] 75fs rms broadband random jitter

[0171] On - chip input terminations

[0172] 3.3V power supply

[0173] The above - described embodiments only represent the specific implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the protection scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the technical solution of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application

[0174] This background technology section is provided to generally present the context of the present invention. The work of the currently named inventors, to the extent described in this background technology section, and aspects described in this section that do not constitute prior art at the time of filing this application are neither expressly nor implicitly admitted to be prior art of the present invention

Claims

1. An 8-channel high-speed synchronous broadband signal acquisition and processing module, characterized in that, it includes: A high-speed broadband signal acquisition functional unit, the high-speed broadband signal acquisition functional unit includes 8 ADC channels, which are respectively used to acquire broadband signals of 8 channels, the sampling frequency range is 2 GHz to 18 GHz, the sampling rate is 2.4 GHz, and the resolution is 12 bits; A multi-signal synchronization and signal processing functional unit, the multi-signal synchronization and signal processing functional unit includes two FPGAs, and the two FPGAs respectively complete the digital signal processing of 4 ADC channels; An external interface and communication control functional unit, the external interface and communication control functional unit is used to realize data fusion, clock configuration, ADC configuration, management control, external interface communication and control of the two FPGAs; A health management functional unit, the health management functional unit realizes the health status monitoring and management of each module; A clock circuit functional unit, the clock circuit functional unit provides a working clock for each module; A power management functional unit, the power management functional unit provides power for each module; The external interface and communication control functional unit includes: FPGA3; The chip model of the FPGA3 is XC7K325T-2FFG900I; The external interface of the FPGA3 is uniformly external through the VPX connector interface; The FPGA3 is provided with 4 RS422 interfaces for fast attenuation control; The FPGA3 is provided with 2 RS232 interfaces, 1 for communicating with STM32 and 1 for debugging; The FPGA3 is provided with 2 groups of 8 LVTTL interfaces, which are output after being buffered by a driver chip; the model of the driver chip is SN74LVC16T245DGGR; The FPGA3 outputs 2 groups of 4 MLVDS buses through an MLVDS transceiver chip; the model of the MLVDS transceiver chip is DS91M040TSQ, and each MLVDS transceiver chip outputs 4 MLVDS buses.

2. An 8-channel high-speed synchronous broadband signal acquisition and processing module according to claim 1, characterized in that, The ADC chip model in the ADC channel is AD9625BBPZ-2.5, and the SPI configuration interface of the AD9625BBPZ-2.5 chip is a 3-wire interface with a maximum rate of 25 MHz to realize the configuration of working parameters.

3. An 8-channel high-speed synchronous broadband signal acquisition and processing module according to claim 2, characterized in that, A band-pass filter is provided in the ADC channel, and the model of the band-pass filter is BFCN5032-1800A01; A 33-ohm resistor is connected in series in the ADC channel to reduce bandwidth peaking and minimize the back-off effect of the ADC sampling capacitor.

4. An 8-channel high-speed synchronous broadband signal acquisition and processing module according to claim 3, characterized in that, The digital signal processing includes: ADC acquisition and synchronization, frequency-domain preprocessing, threshold generation and over-threshold detection, time-frequency correlation, parameter extraction, and multi-channel amplitude-phase information extraction.

5. An 8-channel high-speed synchronous broadband signal acquisition and processing module according to claim 1, characterized in that, the multi-signal synchronization and signal processing functional unit includes: FPAG1 and FPGA2; the chip models of the FPAG1 and FPGA2 are XC7VX690TFFG1927I.

6. An 8-channel high-speed synchronous broadband signal acquisition and processing module according to claim 5, characterized in that, the health management functional unit includes: STM32, and the STM32 is connected to the VPX connector through the CAN bus; the STM32 performs voltage detection, PCB board temperature detection, and ADC chip operating temperature detection.

7. An 8-channel high-speed synchronous broadband signal acquisition and processing module according to claim 6, characterized in that, both the FPAG1 and FPGA2 are externally connected with two groups of DDR3 chips to realize real-time storage of 1-channel AD high-speed acquisition data and data caching of 1-channel AD data for 130 ms; one Nor Flash is attached to each of the FPAG1, FPGA2, and FPGA3.

8. An 8-channel high-speed synchronous broadband signal acquisition and processing module according to claim 7, characterized in that, one group of 8-channel GTX interfaces is reserved between the FPGA1 and FPGA2; 48 pairs of LVDS interfaces are reserved between the FPGA1 and FPGA2, including 2 pairs of LVDS clock signals; one group of 4-channel GTX interfaces is reserved between the FPGA1 and FPGA3; 24 pairs of LVDS interfaces are reserved between the FPGA1 and FPGA3, including 2 pairs of LVDS clock signals; one group of 4-channel GTX interfaces is reserved between the FPGA2 and FPGA3; 24 pairs of LVDS interfaces are reserved between the FPGA2 and FPGA3, including 2 pairs of LVDS clock signals; one SPI bus interface and 1 UART interface are reserved between the FPGA3 and STM32.

9. An 8-channel high-speed synchronous broadband signal acquisition and processing module according to claim 1, characterized in that, the clock circuit functional unit includes: a PPL chip, a clock BUFFER chip, a 50M active crystal oscillator, and a 10M VCXO.

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