Method, apparatus, device and storage medium for configuring asynchronous clock divider

Abstract

The application relates to a method, device, equipment and storage medium for configuring an asynchronous clock divider. The method comprises the following steps: configuring a frequency division coefficient of the asynchronous clock divider, calculating a first check code of the frequency division coefficient, judging whether the frequency division coefficient is consistent with a current frequency division coefficient of the asynchronous clock divider, if not, generating a request signal for changing the frequency division coefficient of the asynchronous clock divider, and sending the frequency division coefficient and the first check code to the asynchronous clock divider, controlling the asynchronous clock divider to perform a check operation on the first check code, and if the check passes, updating the current frequency division coefficient of the asynchronous clock divider according to the frequency division coefficient. The application simplifies the configuration process of the asynchronous clock divider, can realize automatic configuration of the frequency division coefficient, can ensure that the frequency division coefficient can be correctly transmitted to the asynchronous clock divider, and improves the reliability and robustness of a chip clock system.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and particularly to a method and device for configuring an asynchronous clock divider, equipment and storage medium. BACKGROUND

[0002] Clock dividers are widely used in chips to provide clock sources for various IPs of the chips. Usually, a dedicated clock management unit is included in the chip to configure the frequency division coefficient and clock gating of the clock divider. The clock for configuring the clock divider and the frequency division coefficient is usually not in the same clock domain, so the frequency division coefficient needs to be processed across clock domains when configuring the frequency division coefficient.

[0003] At present, the configuration of an asynchronous clock divider in the prior art is usually performed through the following steps:

[0004] 1. configuring the frequency division coefficient of the clock divider;

[0005] 2. configuring the update to be equal to 1 through a register to synchronize the level signal to the asynchronous clock domain of the clock divider;

[0006] 3. the clock divider in the asynchronous clock domain synchronizes the new frequency division coefficient to the divider by collecting the update signal;

[0007] 4. configuring the update to be 0 to complete the configuration operation. If the frequency division coefficient needs to be changed again, the above steps 1-4 are repeated.

[0008] However, the above configuration operation process is complicated, and only one-way handshake is used when synchronizing the frequency division coefficient to the asynchronous clock domain, which has poor reliability and is prone to errors.

[0009] Therefore, how to simplify the process of configuring the frequency division coefficient and improve the accuracy and reliability of configuring the frequency division coefficient has become a technical problem to be solved by those skilled in the art. SUMMARY

[0010] In view of the above, the present application provides a method and device for configuring an asynchronous clock divider, equipment and storage medium, which aims to solve the above technical problems.

[0011] In a first aspect, the present application provides a method for configuring an asynchronous clock divider, which comprises:

[0012] configuring the frequency division coefficient of the asynchronous clock divider and calculating the first check code of the frequency division coefficient;

[0013] determining whether the frequency division coefficient is consistent with a current frequency division coefficient of the asynchronous clock divider, if not, generating a request signal for changing the frequency division coefficient of the asynchronous clock divider, and sending the frequency division coefficient and the first check code to the asynchronous clock divider;

[0014] controlling the asynchronous clock divider to perform a check operation on the first check code, and if the check passes, updating the current frequency division coefficient of the asynchronous clock divider according to the frequency division coefficient.

[0015] Preferably, the method further comprises:

[0016] If the check fails, generating information reporting a configuration exception to a master chip, and re-executing the step of configuring the frequency division coefficient of the asynchronous clock divider to the step of controlling the asynchronous clock divider to perform a check operation on the first check code.

[0017] Preferably, the method further comprises:

[0018] calculating the first check code of the frequency division coefficient by using a parity check algorithm.

[0019] Preferably, before generating the request for changing the frequency division coefficient of the asynchronous clock divider, the method further comprises:

[0020] splicing and combining the first check code and the frequency division coefficient to obtain combined information;

[0021] The step of sending the frequency division coefficient and the first check code to the asynchronous clock divider comprises:

[0022] sending the combined information to the asynchronous clock divider.

[0023] Preferably, the step of determining whether the frequency division coefficient is consistent with the current frequency division coefficient of the asynchronous clock divider further comprises:

[0024] when determining that the frequency division coefficient is consistent with the current frequency division coefficient of the asynchronous clock divider, refusing to generate the request signal for changing the frequency division coefficient of the asynchronous clock divider.

[0025] Preferably, the step of controlling the asynchronous clock divider to perform a check operation on the first check code comprises:

[0026] controlling the asynchronous clock divider to collect the first check code and the frequency division coefficient, and calculating a second check code of the frequency division coefficient;

[0027] determining whether check bits of the first check code and the second check code are consistent;

[0028] If it is judged that the check bits of the first check code and the second check code are consistent, the check is passed.

[0029] If it is judged that the check bits of the first check code and the second check code are inconsistent, the check is failed.

[0030] Preferably, after updating the current division factor of the asynchronous clock divider according to the division factor, the method further comprises:

[0031] Sending a signal of success of the division factor update to a master chip.

[0032] In a second aspect, the application provides an apparatus for configuring an asynchronous clock divider, which comprises:

[0033] A configuration module, configured to configure a division factor of the asynchronous clock divider and calculate a first check code of the division factor;

[0034] A sending module, configured to judge whether the division factor is consistent with a current division factor of the asynchronous clock divider, if not, generate a request signal for changing the division factor of the asynchronous clock divider, and send the division factor and the first check code to the asynchronous clock divider;

[0035] An updating module, configured to control the asynchronous clock divider to perform a check operation on the first check code, and if the check is passed, update the current division factor of the asynchronous clock divider according to the division factor.

[0036] In a third aspect, the application provides an electronic device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus.

[0037] The memory is configured to store a computer program.

[0038] The processor is configured to execute the program stored on the memory, and realize the steps of the method for configuring the asynchronous clock divider according to any one of the first aspect.

[0039] In a fourth aspect, a computer readable storage medium is provided, which stores a computer program, and the computer program is executed by a processor to realize the steps of the method for configuring the asynchronous clock divider according to any one of the first aspect.

[0040] The above technical solution provided by the embodiments of the application has the following advantages compared with the prior art:

[0041] The method, device, equipment and storage medium for configuring an asynchronous clock divider provided in the application can realize the function of updating the frequency division factor of the asynchronous clock divider by only configuring the frequency division factor, simplify the process of configuring the asynchronous clock divider, and can realize automatic updating of the frequency division factor of the asynchronous clock divider when the configured frequency division factor is inconsistent with the current frequency division factor of the asynchronous clock divider, thereby solving the problem of low reliability caused by complicated operation in the prior art when configuring the asynchronous clock divider, and avoiding the occurrence of clock abnormality caused by incorrect operation of an engineer when configuring the frequency division factor. The check code of the frequency division factor is calculated when configuring the frequency division factor, and the frequency division factor is checked when the asynchronous clock divider collects the frequency division factor, so that the frequency division factor can be correctly transmitted to the asynchronous clock divider, and the reliability and robustness of the chip clock system are improved. BRIEF DESCRIPTION OF DRAWINGS

[0042] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application.

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

[0044] Figure 1 The flowchart schematic diagram of the preferred embodiment of the method for configuring an asynchronous clock divider of the application;

[0045] Figure 2 The module schematic diagram of the preferred embodiment of the device for configuring an asynchronous clock divider of the application;

[0046] Figure 3 The schematic diagram of the preferred embodiment of the electronic equipment of the application;

[0047] The implementation, functional features and advantages of the application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the application more clear, the application will be further described in detail with reference to the embodiments and the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the application, and are not used to limit the application. Based on the embodiments in the application, all other embodiments obtained by those of ordinary skill in the art without any creative effort fall within the scope of the application.

[0049] It should be noted that the descriptions involving "first", "second", etc. in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the fact that a person skilled in the art can realize it, and when the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist and is not within the protection scope required by the present application.

[0050] The present application provides a method for configuring an asynchronous clock divider. Referring to Figure 1 The method flow diagram of the embodiment of the method for configuring an asynchronous clock divider of the present application is shown. The method can be executed by an electronic device, which can be realized by software and / or hardware. The method for configuring an asynchronous clock divider comprises:

[0051] Step S10: configuring a frequency division coefficient of the asynchronous clock divider, and calculating a first check code of the frequency division coefficient;

[0052] Step S20: determining whether the frequency division coefficient is consistent with the current frequency division coefficient of the asynchronous clock divider, if not, generating a request signal for changing the frequency division coefficient of the asynchronous clock divider, and sending the frequency division coefficient and the first check code to the asynchronous clock divider;

[0053] Step S30: controlling the asynchronous clock divider to perform a check operation on the first check code, and if the check is passed, updating the current frequency division coefficient of the asynchronous clock divider according to the frequency division coefficient.

[0054] In the embodiment, the asynchronous clock divider refers to the clock divider of the asynchronous clock domain. When the master chip (for example, CPU) configures the frequency division coefficient of the asynchronous clock divider, the first check code of the configured frequency division coefficient is calculated. The first check code is used to verify whether the transmission error occurs in the transmission process of the frequency division coefficient when the frequency division coefficient is sent to the asynchronous clock divider in the subsequent process. The first check code can be a CRC check code, and the CRC encoding operation is performed on the frequency division coefficient to obtain the CRC check code of the frequency division coefficient. The CRC (Cyclic Redundancy Check, cyclic redundancy check code) is a commonly used error check code in data communication. The method for realizing the check by using CRC is that a CRC code for check of R bits is generated according to K-bit binary code data to be transmitted at the data sending end according to a certain rule, and a new binary code data of K+R bits is sent out. The data receiving end follows the same rule to perform the check to determine whether an error occurs in the transmission process.

[0055] Further, the first check code can also be calculated by using a parity algorithm. The parity is a process of ensuring accurate data transmission between nodes in a communication process. Parity bits are added to the original data bits to create even or odd bits. The smallest unit in memory is a bit, also known as a bit, which has only two states, represented by 1 and 0. Memory without parity has only 8 bits per byte, and if a bit stores an incorrect value, it will cause the corresponding data stored to change, and thus cause the program to have an error.

[0056] After calculating the first check code of the frequency division coefficient, it is determined whether the configured frequency division coefficient is consistent with the current frequency division coefficient of the asynchronous clock divider. If the configured frequency division coefficient is not consistent with the current frequency division coefficient of the asynchronous clock divider, a request signal for changing the frequency division coefficient of the asynchronous clock divider can be automatically generated, and the frequency division coefficient and the first check code are sent to the asynchronous clock divider. For example, the frequency division coefficient configured by the master chip is 10, and the current frequency division coefficient of the asynchronous clock divider is 5. Since 10 and 5 are different, a request signal for changing the frequency division coefficient can be generated, and the frequency division coefficient and the first check code of the frequency division coefficient are sent to the asynchronous clock divider. Further, if it is determined that the configured frequency division coefficient is consistent with the current frequency division coefficient of the asynchronous clock divider, the request signal for changing the frequency division coefficient of the asynchronous clock divider is refused, i.e., the current frequency division coefficient of the asynchronous clock divider is not updated.

[0057] After the asynchronous clock divider collects the request signal for changing the frequency division coefficient, the asynchronous clock divider starts to collect the frequency division coefficient and the first check code of the frequency division coefficient. After the asynchronous clock divider collects the frequency division coefficient and the first check code of the frequency division coefficient, the asynchronous clock divider performs a check operation on the first check code. For example, if the first check code is a CRC check code, the remainder of the first check code can be calculated by using modulo 2 division. If the remainder of the first check code is a preset value (for example, 0), it means that the CRC check is passed. If the check is passed, it means that the frequency division coefficient has not appeared abnormal in the transmission process, and at this time, the current frequency division coefficient of the asynchronous clock divider can be updated according to the frequency division coefficient, i.e., the frequency division coefficient of the asynchronous clock divider is changed. For example, the frequency division coefficient configured by the master chip is 10, and the current frequency division coefficient of the asynchronous clock divider is 5. Then, the frequency division coefficient of the asynchronous clock divider is changed to 10.

[0058] Compared with the prior art, the application only needs to configure the frequency division coefficient to realize the function of updating the frequency division coefficient of the asynchronous clock divider, simplifies the configuration process of the asynchronous clock divider, generates a request signal for changing the frequency division coefficient of the asynchronous clock divider when the configured frequency division coefficient is inconsistent with the current frequency division coefficient of the asynchronous clock divider, and can automatically update the frequency division coefficient of the asynchronous clock divider, thereby solving the problem of low reliability caused by complicated operation in the prior art when configuring the asynchronous clock divider, and avoiding the situation of clock abnormality caused by incorrect operation of engineers. In addition, when configuring the frequency division coefficient, the application calculates the check code of the frequency division coefficient, and checks when the asynchronous clock divider collects the frequency division coefficient, which can ensure that the frequency division coefficient can be correctly transmitted to the asynchronous clock divider, avoid the problem of occasional errors of the frequency division coefficient in the transmission process caused by the lack of checking of the frequency division coefficient in the prior art, and improve the reliability and robustness of the chip clock system.

[0059] In one embodiment, the method further comprises:

[0060] If the verification fails, an information of configuration exception is generated and reported to the master chip, and the steps of configuring the frequency division coefficient of the asynchronous clock divider to control the asynchronous clock divider to perform the verification operation on the first check code are re-executed.

[0061] After the asynchronous clock divider collects the frequency division coefficient and the first check code of the frequency division coefficient, the asynchronous clock divider performs the verification operation on the first check code. If the verification fails, it indicates that the frequency division coefficient has an exception or error in the transmission process. At this time, an information of configuration exception can be generated and reported to the master chip, and the master chip is notified to reconfigure the frequency division coefficient of the asynchronous clock divider, i.e. to re-execute the above steps S10 to S30. The frequency division coefficient with configuration error can be avoided to be configured to the asynchronous clock divider. Further, if the verification fails for a continuous preset number of times (for example, 3 times), an information of configuration failure is generated and reported to the master chip.

[0062] In one embodiment, before generating the request for changing the frequency division coefficient of the asynchronous clock divider, the method further comprises:

[0063] Combining the first check code and the frequency division coefficient to obtain combined information.

[0064] Before generating the request of changing the division factor of the asynchronous clock divider, the division factor and the first check code corresponding to the division factor can be combined to obtain combination information. For example, the division factor configured by the master chip and the check code of the division factor are spliced and combined, or are placed in the same packet for transmission. Further, the sending of the division factor and the first check code to the asynchronous clock divider includes: sending the combination information to the asynchronous clock divider. Thus, the number of data transmission times is reduced.

[0065] In one embodiment, the control of the asynchronous clock divider to perform the check operation on the first check code includes:

[0066] The control of the asynchronous clock divider to collect the first check code and the division factor and to calculate a second check code of the division factor;

[0067] The judgment of whether the check bits of the first check code and the second check code are consistent;

[0068] If it is judged that the check bits of the first check code and the second check code are consistent, the check is passed.

[0069] If it is judged that the check bits of the first check code and the second check code are inconsistent, the check is failed.

[0070] After the asynchronous clock divider collects the division factor configured by the master chip and the first check code of the division factor, the asynchronous clock divider can calculate a second check code of the division factor, judge whether the check bits of the first check code and the second check code are consistent, and if the check bits of the first check code and the second check code are consistent, the check is passed. If it is judged that the check bits of the first check code and the second check code are inconsistent, the check is failed.

[0071] It can be understood that if the first check code is obtained by the CRC encoding operation on the division factor configured by the master chip, the second check code is obtained by the CRC encoding operation on the division factor collected by the asynchronous clock divider, if the first check code is obtained by the parity check operation on the division factor configured by the master chip, the second check code is obtained by the parity check operation on the division factor collected by the asynchronous clock divider.

[0072] In one embodiment, after updating the current division factor of the asynchronous clock divider according to the division factor, the method further includes:

[0073] Sending a signal of successful division factor update to the master chip.

[0074] After updating the current division factor of the asynchronous clock divider according to the division factor configured by the master chip, a signal of successful division factor update can be further sent to the master chip to notify the master chip that the division factor has been successfully configured.

[0075] Referring to Figure 2 Fig. 1 is a schematic diagram of functional modules of an apparatus 100 for configuring an asynchronous clock divider according to an embodiment of the present application.

[0076] The apparatus 100 for configuring an asynchronous clock divider according to the present application can be installed in an electronic device. According to the functions implemented, the apparatus 100 for configuring an asynchronous clock divider can include a configuration module 110, a sending module 120, and an updating module 130. The modules according to the present application can also be referred to as units, which refer to a series of computer program segments that can be executed by a processor of an electronic device and can complete a fixed function, and are stored in a memory of the electronic device.

[0077] In the present embodiment, the functions of the modules / units are as follows:

[0078] The configuration module 110 is configured to configure a division factor of an asynchronous clock divider, and calculate a first check code of the division factor.

[0079] The sending module 120 is configured to determine whether the division factor is consistent with a current division factor of the asynchronous clock divider, and if not, generate a request signal for changing the division factor of the asynchronous clock divider, and send the division factor and the first check code to the asynchronous clock divider.

[0080] The updating module 130 is configured to control the asynchronous clock divider to perform a check operation on the first check code, and if the check passes, update the current division factor of the asynchronous clock divider according to the division factor.

[0081] In one embodiment, the apparatus for configuring an asynchronous clock divider further includes a reporting module 140, which is configured to:

[0082] If the check does not pass, generate information about a configuration exception and report it to a master chip, and re-execute the steps of configuring the division factor of the asynchronous clock divider to control the asynchronous clock divider to perform the check operation on the first check code.

[0083] In one embodiment, the calculation of the first check code of the division factor includes:

[0084] The first check code of the division factor is calculated using a parity check algorithm.

[0085] In one embodiment, the sending module 120 is further configured to:

[0086] The first check code and the division factor are spliced and combined to obtain combined information.

[0087] The sending of the frequency division coefficient and the first check code to the asynchronous clock divider includes:

[0088] The sending of the combination information to the asynchronous clock divider.

[0089] In one embodiment, the judging of whether the frequency division coefficient is consistent with the current frequency division coefficient of the asynchronous clock divider further includes:

[0090] When it is judged that the frequency division coefficient is consistent with the current frequency division coefficient of the asynchronous clock divider, the request signal for changing the frequency division coefficient of the asynchronous clock divider is refused to be generated.

[0091] In one embodiment, the controlling of the asynchronous clock divider to perform the check operation on the first check code includes:

[0092] The controlling of the asynchronous clock divider to collect the first check code and the frequency division coefficient and to calculate a second check code of the frequency division coefficient;

[0093] The judging of whether the check bits of the first check code and the second check code are consistent;

[0094] If it is judged that the check bits of the first check code and the second check code are consistent, the check is passed;

[0095] If it is judged that the check bits of the first check code and the second check code are inconsistent, the check is failed.

[0096] In one embodiment, the updating module 130 is further configured to:

[0097] The updating module 130 is further configured to send a signal of success of the frequency division coefficient update to the master control chip.

[0098] Referring to Figure 3 FIG. 1 shows a schematic diagram of a preferred embodiment of an electronic device 1 according to the present application.

[0099] The electronic device 1 includes but is not limited to a memory 11, a processor 12, a display 13, and a communication interface 14. The electronic device 1 can be connected to a network through the communication interface 14. The network can be an Intranet, the Internet, a Global System of Mobile communication (GSM), a Wideband Code Division Multiple Access (WCDMA), a 4G network, a 5G network, Bluetooth, Wi-Fi, a call network, and the like.

[0100] The memory 11 includes at least one type of readable storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory (e.g., SD or DX memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, an optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the electronic device 1, such as a hard disk or a memory of the electronic device 1. In other embodiments, the memory 11 can also be an external storage device of the electronic device 1, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped with the electronic device 1. Of course, the memory 11 can also include both the internal storage unit and the external storage device of the electronic device 1. In this embodiment, the memory 11 is generally used to store an operating system and various application software installed in the electronic device 1, such as program codes of the program 10 for configuring an asynchronous clock divider, etc. In addition, the memory 11 can also be used to temporarily store various data that have been output or will be output.

[0101] The processor 12 can be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chip in some embodiments. The processor 12 is generally used to control the overall operation of the electronic device 1, such as performing control and processing related to data interaction or communication, etc. In this embodiment, the processor 12 is used to run program codes or process data stored in the memory 11, such as running program codes of the program 10 for configuring an asynchronous clock divider, etc.

[0102] The display 13 can be referred to as a display screen or a display unit. In some embodiments, the display 13 can be an LED display, a liquid crystal display, a touch liquid crystal display, an organic light-emitting diode (OLED) touch, etc. The display 13 is used to display information processed in the electronic device 1 and to display a visualized work interface.

[0103] The communication interface 14 can optionally include a standard wired interface, a wireless interface (such as a WI-FI interface), etc. The communication interface 14 is generally used to establish a communication connection between the electronic device 1 and other electronic devices.

[0104] Figure 3Only the electronic device 1 with the components 11-14 and the program 10 for configuring the asynchronous clock divider is shown, but it is understood that it is not required to implement all the shown components, and more or less components can be alternatively implemented.

[0105] In the above embodiment, the processor 12 implements the following steps when executing the program 10 for configuring the asynchronous clock divider stored in the memory 11:

[0106] configuring a division factor of the asynchronous clock divider, calculating a first check code of the division factor;

[0107] determining whether the division factor is consistent with a current division factor of the asynchronous clock divider, if not, generating a request signal for changing the division factor of the asynchronous clock divider, and sending the division factor and the first check code to the asynchronous clock divider;

[0108] controlling the asynchronous clock divider to perform a check operation on the first check code, and if the check passes, updating the current division factor of the asynchronous clock divider according to the division factor.

[0109] The storage device can be the memory 11 of the electronic device 1, or other storage device in communication connection with the electronic device 1.

[0110] For detailed introduction of the above steps, please refer to the above Figure 2 For the function module diagram of the embodiment of the apparatus 100 for configuring the asynchronous clock divider and Figure 1 For the flow chart of the embodiment of the method for configuring the asynchronous clock divider.

[0111] In addition, the embodiment of the present application further proposes a computer readable storage medium, which can be non-volatile or volatile. The computer readable storage medium can be any one or any combination of a hard disk, a multimedia card, an SD card, a flash memory card, an SMC, a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disc read-only memory (CD-ROM), a USB memory, etc. The computer readable storage medium includes a storage data area and a storage program area, and the storage program area stores the program 10 for configuring the asynchronous clock divider, which is executed by the processor to implement the following operations:

[0112] configuring a division factor of the asynchronous clock divider, calculating a first check code of the division factor;

[0113] determining whether the frequency division coefficient is consistent with a current frequency division coefficient of the asynchronous clock divider, and if not, generating a request signal for changing the frequency division coefficient of the asynchronous clock divider, and sending the frequency division coefficient and the first check code to the asynchronous clock divider;

[0114] controlling the asynchronous clock divider to perform a check operation on the first check code, and if the check passes, updating the current frequency division coefficient of the asynchronous clock divider according to the frequency division coefficient.

[0115] The specific implementation of the computer readable storage medium of the present application is substantially the same as that of the above-mentioned method for configuring an asynchronous clock divider, and will not be described here.

[0116] It should be noted that the above-mentioned sequence numbers of the embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments. Moreover, the terms "include", "contain" or any other variant thereof in the present text are intended to cover non-exclusive inclusion, so that the process, device, article or method including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, device, article or method. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, device, article or method including the element.

[0117] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment method can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes a plurality of instructions for making a terminal device (which can be a mobile phone, computer, electronic device, or network device, etc.) execute the method described in each embodiment of the present application.

[0118] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method of configuring an asynchronous clock divider, the method comprising: The method comprises: configuring a frequency division factor of an asynchronous clock divider, calculating a first check code of the frequency division factor; determining whether the frequency division factor is consistent with a current frequency division factor of the asynchronous clock divider, if not, generating a request signal for changing the frequency division factor of the asynchronous clock divider, and sending the frequency division factor and the first check code to the asynchronous clock divider; controlling the asynchronous clock divider to perform a check operation on the first check code, if the check passes, updating the current frequency division factor of the asynchronous clock divider according to the frequency division factor, wherein the first check code is used to verify whether a transmission error occurs in the frequency division factor during transmission when a subsequent frequency division factor is sent to the asynchronous clock divider.

2. The method of configuring an asynchronous clock divider as recited in claim 1, wherein, The method further comprises: if the check does not pass, generating information of configuration exception and reporting to a master control chip, and re-executing the steps of configuring the frequency division factor of the asynchronous clock divider to controlling the asynchronous clock divider to perform the check operation on the first check code.

3. The method of configuring an asynchronous clock divider as recited in claim 1, wherein, The calculation of the first check code of the frequency division factor comprises: calculating the first check code of the frequency division factor by using a parity check algorithm.

4. The method of configuring an asynchronous clock divider as recited in claim 1, wherein, Before generating the request for changing the frequency division factor of the asynchronous clock divider, the method further comprises: splicing and combining the first check code and the frequency division factor to obtain combined information; The sending of the frequency division factor and the first check code to the asynchronous clock divider comprises: sending the combined information to the asynchronous clock divider.

5. The method of configuring an asynchronous clock divider as recited in claim 1, wherein, The determination of whether the frequency division factor is consistent with the current frequency division factor of the asynchronous clock divider further comprises: when determining that the frequency division factor is consistent with the current frequency division factor of the asynchronous clock divider, refusing to generate the request signal for changing the frequency division factor of the asynchronous clock divider.

6. The method of configuring an asynchronous clock divider as recited in claim 1, wherein, The control of the asynchronous clock divider to perform the check operation on the first check code comprises: controlling the asynchronous clock divider to collect the first check code and the frequency division factor, and calculating a second check code of the frequency division factor; determining whether check bits of the first check code and the second check code are consistent; if the check bits of the first check code and the second check code are consistent, the check passes; if the check bits of the first check code and the second check code are not consistent, the check does not pass.

7. The method of configuring an asynchronous clock divider as recited in claim 1, wherein, After updating the current frequency division factor of the asynchronous clock divider according to the frequency division factor, the method further comprises: sending a signal of successful frequency division factor update to a master control chip.

8. An apparatus for configuring an asynchronous clock divider, the apparatus comprising: The device comprises: a configuration module configured to configure a frequency division factor of an asynchronous clock divider, and calculate a first check code of the frequency division factor; a sending module configured to determine whether the frequency division factor is consistent with a current frequency division factor of the asynchronous clock divider, if not, generate a request signal for changing the frequency division factor of the asynchronous clock divider, and send the frequency division factor and the first check code to the asynchronous clock divider; The updating module is configured to control the asynchronous clock divider to perform a check operation on the first check code, and if the check passes, update the current division factor of the asynchronous clock divider according to the division factor, wherein the first check code is used to verify whether a transmission error occurs in the transmission of the division factor to the asynchronous clock divider.

9. An electronic device, comprising: The computer device comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; The memory is configured to store a computer program. The processor is configured to execute the program stored in the memory, and implement the method for configuring the asynchronous clock divider according to any one of claims 1 to 7.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method for configuring the asynchronous clock divider according to any one of claims 1 to 7.

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