A chip initialization method and system, a chip and a readable storage medium

Abstract

The application discloses a chip initialization method and system, a chip and a readable storage medium. The initialization method comprises the following steps: acquiring a mode selection signal; and executing a chip initialization strategy according to the mode selection signal. The test initialization strategy comprises the following steps: sequentially writing a plurality of preset test trimming data into a trimming register module from outside; trimming a to-be-trimmed module according to each test trimming data, and obtaining a plurality of trimming results one by one; selecting target trimming data from the plurality of test trimming data according to the plurality of trimming results; and writing the target trimming data into a storage unit through a processing unit. The non-test initialization strategy comprises the following steps: reading the target trimming data from the storage unit to the trimming register module through a data loading circuit; and trimming the to-be-trimmed module according to the target trimming data. The initialization method can improve the stability of the system and reduce the operation load of the CPU.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a chip initialization method, system, chip, and readable storage medium. Background Technology

[0002] In System-on-Chip (SOC) design, due to the influence of process parameters or environment, some components (such as oscillators (OSC), phase-locked loops (PLLs), and digital-to-analog converters (ADCs)) incorporate a trimming method to improve their performance after tape-out. This involves loading trimming values ​​into relevant registers during chip usage, thereby trimming the modules to be trimmed. Loading these registers is a crucial part of chip initialization.

[0003] Current chip initialization methods are implemented in software. Software drives hardware to perform corresponding operations through instructions. Instruction execution requires instruction fetching, instruction decoding, and instruction execution; even a simple register load instruction can consume significant CPU resources. Furthermore, with significant process variations, the more complex the initialization of critical modules (such as OSC and PLL), the more unstable the chip clock may become. The system might enter an illegal state during the instruction fetching and decoding phases, posing a risk to system operation. Additionally, if chip initialization is entirely performed in hardware, the chip area increases, raising chip development costs. Summary of the Invention

[0004] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a chip initialization method that can improve system stability and reduce the CPU's operating load.

[0005] The present invention also provides a chip initialization system, a chip, and a computer-readable storage medium.

[0006] According to a first aspect of the present invention, a chip initialization method is provided, wherein the chip includes a trimming module, a trimming register module, a storage unit, a processing unit, and a data loading circuit; the initialization method includes the following steps:

[0007] Acquire mode selection signal;

[0008] The chip initialization strategy is executed according to the mode selection signal, and the chip initialization strategy includes a test initialization strategy and a non-test initialization strategy.

[0009] The test initialization strategy includes the following steps: sequentially writing multiple preset test adjustment data into the adjustment register module from an external source; adjusting the module to be adjusted according to each test adjustment data to obtain multiple adjustment results; selecting target adjustment data from the multiple test adjustment data according to the multiple adjustment results; and writing the target adjustment data into the storage unit through the processing unit.

[0010] The non-test initialization strategy includes the following steps: reading the target adjustment data from the storage unit into the adjustment register module through the data loading circuit; and adjusting the module to be adjusted according to the target adjustment data.

[0011] The initialization method according to embodiments of the present invention has at least the following beneficial effects:

[0012] By acquiring the mode selection signal, it can be determined whether the chip is in the testing phase. If the mode selection signal indicates that the chip is in the testing phase, a test initialization strategy is executed. Multiple preset test tuning data are sequentially written from the outside into the tuning register module. The module to be tuned is tuned according to each test tuning data, and target tuning data is selected from the multiple test tuning data. Then, the target tuning data is written into the storage unit through the processing unit. If the mode selection signal indicates that the chip is not in the testing phase, a non-test initialization strategy is executed. The target tuning data is directly read from the storage unit into the tuning register module through the data loading circuit, and the module to be tuned is tuned according to the target tuning data. Using the data loading circuit to load the target tuning data reduces the CPU's operating load, and the loading of the target tuning data can be completed within one clock cycle, improving system stability. The initialization method of this embodiment of the invention uses a combination of hardware and software to implement the chip initialization process, which can improve system stability and reduce the CPU's operating load.

[0013] According to some embodiments of the present invention, writing the target adjustment data into the storage unit through the processing unit includes the following steps:

[0014] Obtain the preset target address region in the storage unit;

[0015] The processing unit writes the target adjustment data into the target address area.

[0016] According to some embodiments of the present invention, the data loading circuit includes a reset signal detection circuit, an address memory, and a read enable circuit, wherein the read enable circuit is connected to the reset signal detection circuit and the address memory, respectively.

[0017] The step of reading the target trimming data from the storage unit into the trimming register module through the data loading circuit includes the following steps:

[0018] Obtain the preset target address region in the storage unit;

[0019] The address information of the target address region is read into the address memory;

[0020] If the reset signal detection circuit detects the reset signal, the read enable circuit reads the target adjustment data from the target address region into the adjustment register module according to the address information, so that the module to be adjusted can be adjusted according to the target adjustment data.

[0021] According to some embodiments of the present invention, the step of reading the target trimming data from the target address region into the trimming register module based on the address information through the read enable circuit includes the following steps:

[0022] The read enable circuit generates a read enable control signal based on the address information.

[0023] The read enable control signal is sent to the storage unit to read the target trimming data from the target address region into the trimming register module.

[0024] According to some embodiments of the present invention, the step of executing the chip initialization strategy based on the mode selection signal includes the following steps:

[0025] If the mode selection signal indicates that the chip is in the testing phase, the test initialization strategy is executed.

[0026] If the mode selection signal indicates that the chip is in a non-test phase, the non-test initialization strategy is executed.

[0027] A chip initialization system according to a second aspect embodiment of the present invention includes:

[0028] The mode selection signal acquisition unit is used to acquire the mode selection signal;

[0029] A chip initialization strategy execution unit is used to execute a chip initialization strategy according to the mode selection signal. The chip initialization strategy includes a test initialization strategy and a non-test initialization strategy. The test initialization strategy includes the following steps: sequentially writing multiple preset test tuning data from an external source into the tuning register module; tuning the module to be tuned according to each test tuning data, obtaining multiple tuning results; selecting target tuning data from the multiple test tuning data based on the multiple tuning results; and writing the target tuning data into the storage unit through the processing unit. The non-test initialization strategy includes the following steps: reading the target tuning data from the storage unit into the tuning register module through the data loading circuit; and tuning the module to be tuned according to the target tuning data.

[0030] The initialization system according to embodiments of the present invention has at least the following beneficial effects:

[0031] The mode selection signal is acquired by the mode selection signal acquisition unit to determine whether the chip is in the testing phase. Then, the chip initialization strategy execution unit selects to execute either a test initialization strategy or a non-test initialization strategy based on the mode selection signal. If the mode selection signal indicates the chip is in the testing phase, the test initialization strategy is executed. Multiple preset test tuning data are sequentially written from the outside into the tuning register module. The module to be tuned is tuned according to each test tuning data, and target tuning data is selected from the multiple test tuning data. The processing unit then writes the target tuning data into the storage unit. If the mode selection signal indicates the chip is not in the testing phase, the non-test initialization strategy is executed. The target tuning data is directly read from the storage unit into the tuning register module via the data loading circuit, and the module to be tuned is tuned according to the target tuning data. Using the data loading circuit to load the target tuning data reduces the CPU's operating load, and the loading of the target tuning data can be completed within one clock cycle, improving system stability. This embodiment of the invention uses a hardware and software combination to implement the chip initialization process, which can improve system stability and reduce the CPU's operating load.

[0032] A chip according to a third aspect embodiment of the present invention includes:

[0033] Modules to be repaired / adjusted;

[0034] A repair register module is connected to the module to be repaired;

[0035] Storage unit;

[0036] The selector has a first selection terminal, a second selection terminal, an output terminal, and a control terminal. The first selection terminal is used to sequentially input multiple preset test and adjustment data written externally. The output terminal is connected to the adjustment register module.

[0037] The processing unit is used to acquire a mode selection signal and output the mode selection signal to the control terminal, and to adjust the module to be adjusted according to each test adjustment data, to obtain multiple adjustment results in a one-to-one correspondence, to select target adjustment data from multiple test adjustment data according to multiple adjustment results, and to write the target adjustment data into the storage unit.

[0038] A data loading circuit is connected to the second selection terminal and the processing unit respectively. The data loading circuit is used to read the target adjustment data from the storage unit to the second selection terminal, so as to transmit the target adjustment data to the adjustment register module, thereby adjusting the module to be adjusted according to the target adjustment data.

[0039] The chip according to embodiments of the present invention has at least the following beneficial effects:

[0040] The processing unit can acquire a mode selection signal to determine whether the chip is in the testing phase. If the mode selection signal indicates that the chip is in the testing phase, multiple preset test tuning data are sequentially written from the outside into the tuning register module through the first selection terminal of the selector. The module to be tuned is tuned according to each test tuning data. Target tuning data is selected from the multiple test tuning data, and then the processing unit writes the target tuning data into the storage unit. If the mode selection signal indicates that the chip is not in the testing phase, the target tuning data is directly read from the storage unit to the second selection terminal of the selector through the data loading circuit, and then output to the tuning register module. Finally, the module to be tuned is tuned according to the target tuning data. Using the data loading circuit to load the target tuning data reduces the CPU's operating load, and the loading of the target tuning data can be completed within one clock cycle, improving system stability. The chip in this embodiment of the invention implements the chip initialization process through a combination of hardware and software, which can improve system stability and reduce the CPU's operating load.

[0041] According to some embodiments of the present invention, the storage unit includes a target address region for storing the target adjustment data; the data loading circuit includes:

[0042] Reset signal detection circuit, used to detect reset signal;

[0043] An address storage device is used to store the address information of the target address region;

[0044] The read enable circuit is used to read the target adjustment data from the target address region to the second selection terminal according to the address information after the reset signal detection circuit detects the reset signal, so as to transmit the target adjustment data to the adjustment register module, thereby adjusting the module to be adjusted according to the target adjustment data.

[0045] According to some embodiments of the present invention, the adjustment register module includes a plurality of adjustment registers, which together are used to improve the adjustment accuracy of the module to be adjusted.

[0046] According to a fourth aspect embodiment of the present invention, a computer-readable storage medium stores computer-executable instructions for performing the initialization method as described in the first aspect embodiment. Since the computer-readable storage medium employs all the technical solutions of the initialization method of the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments.

[0047] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. Attached Figure Description

[0048] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0049] Figure 1 This is an electrical schematic diagram of the chip according to an embodiment of the present invention;

[0050] Figure 2 This is a flowchart of the initialization method according to an embodiment of the present invention.

[0051] Figure label:

[0052] 100 modules to be repaired;

[0053] Adjust and modify the register module 200;

[0054] Storage unit 300;

[0055] Selector 400;

[0056] Processing unit 500;

[0057] Data loading circuit 600. Detailed Implementation

[0058] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0059] In the description of this invention, the use of terms such as "first," "second," etc., is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or implicitly indicating the order of the technical features indicated.

[0060] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the drawings and are only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0061] In the description of this invention, it should be noted that, unless otherwise explicitly defined, terms such as "setting," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0062] To better illustrate the initialization method of the embodiments of the present invention, the concept of adjustment will be briefly explained first.

[0063] For example, a chip may have an embedded FLASH memory with a 0.8V voltage reference. This voltage reference corresponds to a 3-bit register. When the chip powers on, the register's default value of 000 corresponds to 0.8V. However, due to manufacturing process variations, the default value of 000 may not actually correspond to 0.8V; instead, it may deviate from 0.8V. Therefore, we need to reconfigure the corresponding register to adjust the voltage reference value to 0.8V. It should be noted that the specific parameters described above are for illustrative purposes only and should not be considered as limiting the scope of this invention.

[0064] This invention provides a chip including a trimming module 100, a trimming register module 200, a storage unit 300, a selector 400, a processing unit 500, and a data loading circuit 600. The tuning register module 200 is connected to the tuning module 100; the selector 400 has a first selection terminal, a second selection terminal, an output terminal, and a control terminal. The first selection terminal is used to sequentially input multiple preset test tuning data written externally, and the output terminal is connected to the tuning register module 200; the processing unit 500 is used to acquire a mode selection signal and output the mode selection signal to the control terminal, and to tune the tuning module 100 according to each test tuning data, obtaining multiple tuning results one-to-one, selecting target tuning data from the multiple test tuning data according to the multiple tuning results, and writing the target tuning data into the storage unit 300; the data loading circuit 600 is connected to the second selection terminal and the processing unit 500 respectively. The data loading circuit 600 is used to read the target tuning data from the storage unit 300 to the second selection terminal, so as to transmit the target tuning data to the tuning register module 200, thereby tuning the tuning module 100 according to the target tuning data.

[0065] The following will combine Figure 1 and Figure 2 The initialization method of the embodiments of the present invention will be clearly and completely described below. Obviously, the embodiments described below are some embodiments of the present invention, not all embodiments.

[0066] According to a first aspect of the present invention, the chip includes a trimming module 100, a trimming register module 200, a storage unit 300, a processing unit 500, and a data loading circuit 600; the initialization method includes the following steps:

[0067] Acquire mode selection signal;

[0068] The chip initialization strategy is executed according to the mode selection signal. The chip initialization strategy includes a test initialization strategy and a non-test initialization strategy.

[0069] The test initialization strategy includes the following steps: sequentially writing multiple preset test adjustment data into the adjustment register module 200 from the outside; adjusting the module 100 to be adjusted according to each test adjustment data, obtaining multiple adjustment results one by one; selecting target adjustment data from the multiple test adjustment data according to the multiple adjustment results; and writing the target adjustment data into the storage unit 300 through the processing unit 500.

[0070] The non-test initialization strategy includes the following steps: reading the target adjustment data from the storage unit 300 into the adjustment register module 200 through the data loading circuit 600; and adjusting the module 100 to be adjusted according to the target adjustment data.

[0071] Storage cell 300 is a FLASH memory, which can erase, write, and reprogram memory cell blocks, and can retain data for a long time without a current supply. The FLASH memory includes two types of areas: a main array, used as program space, and a non-volatile register (NVR) area, used to record frequently used register data. The FLASH memory has multiple interfaces, all used for enabling operations. During the testing phase, the target trimming data is stored in the NVR area of ​​the FLASH memory. This allows the chip to directly load the target trimming data stored in the FLASH memory into the trimming register module 200 during non-testing phases, enabling the trimming module 100 to be trimmed according to the target trimming data. It should be noted that storage cell 300 can also use other storage devices that can achieve the same function, and this should not be considered a limitation of the invention.

[0072] The selector 400 has a first selection terminal, a second selection terminal, an output terminal, and a control terminal. The control terminal receives a mode selection signal to select whether the chip is in the testing phase. The mode selection signal is in high / low level form. When the mode selection signal is high, it indicates that the chip is in the testing phase. The selector 400 selects an external I / O (first selection terminal) to directly serially write to the trimming register module 200. By traversing all test trimming data, the most suitable data is selected as the target trimming data, and the target trimming data is recorded in a designated non-volatile register area of ​​the FLASH memory. When the mode selection signal is low, it indicates that the chip is not in the testing phase. The selector 400 selects the target trimming data output from the data loading circuit 600 (second selection terminal) to write to the trimming register module 200, so as to trim the trimming module 100 according to the target trimming data. It should be noted that, alternatively, the mode selection signal can be high to indicate that the chip is not in the testing phase, and low to indicate that the chip is in the testing phase. The mode selection signal can also take other forms, as long as it can distinguish between the two states, and should not be regarded as a limitation on the invention.

[0073] The data loading circuit 600 includes a reset signal detection circuit, an address memory, and a read enable circuit. The reset signal detection circuit detects the chip's reset signal. The address memory stores address information for a target address region, which is a pre-defined non-volatile register region of the FLASH memory, used to store target adjustment data. The read enable circuit, upon detecting the reset signal, reads the target adjustment data from the target address region to a second selection terminal based on the address information, transmitting the target adjustment data to the adjustment register module 200. This allows the adjustment module 100 to be adjusted based on the target adjustment data. Each time the chip is reset and released, the read enable circuit performs a read operation on the target address region, reading the target adjustment data from the target address region to the second selection terminal. The data loading circuit 600 also includes a clock circuit, allowing the loading process of the target adjustment data to be completed within one clock cycle, improving system stability.

[0074] It should be noted that if there are multiple modules 100 to be repaired, each module 100 corresponds to one repair register module 200, one selector 400 and one data loading circuit 600. Multiple modules 100 to be repaired can use the same storage unit 300 or multiple storage units 300 corresponding to each other, which is not limited here.

[0075] According to the initialization method of this embodiment, by acquiring a mode selection signal, it can be determined whether the chip is in the testing phase. If the mode selection signal indicates that the chip is in the testing phase, a test initialization strategy is executed. Multiple preset test tuning data are sequentially written from the outside into the tuning register module 200. The tuning module 100 is tuned according to each test tuning data, and target tuning data is selected from the multiple test tuning data. Then, the processing unit 500 writes the target tuning data into the storage unit 300. If the mode selection signal indicates that the chip is not in the testing phase, a non-test initialization strategy is executed. The target tuning data is directly read from the storage unit 300 into the tuning register module 200 through the data loading circuit 600, and the tuning module 100 is tuned according to the target tuning data. Using the data loading circuit 600 to load the target tuning data reduces the CPU's operating load, and the loading of the target tuning data can be completed within one clock cycle, improving system stability. The initialization method of this embodiment uses a combination of hardware and software to implement the chip initialization process, which can improve system stability and reduce the CPU's operating load.

[0076] In some embodiments of the present invention, reference is made to Figure 1 The target adjustment data is written into the storage unit 300 by the processing unit 500, including the following steps:

[0077] Obtain the preset target address region in storage unit 300;

[0078] The target adjustment data is written to the target address area by the processing unit 500.

[0079] Storage unit 300 is a FLASH flash memory, where one address in the non-volatile register area corresponds to 36 bits of data, of which bits 16 to 19 are used to record target adjustment data. Under the premise that the voltage reference of the module to be adjusted 100 is 0.8V, during the testing phase, the target adjustment data is written to a preset target address area. In some embodiments, the target adjustment data can be written to the area at address 0x201. The written target adjustment data is bits 16 to 18 of the data in the 0x201 area. The written target adjustment data is 011, indicating that based on the current process parameters, the default output of the module to be adjusted 100 is approximately 0.65V, and an increase of 0.15V is needed to reach 0.8V. See Table 1 for the specific adjustment levels corresponding to the target adjustment data.

[0080] Table 1. Adjustment levels corresponding to target adjustment data.

[0081] 000 Initial voltage (ideally 0.8V) 001 Initial voltage +0.05V 010 Initial voltage +0.1V 011 Initial voltage +0.15V 100 Initial voltage -0.05V 101 Initial voltage -0.1V 110 Initial voltage -0.15V 111 Initial voltage -0.2V

[0082] It should be noted that the specific parameters mentioned above can be varied according to actual circumstances and should not be regarded as limitations on the present invention.

[0083] In some embodiments of the present invention, reference is made to Figure 1 The data loading circuit 600 includes a reset signal detection circuit, an address memory, and a read enable circuit, with the read enable circuit connected to both the reset signal detection circuit and the address memory. The data loading circuit 600 reads the target trimming data from the storage unit 300 into the trimming register module 200, comprising the following steps:

[0084] Obtain the preset target address region in storage unit 300;

[0085] Read the address information of the target address region into the address memory;

[0086] If the reset signal detection circuit detects a reset signal, the read enable circuit reads the target adjustment data from the target address area into the adjustment register module 200 according to the address information, so that the adjustment module 100 can be adjusted according to the target adjustment data.

[0087] The target address region is a designated non-volatile register region of the FLASH memory, used to store the target trimming data. Each time the chip is reset and released, the read enable circuit performs a read operation on the target address region, thereby reading the target trimming data into the trimming register module 200. The data loading circuit 600 also includes a clock circuit, allowing the loading process of the target trimming data to be completed within one clock cycle, improving system stability. The target trimming data is loaded immediately after the reset signal detection circuit detects the reset signal. Before this, the processing unit 500 does not perform any additional erase, programming, or continuous read operations on the FLASH memory, making the system more stable, reliable, and less prone to errors.

[0088] In some embodiments of the present invention, reference is made to Figure 1 The target trimming data is read from the target address region into the trimming register module 200 based on the address information through the read enable circuit, including the following steps:

[0089] The read enable circuit generates a read enable control signal based on the address information.

[0090] The read enable control signal is sent to the storage unit 300 to read the target trimming data from the target address area into the trimming register module 200.

[0091] The read enable control signal is used to enable the target address region of the FLASH flash memory. It is active high. If the read enable control signal is high, the read enable control signal is sent to the storage unit 300 to read the target trimming data from the target address region into the trimming register module 200.

[0092] In some embodiments of the present invention, reference is made to Figure 1 and Figure 2 The chip initialization strategy is executed according to the mode selection signal, including the following steps:

[0093] If the mode selection for the signal characterization chip is the testing phase, execute the test initialization strategy;

[0094] If the mode selection signal characterization chip is in the non-test phase, execute the non-test initialization strategy.

[0095] The mode selection signal is in high / low level form. When the mode selection signal is high, it indicates that the chip is in the test phase, and the test initialization strategy is executed. The selector 400 selects the external IO (first selection terminal) to directly serially write to the trimming register module 200. By traversing all the test trimming data, the most suitable one is selected as the target trimming data, and the target trimming data is recorded in the agreed non-volatile register area of ​​the FLASH flash memory. When the mode selection signal is low, it indicates that the chip is in the non-test phase, and the non-test initialization strategy is executed. The selector 400 selects the target trimming data output from the data loading circuit 600 (second selection terminal) to write to the trimming register module 200, so as to trim the trimming module 100 according to the target trimming data.

[0096] It should be noted that a high level mode selection signal can indicate that the chip is in a non-testing phase, while a low level mode selection signal can indicate that the chip is in a testing phase. The mode selection signal can also take other forms, as long as it can distinguish between the two states; this should not be considered a limitation of the invention.

[0097] In order to better demonstrate the advantages of the initialization method of the present invention, a specific example is given below, but the specific parameters mentioned below should not be regarded as a limitation of the present invention.

[0098] Storage unit 300 is a FLASH memory, which includes two types of areas: a main array used for program space and a non-volatile register (NVR) area used to record frequently used register data. The FLASH memory has multiple interfaces for enabling operations. Operation signals for the FLASH memory are in high / low level form, with high being active and low being inactive. The corresponding operations include read, erase, and program. Before operating the FLASH memory, the chip select signal must be obtained. A high-level chip select signal indicates that the FLASH memory is selected, and any operation on the FLASH memory must be performed when the chip select signal is active. It should be noted that the operation signals for the FLASH memory can also take other forms, as long as they can distinguish between the two states. The operation signals can also be high-inactive and low-active, which should not be considered a limitation of the invention.

[0099] Under the premise that the voltage reference of the module to be tuned 100 is 0.8V, the chip select signal is high, and the operation signal corresponding to the area at address 0x201 is high (indicating that this area is enabled), during the testing phase, the processing unit 500 sends a mode selection signal (at this time, it is high) to the selector 400, and sequentially writes multiple preset test tuning data into the tuning register module 200 through external IO. According to each test tuning data, the module to be tuned 100 is tuned, and multiple tuning results are obtained one by one. According to the multiple tuning results, the target tuning data is selected from the multiple test tuning data, and the processing unit 500 writes the target tuning data into the area at address 0x201 in the storage unit 300. The written target tuning data is bits 16 to 18 of the data in the 0x201 area. The written target tuning data is 011, indicating that based on the current process parameters, the default output of the module to be tuned 100 is about 0.65V, and it needs to be increased by 0.15V to reach 0.8V.

[0100] During the non-testing phase, the processing unit 500 sends a mode selection signal (low level at this time) to the selector 400. If the reset signal detection circuit detects a reset signal, it generates a read enable control signal (high level at this time) through the read enable circuit. At this point, the target trimming data is read from the region at address 0x201 according to the read enable control signal and output to the trimming register module 200 through the selector 400, so that the trimming module 100 can be trimmed according to the target trimming data. The loading process of the target trimming data is completed within one clock cycle, and the target trimming data is loaded immediately after the reset signal detection circuit detects the reset signal. Before this, the processing unit 500 does not perform any additional erase, programming, or continuous read operations on the FLASH memory, making the system more stable, reliable, and less prone to errors.

[0101] The following will combine Figure 1 and Figure 2 The initialization system of the present invention will be clearly and completely described below. Obviously, the embodiments described below are some embodiments of the present invention, not all embodiments.

[0102] An initialization system according to a second aspect embodiment of the present invention includes a mode selection signal acquisition unit and a chip initialization strategy execution unit. The mode selection signal acquisition unit is used to acquire a mode selection signal; the chip initialization strategy execution unit is used to execute a chip initialization strategy according to the mode selection signal. The chip initialization strategy includes a test initialization strategy and a non-test initialization strategy. The test initialization strategy includes the following steps: sequentially writing multiple preset test tuning data from an external source into a tuning register module 200; tuning the module 100 to be tuned according to each test tuning data, obtaining multiple tuning results one-to-one; selecting target tuning data from the multiple test tuning data according to the multiple tuning results; and writing the target tuning data into a storage unit 300 through a processing unit 500. The non-test initialization strategy includes the following steps: reading the target tuning data from the storage unit 300 into the tuning register module 200 through a data loading circuit 600; and tuning the module 100 to be tuned according to the target tuning data.

[0103] Storage cell 300 is a FLASH memory, which can erase, write, and reprogram memory cell blocks, and can retain data for a long time without a current supply. The FLASH memory includes two types of areas: a main array, used as program space, and a non-volatile register (NVR) area, used to record frequently used register data. The FLASH memory has multiple interfaces, all used for enabling operations. During the testing phase, the target trimming data is stored in the NVR area of ​​the FLASH memory. This allows the chip to directly load the target trimming data stored in the FLASH memory into the trimming register module 200 during non-testing phases, enabling the trimming module 100 to be trimmed according to the target trimming data. It should be noted that storage cell 300 can also use other storage devices that can achieve the same function, and this should not be considered a limitation of the invention.

[0104] The selector 400 has a first selection terminal, a second selection terminal, an output terminal, and a control terminal. The control terminal receives a mode selection signal to select whether the chip is in the testing phase. The mode selection signal is in high / low level form. When the mode selection signal is 1, it indicates that the chip is in the testing phase. The selector 400 selects an external I / O (first selection terminal) to directly serially write to the trimming register module 200. By traversing all test trimming data, the most suitable data is selected as the target trimming data, and the target trimming data is recorded in a designated non-volatile register area of ​​the FLASH memory. When the mode selection signal is 0, it indicates that the chip is not in the testing phase. The selector 400 selects the target trimming data output from the data loading circuit 600 (second selection terminal) to write to the trimming register module 200, so as to trim the trimming module 100 according to the target trimming data. It should be noted that the mode selection signal can also be 1 indicating that the chip is not in the testing phase and 0 indicating that the chip is in the testing phase; this should not be considered a limitation of the invention.

[0105] The data loading circuit 600 includes a reset signal detection circuit, an address memory, and a read enable circuit. The reset signal detection circuit detects the chip's reset signal. The address memory stores address information for a target address region, which is a pre-defined non-volatile register region of the FLASH memory, used to store target adjustment data. The read enable circuit, upon detecting the reset signal, reads the target adjustment data from the target address region to a second selection terminal based on the address information, transmitting the target adjustment data to the adjustment register module 200. This allows the adjustment module 100 to be adjusted based on the target adjustment data. Each time the chip is reset and released, the read enable circuit performs a read operation on the target address region, reading the target adjustment data from the target address region to the second selection terminal. The data loading circuit 600 also includes a clock circuit, allowing the loading process of the target adjustment data to be completed within one clock cycle, improving system stability.

[0106] According to the initialization system of this embodiment, a mode selection signal is acquired by a mode selection signal acquisition unit to determine whether the chip is in the testing phase. Then, the chip initialization strategy execution unit selects to execute a test initialization strategy or a non-test initialization strategy based on the mode selection signal. If the mode selection signal indicates that the chip is in the testing phase, the test initialization strategy is executed. Multiple preset test tuning data are sequentially written from the outside into the tuning register module 200. The tuning module 100 is tuned according to each test tuning data, and target tuning data is selected from the multiple test tuning data. Then, the processing unit 500 writes the target tuning data into the storage unit 300. If the mode selection signal indicates that the chip is not in the testing phase, the non-test initialization strategy is executed. The target tuning data is directly read from the storage unit 300 into the tuning register module 200 through the data loading circuit 600, and the tuning module 100 is tuned according to the target tuning data. Using the data loading circuit 600 to load the target tuning data reduces the CPU's operating load, and the loading of the target tuning data can be completed within one clock cycle, improving the system's stability. The initialization system of this invention adopts a combination of hardware and software to realize the chip initialization process, which can improve the stability of the system and reduce the CPU's operating load.

[0107] The following will combine Figure 1 and Figure 2 The chip of the present invention will be clearly and completely described below. Obviously, the embodiments described below are some embodiments of the present invention, not all embodiments.

[0108] According to a third aspect of the present invention, the chip includes a trimming module 100, a trimming register module 200, a storage unit 300, a selector 400, a processing unit 500, and a data loading circuit 600. The tuning register module 200 is connected to the tuning module 100; the selector 400 has a first selection terminal, a second selection terminal, an output terminal, and a control terminal. The first selection terminal is used to sequentially input multiple preset test tuning data written externally, and the output terminal is connected to the tuning register module 200; the processing unit 500 is used to acquire a mode selection signal and output the mode selection signal to the control terminal, and to tune the tuning module 100 according to each test tuning data, obtaining multiple tuning results one-to-one, selecting target tuning data from the multiple test tuning data according to the multiple tuning results, and writing the target tuning data into the storage unit 300; the data loading circuit 600 is connected to the second selection terminal and the processing unit 500 respectively. The data loading circuit 600 is used to read the target tuning data from the storage unit 300 to the second selection terminal, so as to transmit the target tuning data to the tuning register module 200, thereby tuning the tuning module 100 according to the target tuning data.

[0109] Storage cell 300 is a FLASH memory, which can erase, write, and reprogram memory cell blocks, and can retain data for a long time without a current supply. The FLASH memory includes two types of areas: a main array, used as program space, and a non-volatile register (NVR) area, used to record frequently used register data. The FLASH memory has multiple interfaces, all used for enabling operations. During the testing phase, the target trimming data is stored in the NVR area of ​​the FLASH memory. This allows the chip to directly load the target trimming data stored in the FLASH memory into the trimming register module 200 during non-testing phases, enabling the trimming module 100 to be trimmed according to the target trimming data. It should be noted that storage cell 300 can also use other storage devices that can achieve the same function, and this should not be considered a limitation of the invention.

[0110] The selector 400 has a first selection terminal, a second selection terminal, an output terminal, and a control terminal. The control terminal receives a mode selection signal to select whether the chip is in the testing phase. The mode selection signal is in high / low level form. When the mode selection signal is 1, it indicates that the chip is in the testing phase. The selector 400 selects an external I / O (first selection terminal) to directly serially write to the trimming register module 200. By traversing all test trimming data, the most suitable data is selected as the target trimming data, and the target trimming data is recorded in a designated non-volatile register area of ​​the FLASH memory. When the mode selection signal is 0, it indicates that the chip is not in the testing phase. The selector 400 selects the target trimming data output from the data loading circuit 600 (second selection terminal) to write to the trimming register module 200, so as to trim the trimming module 100 according to the target trimming data. It should be noted that the mode selection signal can also be 1 indicating that the chip is not in the testing phase and 0 indicating that the chip is in the testing phase; this should not be considered a limitation of the invention.

[0111] The data loading circuit 600 includes a reset signal detection circuit, an address memory, and a read enable circuit. The reset signal detection circuit detects the chip's reset signal. The address memory stores address information for a target address region, which is a pre-defined non-volatile register region of the FLASH memory, used to store target adjustment data. The read enable circuit, upon detecting the reset signal, reads the target adjustment data from the target address region to a second selection terminal based on the address information, transmitting the target adjustment data to the adjustment register module 200. This allows the adjustment module 100 to be adjusted based on the target adjustment data. Each time the chip is reset and released, the read enable circuit performs a read operation on the target address region, reading the target adjustment data from the target address region to the second selection terminal. The data loading circuit 600 also includes a clock circuit, allowing the loading process of the target adjustment data to be completed within one clock cycle, improving system stability.

[0112] It should be noted that the chip in this embodiment of the invention includes, but is not limited to, a module to be adjusted 100, an adjustment register module 200, a storage unit 300, a selector 400, a processing unit 500, and a data loading circuit 600. There can be multiple modules to be adjusted 100. Each module to be adjusted 100 corresponds to one adjustment register module 200, one selector 400, and one data loading circuit 600. Multiple modules to be adjusted 100 can use the same storage unit 300 or can correspond one-to-one with multiple storage units 300. No limitation is made here.

[0113] According to the chip of the present invention, the processing unit 500 can obtain a mode selection signal to determine whether the chip is in the testing phase. If the mode selection signal indicates that the chip is in the testing phase, multiple preset test tuning data are sequentially written from the outside into the tuning register module 200 through the first selection terminal of the selector 400. The tuning module 100 is tuned according to each test tuning data. Target tuning data is selected from the multiple test tuning data, and then the processing unit 500 writes the target tuning data into the storage unit 300. If the mode selection signal indicates that the chip is not in the testing phase, the target tuning data is directly read from the storage unit 300 to the second selection terminal of the selector 400 through the data loading circuit 600, and then output to the tuning register module 200. Finally, the tuning module 100 is tuned according to the target tuning data. Using the data loading circuit 600 to load the target tuning data reduces the CPU's operating load, and the loading of the target tuning data can be completed within one clock cycle, improving the system's stability. The chip in this embodiment of the invention implements the chip initialization process through a combination of hardware and software, which can improve system stability and reduce the CPU's operating load.

[0114] In some embodiments of the present invention, the storage unit 300 includes a target address region for storing target adjustment data; the data loading circuit 600 includes a reset signal detection circuit, an address memory, and a read enable circuit. The reset signal detection circuit detects a reset signal; the address memory stores address information of the target address region; the read enable circuit, after the reset signal detection circuit detects the reset signal, reads the target adjustment data from the target address region to a second selection terminal according to the address information, so as to transmit the target adjustment data to the adjustment register module 200, thereby adjusting the adjustment module 100 according to the target adjustment data. The target address region is a predefined non-volatile register region of the FLASH flash memory, used to store the target adjustment data. After each chip reset and release, the read enable circuit performs a read operation on the target address region, thereby reading the target adjustment data in the target address region into the adjustment register module 200. The data loading circuit 600 also includes a clock circuit, allowing the loading process of the target adjustment data to be completed within one clock cycle, improving system stability. The target adjustment data is loaded immediately after the reset signal is detected by the reset signal detection circuit. Before that, the processing unit 500 does not perform any additional erase, programming, or continuous read operations on the FLASH flash memory, which makes the system more stable, reliable, and less prone to errors.

[0115] In some embodiments of the present invention, the trimming register module 200 includes multiple trimming registers, which are used together to improve the trimming accuracy of the module 100 to be trimmed. The trimming register module 200 is an n-bit register (n is at least 2), and each module 100 to be trimmed can correspond to one or more sets of trimming registers. Each module 100 to be trimmed may have several trimming levels; assuming the trimming register module 200 is n-bit, it will correspond to 2... n There are several different adjustment ranges; the more adjustment ranges available, the higher the adjustment accuracy. Taking a voltage reference of 0.8V as an example, the adjustment ranges corresponding to the specific target adjustment data are shown in Table 1.

[0116] Table 1. Adjustment levels corresponding to target adjustment data.

[0117] 000 Initial voltage (ideally 0.8V) 001 Initial voltage +0.05V 010 Initial voltage +0.1V 011 Initial voltage +0.15V 100 Initial voltage -0.05V 101 Initial voltage -0.1V 110 Initial voltage -0.15V 111 Initial voltage -0.2V

[0118] Furthermore, the processing unit 500 of this embodiment includes: a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor and the memory can be connected via a bus or other means.

[0119] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0120] The non-transient software program and instructions required to implement the initialization method of the above embodiments are stored in memory. When executed by the processor, the initialization method of the above embodiments is executed.

[0121] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0122] Furthermore, a fourth aspect of the present invention provides a computer-readable storage medium storing computer-executable instructions that are executed by a processor or controller, for example, by a processor in an embodiment of the present invention, such that the processor performs the initialization method described in the above embodiment.

[0123] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0124] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A chip initialization method, characterized in that, The chip includes a module to be adjusted, an adjustment register module, a storage unit, a processing unit, and a data loading circuit; the initialization method includes the following steps: Acquire mode selection signal; The chip initialization strategy is executed according to the mode selection signal, and the chip initialization strategy includes a test initialization strategy and a non-test initialization strategy. The test initialization strategy includes the following steps: sequentially writing multiple preset test adjustment data into the adjustment register module from an external source; adjusting the module to be adjusted according to each test adjustment data to obtain multiple adjustment results; selecting target adjustment data from the multiple test adjustment data according to the multiple adjustment results; and writing the target adjustment data into the storage unit through the processing unit. The non-test initialization strategy includes the following steps: reading the target adjustment data from the storage unit into the adjustment register module through the data loading circuit; and adjusting the module to be adjusted according to the target adjustment data.

2. The initialization method according to claim 1, characterized in that, The step of writing the target adjustment data into the storage unit through the processing unit includes the following steps: Obtain the preset target address region in the storage unit; The processing unit writes the target adjustment data into the target address area.

3. The initialization method according to claim 1, characterized in that, The data loading circuit includes a reset signal detection circuit, an address memory, and a read enable circuit, wherein the read enable circuit is connected to the reset signal detection circuit and the address memory, respectively. The step of reading the target trimming data from the storage unit into the trimming register module through the data loading circuit includes the following steps: Obtain the preset target address region in the storage unit; The address information of the target address region is read into the address memory; If the reset signal detection circuit detects the reset signal, the read enable circuit reads the target adjustment data from the target address region into the adjustment register module according to the address information, so that the module to be adjusted can be adjusted according to the target adjustment data.

4. The initialization method according to claim 3, characterized in that, The step of reading the target trimming data from the target address region into the trimming register module according to the address information through the read enable circuit includes the following steps: The read enable circuit generates a read enable control signal based on the address information. The read enable control signal is sent to the storage unit to read the target trimming data from the target address region into the trimming register module.

5. The initialization method according to claim 1, characterized in that, The step of executing the chip initialization strategy according to the mode selection signal includes the following steps: If the mode selection signal indicates that the chip is in the testing phase, the test initialization strategy is executed. If the mode selection signal indicates that the chip is in a non-test phase, the non-test initialization strategy is executed.

6. A chip initialization system, characterized in that, The chip includes a module to be adjusted, an adjustment register module, a storage unit, a processing unit, and a data loading circuit; the initialization system includes: The mode selection signal acquisition unit is used to acquire the mode selection signal; A chip initialization strategy execution unit is used to execute a chip initialization strategy according to the mode selection signal. The chip initialization strategy includes a test initialization strategy and a non-test initialization strategy. The test initialization strategy includes the following steps: sequentially writing multiple preset test tuning data from an external source into the tuning register module; tuning the module to be tuned according to each test tuning data, obtaining multiple tuning results; selecting target tuning data from the multiple test tuning data based on the multiple tuning results; and writing the target tuning data into the storage unit through the processing unit. The non-test initialization strategy includes the following steps: reading the target tuning data from the storage unit into the tuning register module through the data loading circuit; and tuning the module to be tuned according to the target tuning data.

7. A chip, characterized in that, include: Modules to be repaired / adjusted; A repair register module is connected to the module to be repaired; Storage unit; The selector has a first selection terminal, a second selection terminal, an output terminal, and a control terminal. The first selection terminal is used to sequentially input multiple preset test and adjustment data written externally. The output terminal is connected to the adjustment register module. The processing unit is used to acquire a mode selection signal and output the mode selection signal to the control terminal, and to adjust the module to be adjusted according to each test adjustment data, to obtain multiple adjustment results in a one-to-one correspondence, to select target adjustment data from multiple test adjustment data according to multiple adjustment results, and to write the target adjustment data into the storage unit. A data loading circuit is connected to the second selection terminal and the processing unit respectively. The data loading circuit is used to read the target adjustment data from the storage unit to the second selection terminal, so as to transmit the target adjustment data to the adjustment register module, thereby adjusting the module to be adjusted according to the target adjustment data.

8. The chip according to claim 7, characterized in that, The storage unit includes a target address region, which is used to store the target adjustment data; The data loading circuit includes: Reset signal detection circuit, used to detect reset signal; An address storage device is used to store the address information of the target address region; The read enable circuit is used to read the target adjustment data from the target address region to the second selection terminal according to the address information after the reset signal detection circuit detects the reset signal, so as to transmit the target adjustment data to the adjustment register module, thereby adjusting the module to be adjusted according to the target adjustment data.

9. The chip according to claim 7, characterized in that, The adjustment register module includes multiple adjustment registers, which together are used to improve the adjustment accuracy of the module to be adjusted.

10. A computer-readable storage medium storing computer-executable instructions, characterized in that, The computer-executable instructions are used to perform the initialization method as described in any one of claims 1 to 5.

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