Benchmark program generation method, device, computer device, and storage medium

Abstract

A method, device, computer device, and storage medium for generating a benchmark program can be applied to a cloud server. The method includes: obtaining a target program to be tested; during the running process of the target program, obtaining status information and system call information associated with instructions; analyzing the status information to determine simulation information corresponding to the target program; combining the target program with the simulation information and system call information to obtain a benchmark program corresponding to the target program. Through the above method, the generated benchmark program simplifies the requirements for the running environment and can be applied to test a hardware platform in the development stage; moreover, all the inputs for generating the benchmark program come from the target program and are independent of the hardware platform to be tested. Even for an unknown hardware platform, a benchmark program can be generated for testing on the new hardware platform to predict the performance of the target program on the new hardware platform.

Description

Technical Field

[0001] The present application relates to the field of computer technologies, and particularly to a method and apparatus for generating a benchmark program, a computer device, and a storage medium. Background Art

[0002] How well existing services perform on a new hardware platform is a concern for cloud service providers. However, even if there are performance issues on the new hardware platform, they often only become apparent after the new hardware platform is finalized. The main reasons are as follows: Although various benchmark programs have long been widely used in the industry, there is still a certain gap between general benchmark programs and real business programs in terms of measuring the performance of new hardware platforms; real business programs cannot be tested for performance on actual hardware during the definition stage due to various reasons.

[0003] In related technologies, a benchmark program corresponding to a hardware system with known characteristic parameters can be generated, but this method cannot obtain a benchmark program corresponding to a business program for an unknown or developing hardware system. Summary of the Invention

[0004] Based on this, in view of the above technical problems, it is necessary to provide a method and apparatus for generating a benchmark program, a computer device, and a storage medium that can generate a benchmark program for an unknown or developing hardware system.

[0005] A method for generating a benchmark program, the method comprising:

[0006] Obtaining a target program to be tested;

[0007] During the running of the target program, obtaining status information and system call information associated with instructions;

[0008] Analyzing the status information to determine simulation information corresponding to the target program;

[0009] Combining the target program with the simulation information and the system call information to obtain a benchmark program corresponding to the target program.

[0010] An apparatus for generating a benchmark program, the apparatus comprising:

[0011] A target program obtaining module, configured to obtain a target program to be tested;

[0012] A status information obtaining module, configured to obtain status information and system call information associated with instructions during the running of the target program;

[0013] A simulation information determining module, configured to analyze the status information to determine simulation information corresponding to the target program;

[0014] A test program generation module, configured to combine the target program with the simulation information and system call information to obtain a benchmark test program corresponding to the target program.

[0015] A computer device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0016] Obtain a target program to be tested;

[0017] During the running of the target program, obtain status information and system call information associated with the instruction;

[0018] Analyze the status information to determine the simulation information corresponding to the target program;

[0019] Combine the target program with the simulation information and system call information to obtain a benchmark test program corresponding to the target program.

[0020] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0021] Obtain a target program to be tested;

[0022] During the running of the target program, obtain status information and system call information associated with the instruction;

[0023] Analyze the status information to determine the simulation information corresponding to the target program;

[0024] Combine the target program with the simulation information and system call information to obtain a benchmark test program corresponding to the target program.

[0025] For the above benchmark test program generation method, device, computer device and storage medium, by obtaining the target program to be tested and the status information associated with the instruction during the running of the target program, after analyzing the status information, the simulation information corresponding to the target query is obtained, and the target program is combined with the simulation information to obtain the benchmark test program corresponding to the target program. Among them, the target program runs on the existing hardware platform. After collecting the status information related to the instruction and analyzing to obtain the simulation information, the benchmark test program is obtained by combining the target program. The benchmark test program generated in this way simplifies the requirements for the running environment and can be applied to test the hardware platform in the development stage; and all the inputs for generating the benchmark test program come from the target program and are independent of the hardware platform to be tested. Even for an unknown hardware platform, a benchmark test program can be generated for testing on the new hardware platform to predict the performance of the target program on the new hardware platform. Description of the Drawings

[0026] Figure 1 It is a flowchart showing the method for generating a benchmark program in an embodiment;

[0027] Figure 2 It is a flowchart showing the process of analyzing status information to determine simulation information corresponding to a target program in an embodiment;

[0028] Figure 3 It is a flowchart showing the process of determining the instruction simulation transition probability of a target program based on an instruction sequence in an embodiment;

[0029] Figure 4 It is a flowchart showing the process of combining a target program with simulation information and system call information to obtain a benchmark program corresponding to the target program in an embodiment;

[0030] Figure 5 It is a recording / playback diagram of a target program in a specific embodiment;

[0031] Figure 6 It is a recording / playback data statistics diagram of a target program in a specific embodiment;

[0032] Figure 7 It is a recording / playback data comparison diagram of a target program in a specific embodiment;

[0033] Figure 8 It is a general flowchart showing the method for generating a benchmark program in a specific embodiment;

[0034] Figure 9 It is a flowchart showing the process of obtaining conditional jump instructions and function call transition probabilities in a specific embodiment;

[0035] Figure 10 It is a flowchart showing the process of combining simulation information and a target program to generate a benchmark program in a specific embodiment;

[0036] Figure 11 It is a structural block diagram of a benchmark program generation device in an embodiment;

[0037] Figure 12 It is an internal structure diagram of a computer device in an embodiment. Detailed Description of the Embodiment

[0038] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0039] In one embodiment, as Figure 1 shown, a benchmark program generation method is provided. In this embodiment, taking the application of this method to a terminal as an example, it can be understood that this method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server.

[0040] Among them, the server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, and can also be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, etc., but is not limited thereto. The terminal and the server can be directly or indirectly connected through wired or wireless communication methods, and this application does not limit this.

[0041] Cloud computing refers to the delivery and usage model of IT infrastructure, which means obtaining the required resources in a on-demand and easily expandable manner through the network; in a broad sense, cloud computing refers to the delivery and usage model of services, which means obtaining the required services in a on-demand and easily expandable manner through the network. Such services can be related to IT and software, the Internet, or other services. Cloud computing is the product of the development and integration of traditional computer and network technologies such as grid computing, distributed computing, parallel computing, utility computing, network storage technologies, virtualization, and load balance.

[0042] With the development of the Internet, real-time data streams, and the diversification of connected devices, as well as the promotion of demands such as search services, social networks, mobile commerce, and open collaboration, cloud computing has developed rapidly. Different from previous parallel distributed computing, the emergence of cloud computing will revolutionize the entire Internet model and enterprise management model conceptually.

[0043] In this embodiment, the method includes steps S110 to S140.

[0044] Step S110, obtain the target program to be tested.

[0045] Among them, the target program to be tested represents a program for which a benchmark program needs to be generated. The generated benchmark program can be used for subsequent testing of the target program on a new hardware platform. The new hardware platform can be a hardware platform in the development stage or a completed hardware platform.

[0046] In one embodiment, the type of the target program to be tested is an executable file. An executable file refers to a file that can be loaded and executed by an operating system. In different operating system environments, the presentation of an executable program is different. Under the Windows operating system, an executable program can be a file of types such as.exe,.sys,.com, etc. If the target program is an executable file and the program source code cannot be obtained, a corresponding benchmark program can also be generated from the more easily obtainable executable file. In other embodiments, the target program can also be of other types.

[0047] Step S120: During the running of the target program, obtain status information and system call information associated with the instructions.

[0048] Among them, the running process of the target program can be on an existing hardware platform, which is in contrast to the new hardware platform for which performance needs to be tested. The execution process of the target program includes a user-mode logic execution process and a kernel-mode logic execution process. Among them, the user-mode logic is determined by the target program and its related dynamic link libraries, and the kernel-mode logic is determined by the system call information. In one embodiment, during the running of the target program, status information associated with the instructions is obtained in the user mode, and system call information is obtained in the kernel mode.

[0049] The status information associated with the instructions is information used to indicate information related to the instructions during the running of the program. During the running of the target program, status information associated with the instructions can be obtained. In one embodiment, the instructions include memory access instructions and non-memory access instructions, where the non-memory access instructions can include conditional jump instructions and function call instructions. Further, in one embodiment, the status information associated with the instructions includes: the address of the currently executed instruction, the current function call stack, the number of instructions already executed by the current corresponding thread, and for memory access instructions, record the corresponding accessed linear address. In other embodiments, the status information associated with the instructions can also include other contents.

[0050] The system call information represents information on system call-related interfaces during the running of the program. In one embodiment, the system call information includes the input parameters of the system call and the relevant system call return results.

[0051] In one embodiment, a state information acquisition tool is used to acquire state information associated with instructions during the running of a target program. For example, in a specific embodiment, the Pin tool can be used to acquire state information associated with instructions in the user state. The commonly used Pin tool in the industry executes the target program through binary translation and can obtain various register intermediate variable information during the program execution process, including the memory access addresses of the program. By analyzing the program stack, function call stack information can also be obtained. In another embodiment, the page fault mechanism of the CPU and the operating system can also be used to acquire state information associated with instructions during the running of the target program. The page fault mechanism of the CPU and the operating system can also be used to obtain this information. A page fault is a processor interrupt triggered by an application accessing a linear address for which there is no page table mapping relationship. The processor will suspend the execution of the current user-state instruction and switch to the kernel state to handle this page fault. During the handling process, the kernel-state logic can analyze the register and program heap information to obtain: the instruction address, the function call stack, and the accessed linear address; the number of instructions executed by the current thread can be obtained through the processor PMU counter. By controlling the page table mapping relationship of the linear address, page fault interrupt events can be artificially created to obtain the state information of the target program. In other embodiments, state information associated with instructions can also be obtained through other means.

[0052] In one embodiment, system call information can be acquired through relevant tools. For example, in a specific embodiment, in all Linux systems (an operating system), Unix systems (an operating system), the system call information in the kernel state can be obtained through the Linux strace tool (a debugging and tracing tool that can take over the system calls and received signals of the traced process); in Windows systems (an operating system developed by Microsoft), the StraceNT tool can be used; in macOS systems (an operating system developed by Apple and running on Macintosh series computers), the dtruss tool (which can be used to analyze the (error) behavior of applications on OS X) can be used. In other embodiments, system call information can also be obtained through other means.

[0053] Furthermore, in one embodiment, during the running of the target program, state information and system call information associated with instructions are acquired at preset time intervals. In this embodiment, the obtained state information and system call information are discrete. Among them, the preset time interval can be set according to the actual situation. In this embodiment, by acquiring discrete state information and system call information from the running process of the target program at preset time intervals, the instruction stream executed during the running process of the target program is subsequently analyzed using the discrete state information and system call information, and then a benchmark test program is generated.

[0054] Step S130: Analyze the status information to determine the simulation information corresponding to the target program.

[0055] After obtaining the status information, the status information can be analyzed to obtain the simulation information of the target program. In this embodiment, the simulation information represents the information obtained by analyzing the status information. In one embodiment, the simulation information corresponding to the target program includes: the instruction simulation transfer probability of the target program, and the simulated access linear address corresponding to the memory access instruction in the target program.

[0056] The instruction simulation transfer probability represents the transfer probability between conditional jump instructions or the transfer probability of function call instructions. Among them, a conditional jump instruction generally has two possible jump destination addresses, one is the target address (target1) encoded in the conditional jump instruction, and the other is the address of the next instruction in the instruction sequence order (target2). For any conditional jump instruction in the program, its transfer probability can be obtained after counting the jump results during its execution. For example, target1 - A%, target2 - B%, where A + B = 100. In one embodiment, the status information includes conditional jump instructions and function call instructions. Since the logic or function of program execution is limited, no matter how complex it is, after a period of sampling and observation, a relatively complete set of actual executed instructions can be obtained, and the transfer probabilities of conditional jump instructions and function call instructions can be obtained through statistical analysis of the set of actual executed instructions.

[0057] The simulated access linear address corresponding to the memory access instruction in the target program represents the linear address corresponding to the memory access instruction in the target program. In one embodiment, the status information includes memory access instructions and the linear addresses corresponding to the memory access instructions. In this embodiment, the simulated access linear address corresponding to the memory access instruction in the target program can be obtained after analyzing the status information. In other embodiments, the simulation information may also include other information. Further, the specific process of analyzing the status information to obtain the corresponding simulation information will be described in detail in subsequent embodiments and will not be elaborated here.

[0058] Step S140: Combine the target program with the simulation information and system call information to obtain the benchmark program corresponding to the target program.

[0059] Among them, the benchmark is used to measure the highest actual running performance of the machine's hardware and the performance improvement effect of software optimization, and can be divided into microbenchmark and macrobenchmark. In one embodiment, the generated benchmark has performance characteristics similar to the stable state of the target program, and can generate a similar pressure on the system under test as the target program; the benchmark is directly executable. The program stable state refers to the state when the program processes typical data of normal business, excluding the processing of error information and error events, and all resources required for program execution have been initialized.

[0060] In one embodiment, using binary recompilation technology, based on the target program, combined with simulation information and system call information, a benchmark is generated. Binary recompilation is a process of analyzing the program machine code based on the binary executable program to summarize the logical structure of the program, and then regenerating a separate binary program according to this information; the binary program generated by binary recompilation is functionally the same as the original program.

[0061] Furthermore, the detailed process of combining the target program with simulation information and system call information to obtain the benchmark corresponding to the target program will be described in detail in subsequent embodiments and will not be elaborated here.

[0062] The above benchmark generation method obtains the target program to be tested and the state information associated with the instructions during the running of the target program, analyzes the state information to obtain the simulation information corresponding to the target query, and combines the target program with the simulation information to obtain the benchmark corresponding to the target program. Among them, the target program runs on the existing hardware platform. After collecting the state information related to the instructions and analyzing to obtain the simulation information, the benchmark is obtained by combining the target program. The benchmark generated in this way simplifies the requirements for the running environment and can be used for testing on the hardware platform in the development stage; and all the inputs for generating the benchmark come from the target program and are independent of the hardware platform to be tested. Even for an unknown hardware platform, a benchmark can be generated for testing on the new hardware platform to predict the performance of the target program on the new hardware platform.

[0063] In one embodiment, the simulation information includes: the instruction simulation transfer probability of the target program and the simulated access linear address corresponding to the memory access instruction in the target program; in this embodiment, as Figure 2 shown, analyzing the state information to determine the simulation information corresponding to the target program includes steps S131 to S135.

[0064] Step S131: Read the access linear address corresponding to the non-memory access instruction and the memory access instruction in the status information.

[0065] Among them, the non-memory access instruction refers to an instruction that has nothing to do with memory access collected from the status information obtained during the operation of the target program. In one embodiment, the non-memory access instructions include conditional jump instructions and function call instructions. The memory access instruction is an instruction used to access the data storage structure. The address format of the memory access instruction is generally: base address + offset, where the base address is generally located in a register. In this embodiment, for the relevant information of the memory access instruction in the status information, the access linear address corresponding to the memory access instruction can be obtained.

[0066] Step S132: Obtain the instruction sequence between two status information according to the non-memory access instructions corresponding to two adjacent status information.

[0067] The status information corresponds to the relevant information of the status at a certain moment. Therefore, one status information can correspond to one instruction. If the instructions corresponding to two adjacent status information are both non-memory access instructions, an instruction sequence with these two instructions as the head and tail can be obtained. In one embodiment, if the status information is continuous, the obtained instruction sequence may only include two non-memory access instructions. In another embodiment, if the status information is discrete, there may be multiple instructions between two adjacent status information. At this time, the non-memory access instruction corresponding to the earlier status information can be used as the first non-memory access instruction, and the non-memory access instruction corresponding to the later status information can be used as the last non-memory access instruction, and the instructions between the first and last non-memory access instructions can be inferred in a certain way.

[0068] In one embodiment, obtaining the instruction sequence between two status information according to the non-memory access instructions corresponding to two adjacent status information includes: using the first non-memory access instruction among the non-memory access instructions corresponding to two adjacent status information as the first non-memory access instruction, and the second non-memory access instruction among the non-memory access instructions corresponding to two adjacent status information as the last non-memory access instruction; trying any instruction combination between the first non-memory access instruction and the last non-memory access instruction to obtain the instruction sequence.

[0069] In this embodiment, the non-memory access instructions corresponding to two adjacent status information are respectively used as the first and last instructions of the instruction sequence, and the instruction sequence is obtained by trying various combinations of instructions between the first and last instructions. In one embodiment, the non-memory access instructions include conditional jump instructions and function call instructions. Among them, trying any instruction combination between the first non-memory access instruction and the last non-memory access instruction can be implemented in any way, such as the enumeration method, etc.

[0070] Step S133: Determine the instruction simulation transition probability of the target program based on the instruction sequence.

[0071] After obtaining the instruction sequences between the instructions corresponding to adjacent two state information, and combining all the state information, multiple instruction sequences in the target program can be obtained; in one embodiment, if the state information is N, (N - 1) instruction sequences can be obtained.

[0072] After obtaining multiple instruction sequences of the target program, by counting various jump combinations in these instruction sequences, the transition probabilities corresponding to each jump combination of the non-memory access instructions in the target program can be obtained. In one embodiment, the conditional jump instruction X includes two possible jump destination addresses: target 1 and target 2. By counting the instruction sequences, the transition probabilities corresponding to the two jump destination addresses of the conditional jump instruction X can be obtained. For example, target1 - A%, target2 - B%, where A + B = 100. Since the transition probability is only obtained by counting the instruction sequences based on the simulation information, the transition probability between instructions obtained according to the instruction sequence is denoted as the instruction simulation transition probability in this embodiment.

[0073] In one embodiment, as Figure 3 shown, determining the instruction simulation transition probability of the target program based on the instruction sequence includes steps S1331 to S1333.

[0074] Step S1331: Obtain the instruction jump combinations composed of two-by-two instructions according to the instruction sequence.

[0075] The instruction sequence is composed of multiple instructions. In this embodiment, adjacent instructions are denoted as combined jump combinations.

[0076] Step S1332: Count the occurrence times of each instruction jump combination in the instruction sequence.

[0077] Among them, the occurrence times of the instruction jump combination represent the occurrence times of the same instruction jump combination in all instruction sequences.

[0078] Step S1333: Obtain the instruction simulation transition probability of the target program based on the occurrence times of each instruction jump combination.

[0079] By analyzing the occurrence times of each instruction jump combination in each instruction sequence, it is possible to determine the next instruction that each instruction may appear, as well as the probability corresponding to the next instruction of each instruction, and determine this probability as the instruction simulation transfer probability. It can be understood that the instruction simulation transfer probability includes the transfer probabilities corresponding to multiple different situations corresponding to multiple instructions; for example, for instruction X, the transfer probability from instruction X to target1 is A%, and the transfer probability from instruction X to target2 is B%, A + B = 100; for instruction Y, the transfer probability from instruction Y to target3 is C%, and the transfer probability from instruction Y to target4 is D%, C + D = 100, and so on.

[0080] Step S134, read the occurrence frequency of each accessed linear address.

[0081] Similar to counting the occurrence times of instruction jump combinations, the occurrence frequency of each accessed linear address can be obtained by counting the occurrence times of each accessed linear address in the memory access instructions corresponding to each state information. Subsequently, the accessed linear address can be filtered based on the occurrence frequency as the simulated accessed linear address.

[0082] Step S135, select the simulated accessed linear address based on the occurrence frequency of each accessed linear address.

[0083] In one embodiment, the accessed linear address whose occurrence frequency meets the preset condition can be taken as the simulated linear address. Among them, the preset condition can be set according to the actual situation; for example, in one embodiment, selecting the simulated accessed linear address based on the occurrence frequency of each accessed linear address includes: selecting the accessed linear address with the highest occurrence frequency and determining it as the simulated accessed linear address. In this embodiment, only a single accessed linear address is simulated, and the preset condition is set to take the accessed linear address with the highest occurrence frequency as the simulated accessed linear address. In another embodiment, only a single accessed linear address is simulated, and the preset condition can also be set to select any accessed linear address, or set to select the accessed linear address with a preset occurrence frequency value, and so on.

[0084] Furthermore, in another embodiment, it is also possible to set to select more than two accessed linear addresses for simulation, and the corresponding preset condition can be set to, for example, select the accessed linear addresses with the first and second highest occurrence frequencies as the simulated accessed linear addresses, or the preset condition can also be set to other conditions.

[0085] The linear address accessed by an instruction can be statically encoded (e.g., the current instruction address as the base address + a fixed offset), or it can be dynamic (e.g., register A + register B * scale + a fixed offset, where scale can be a number in [1, 2, 4, 8]). In one embodiment, the addresses accessed by most storage-related instructions follow a certain pattern within a small range, and different instructions have different patterns. In another embodiment, a small σ can also be added based on this single accessed linear address. Only simulate with a single accessed linear address, without adding other extra instructions / registers / memory resources to maintain state changes, simplifying the running environment required for simulation.

[0086] In this embodiment, it describes how to analyze the state information associated with instructions to obtain simulation information. Specifically, between non-storage access instructions corresponding to two adjacent state information, by trying various instruction combinations, an instruction sequence between adjacent state information is obtained. By counting the occurrence times of each instruction jump combination in each instruction sequence, the simulated jump probability of the instruction is obtained; at the same time, based on the occurrence frequency of the linear access address of the storage access instruction corresponding to each state information, and based on the occurrence frequency, a simulated access linear address is selected. Thus, in the target program, the simulated jump probability of non-storage access instructions and the simulated access linear address of storage access instructions are obtained, and subsequently, a benchmark program is generated using the simulation information.

[0087] Further, in one embodiment, as Figure 4 shown, the target program is combined with simulation information and system call information to obtain a benchmark program corresponding to the target program, including steps S141 to S144.

[0088] Step S141, parse the target program to obtain the intermediate state of the target program.

[0089] Among them, the intermediate state of the program contains all internal information of the program and can be used to generate an equivalent program with the same function as the input program. Among them, parsing the target program to obtain the corresponding intermediate state can be achieved in any way. In a specific embodiment, the target program is parsed through binary recompilation technology to obtain the intermediate state of the target query.

[0090] Step S142, based on the system call information and simulation information, replace the corresponding intermediate state information in the intermediate state to obtain the replaced program.

[0091] On the basis of parsing and obtaining the intermediate state of the target program, use the system call information and the instruction information included in the simulation information to overwrite part of the intermediate state information. In this embodiment, the program obtained after replacement is denoted as the program after replacement. In one embodiment, taking the replacement of part of the intermediate state information of the intermediate state with simulation information as an example, it may specifically include: rewriting the corresponding instructions in the intermediate state according to the instruction jump probability in the simulation information, and using the simulated access linear address in the simulation information as the access linear address of the benchmark program. Further, the detailed process of obtaining the program after replacement by replacing the corresponding intermediate state information in the intermediate state based on the system call information and the simulation information will be described in detail in the subsequent embodiments and will not be elaborated here.

[0092] Step S143, based on the simulated access linear address, add storage space initialization logic to the program after replacement to obtain the intermediate state incorporating the simulation information.

[0093] In the process of generating the benchmark program, use the simulated access linear address as the access linear address of the benchmark program and perform initialization before accessing the simulated access linear address to ensure that when the generated benchmark program is used for testing, the access linear address corresponding to the storage access instruction will not be incorrect.

[0094] In one embodiment, based on the simulated access linear address, adding storage space initialization logic to the program after replacement to obtain the intermediate state incorporating the simulation information includes: adding storage space initialization logic corresponding to the simulated access linear address in the initialization stage of the program after replacement to obtain the intermediate state incorporating the simulation information.

[0095] Further, in one embodiment, the storage space initialization logic can initialize the storage space corresponding to the simulated access linear address through memory mapping. Among them, the memory mapping method can establish the mapping relationship between the relevant linear address and the physical page. Any linear address accessed by the program requires the operating system to allocate memory resources, otherwise the program will be killed by the operating system (segmentation fault) because it accesses an invalid address. For the benchmark program generated using the above method, the linear addresses it needs to access are determined in advance. To avoid segmentation fault, it is necessary to allocate memory resources for the simulated linear address. In a specific embodiment, in the storage space initialization logic, the mmap tool can be used to apply for the corresponding internal resources for the simulated access linear address. mmap is a system call in Linux for applying for memory resources. The mmap interface allows inputting the specified linear address, and the operating system allocates memory resources for these specific addresses. Among them, adding the storage space initialization logic corresponding to the simulated access linear address in the initialization stage of the program after replacement can also be implemented by other means.

[0096] In one embodiment, the initialization phase of the replaced program may specifically be the entry point of the main function (the main function, which is the starting point of program execution). In this embodiment, storage space initialization logic corresponding to the simulated access linear address is added at the entry point of the main function of the replaced program.

[0097] In another embodiment, after the above method replaces the corresponding intermediate state information in the intermediate state based on the system call information and the simulation information to obtain the replaced program, it further includes: establishing a direct jump from the main function to the instructions in the instruction sequence in the replaced program. The target program generally consists of initialization logic and main processing logic, and most of the program execution time is spent executing the main processing logic. The main purpose of the benchmark program generated in the above embodiment is to simulate the main processing logic and does not consider the simulation of the target program initialization logic. Therefore, the instructions executed during the initialization process of the target program do not need to be executed in the benchmark program. During the above process of generating the benchmark program, the instructions to be simulated are clearly defined, so a suitable instruction (for example: <instr_entry>) can be found as the first instruction to simulate the main processing logic; for example, when generating the benchmark program, adding jmp <instr_entry> in the main function of the replaced program is sufficient.

[0098] Step S144, generating a benchmark program corresponding to the target program according to the intermediate state of the merged simulation information.

[0099] After adding the storage space initialization logic to the replaced program based on the simulated access linear address, the intermediate state of the merged simulation information is obtained. In this embodiment, it is denoted as the intermediate state of the merged simulation information; further, a benchmark program corresponding to the target program can be generated according to the intermediate state of the merged simulation information.

[0100] In this embodiment, by using binary recompilation technology, during the recompilation of the target program, conditional jump instructions, function call instructions, and memory access instructions included in all state information can be rewritten, system call information can be added, and storage space initialization logic can be increased to generate a benchmark program that can execute independently.

[0101] In one embodiment, the above method includes: the instruction simulation transfer probability of the target program includes: the transfer probability of the conditional jump instruction; in this embodiment, replacing the corresponding intermediate state information in the intermediate state based on the system call information and the simulation information includes: determining the replacement object of the conditional jump instruction according to the transfer probability of the conditional jump instruction; replacing the conditional jump instruction in the intermediate state with the replacement object of the conditional jump instruction.

[0102] As can be seen from the description in the above embodiments, a conditional jump instruction usually includes two possible jump destination addresses, and the transfer probabilities of each conditional jump instruction have been determined when analyzing the state to obtain simulation information. Therefore, in this embodiment, the replacement object corresponding to the conditional jump instruction can be determined in combination with the transfer probability of the conditional jump instruction, and the corresponding conditional jump instruction in the intermediate state is replaced with the replacement object.

[0103] In a specific embodiment, the transfer probabilities of the conditional jump instruction are target1 - A%, target2 - B%. For the case where A or B is 0, the instruction has only one jump address and is directly rewritten as an unconditional jump instruction jmptargetX.

[0104] In another specific embodiment, the transfer probabilities of the conditional jump instruction are target1 - A%, target2 - B%. For the case where there are transfer probabilities for both addresses, assume here that A > B and let Ratio = int(A / B). Add a j_ratio variable to the target program and use it to control the jump result of the corresponding instruction. The following logic can be adopted:

[0105]

[0106] In other embodiments, the replacement object corresponding to the conditional jump instruction can be determined in combination with the transfer probability of the conditional jump instruction, and it can also be implemented by other means.

[0107] In one embodiment, the above method includes: the instruction simulation transfer probability of the target program includes: the transfer probability of the function call instruction; in this embodiment, based on the system call information and the simulation information, the corresponding intermediate state information in the intermediate state is replaced, including: if the target address of the function call instruction includes a dynamic target address, the replacement object of the function call instruction is determined according to the dynamic target address; the function call instruction in the intermediate state is replaced with the replacement object of the function call instruction.

[0108] As can be seen from the description in the above embodiments, the transfer probabilities of each function call instruction have been determined when analyzing the state to obtain simulation information. Therefore, in this embodiment, the replacement object corresponding to the function call instruction can be determined in combination with the transfer probability of the function call instruction, and the corresponding function call instruction in the intermediate state is replaced with the replacement object.

[0109] In a specific embodiment, there are two types of function call instructions. One type of instruction has a constant target address included in the instruction, and such instructions do not need to be modified. Another type of instruction has a target address located in a register or storage space (memory), and such function call instructions need to be rewritten. For the case of a single target address, the corresponding instruction can be simply rewritten; for the case of multiple target addresses, variables are added to control random jumps according to the method of conditional jump instructions with two jump results.

[0110] In one embodiment, the above method includes: the instruction simulation transfer probability of the target program includes: the transfer probability of the function call instruction; in this embodiment, based on the system call information and simulation information, the corresponding intermediate state information is replaced in the intermediate state, including: if the target address of the function call instruction includes more than two dynamic target addresses, the replacement object of the function call instruction is determined according to the transfer probability of the function call instruction and the dynamic target address; the function call instruction in the intermediate state is replaced with the replacement object of the function call instruction.

[0111] In another embodiment, replacing the corresponding intermediate state information with simulation information in the intermediate state includes: determining the replacement object of the memory access instruction; replacing the memory access instruction in the intermediate state with the replacement object of the memory access instruction.

[0112] Among them, the address format of the memory access instruction is generally: base address + offset, where the base address is generally located in a register. When updating the memory access instruction, it is necessary to ensure that the linear access address falls within the valid memory address range. By analyzing the instruction stream, it can be known whether the base address register of a certain memory access instruction contains a valid linear address. If this condition is not met, additional instructions need to be added before this instruction to set the valid linear address. Among them, analyzing and determining whether the base address register of the memory access instruction contains a valid linear address can be achieved through the following method: since all jump / function call instructions are under control, all instruction execution paths can be obtained. For example, there are N instructions between instruction A and instruction B. By comparing with all possible instruction execution paths, it can be found that there is no possibility of directly jumping to these N instructions from other instructions, and the base address register R1 of instruction A will not be modified in these N instructions, then instruction B can directly use the base address register R1 of instruction A. If there is a possibility of directly jumping to these N instructions from other instructions, this means that the value of R1 may be other and cannot be used as the base address for memory access.

[0113] Further, after determining that the linear access address falls within the valid memory address range, the replacement object of the memory access instruction can be determined, and the replacement object of the memory access instruction is replaced with the corresponding memory access instruction in the intermediate state.

[0114] In one embodiment, replacing the corresponding intermediate state information with analog information in the intermediate state includes: determining the replacement object of the system call information; and replacing the system call information in the intermediate state with the replacement object of the system call information.

[0115] In a specific embodiment, after finding the relevant system calls by analyzing the target program, the original system call logic is bypassed by rewriting the relevant instructions, and new system call logic is added according to the relevant information. All parameter settings follow the analog information - system call parameters, where array parameters can use the initialized storage space.

[0116] In this embodiment, based on different situations of replacing the corresponding intermediate state information with analog information in the intermediate state according to the system call information, a detailed description is given. By replacing some of the intermediate state information in the intermediate state through the above steps, an independently executable benchmark program can be obtained.

[0117] In a specific embodiment, through the above method, the Tconnd benchmark is modeled to generate a benchmark program. From the final effect, the generated benchmark program is quite close to the original Tconnd program in terms of parameters such as user - mode IPC, user - mode cache miss rate, DRAM bandwidth / delay, etc. As Figure 5 shown in the recording / playback schematic diagram of the Tconnd benchmark, Figure 6 shown in the recording / playback data statistics schematic diagram of the Tconnd benchmark, Figure 7 shown in the recording / playback data comparison schematic diagram of the Tconnd benchmark.

[0118] Among them, IPC represents the number of instructions executed by the CPU in each clock cycle, which is a rough measure of CPU performance. IPC is a dynamic indicator, and different programs will have different IPC results on the same CPU. Cache Miss (events / s) represents cache misses. The cache hit situation has a relatively large impact on performance. The CPU generally has a built-in PMU counter to count the cache miss situation. This counter is usually a counter. Therefore, the cache miss situation within a certain period of time (how many cache misses occur per second) is determined by two accesses at intervals. Among them, cache miss events may occur in caches at different levels (L1-L3), and can also be combined with the CPU mode (user mode / kernel mode) for the following detailed decomposition: User L1 Cache Miss, User L2 Cache Miss, User L3 Cache Miss, Kernel L1 Cache Miss, Kernel L2 Cache Miss, Kernel L3 Cache Miss.

[0119] As Figure 7 shown in the comparison of the original / playback data, the data mainly reflects that the generated benchmark program is relatively close to the target program in terms of the main indicator of IPC, reflecting the accuracy of the simulation. Considering the results in both user mode and kernel mode, the difference in IPC from the target program is about 7%.

[0120] This application also provides an application scenario that applies the above benchmark test program generation method. In this embodiment, taking the above method based on the x86 architecture as an example, the operating system is Linux; in other embodiments, similar practices can also be implemented on other architectures (such as ARM64), and the operating system can be the Windows system. As Figure 8 shown in the overall flow diagram of the benchmark test program generation method in this embodiment. Specifically, the application of the benchmark test program generation method in this application scenario is as follows:

[0121] To have a performance effect close to that of the target program, the most ideal way is to use the same instruction sequence as the target program during execution and process the same data set. In terms of the overall architecture, in this embodiment, the running instruction stream information of the target program is obtained, and a benchmark test program is constructed in combination with the target program binary file. Specifically, the following two types of information need to be collected for the target program:

[0122] ① Sample the execution process of the target program in user mode to obtain discrete state information, including the instruction address executed during sampling, the call stack, the number of instructions executed by the corresponding thread, and record the linear address corresponding to the storage (memory) access instruction.

[0123] ② System call information, including: input parameters of system calls, return results of related system calls.

[0124] Perform state analysis on the obtained discrete state information to obtain simulation information on control flow and memory access. Combine the system call information and use binary recompilation technology to generate a directly executable benchmark program based on the executable file of the target program. Taking the Linux operating system as an example, multiple threads may execute interleaved during the execution of the target program. The following description is based on a single-threaded program, and the multi-threaded situation can be decomposed into single threads and processed similarly.

[0125] Furthermore, the specific descriptions of each stage of the above steps are as follows:

[0126] (1) Extract discrete state information from the actually running target program

[0127] The execution process of the target program includes the user-mode logical execution process and the kernel-mode logical execution process. For the user mode: from the perspective of the general-purpose processor, the program execution process is the process of the processor executing instructions. Since the error / exception handling code included in the program logic is rarely triggered in the normal execution state, the actual instruction sequence executed by the program is often simpler than the instructions included in the program executable file. The observed instruction set obtained from the actual execution is part of the executable file instruction set.

[0128] Since it is necessary to analyze the collected instruction samples later to obtain the actual execution path distribution of the instructions, and for memory-related instructions, it is necessary to know their approximate linear address range for simulation in the benchmark program. Therefore, in the actually running target program, collect the following state information associated with the instructions: the current instruction address, the number of instructions executed by the current thread, the current function call stack, and the current accessed linear address (memory-related instructions). The methods for obtaining the above information have been described in the above embodiments and will not be elaborated here.

[0129] The state information related to the kernel mode includes the input parameters of system calls, and these information can be obtained by the Linux strace tool.

[0130] (2) Perform state analysis on the state information to obtain simulation information

[0131] In this embodiment, the simulation information includes: a. The simulated transfer probability of instructions, specifically including the transfer probability of conditional jump instructions and the transfer probability of function call instructions; b. The linear addresses of memory-related instructions

[0132] Among them, for any conditional jump instruction in the program, its transfer probability can be obtained by counting the jump results during its execution process. For example, target1 - A%, target2 - B%, where A + B = 100. The discrete information contains the linear addresses accessed by the program. In a specific embodiment, the linear address with the highest occurrence frequency is selected as the simulated access linear address.

[0133] The process of obtaining the transfer probabilities of conditional jump instructions and function calls is as Figure 9 shown. First, for every two adjacent discrete state information (such as SampleN and SampleN+1), the conditional jump instructions and function call instructions of an instruction stream (SegmentN) can be obtained (by trying various combinations of conditional jump instructions and function call instructions). A total of N Segment (fragment) information (the above instruction sequences) can be obtained from N+1 discrete state information. Each Segment information contains a certain number of conditional jump instruction transfer results / function call instruction transfer results. After summarizing all Segment information, the transfer probabilities of each conditional jump instruction and function call instruction can be obtained.

[0134] (3) Combining the simulated information and the target program to generate a benchmark program

[0135] This step mainly uses binary recompilation technology. During the recompilation of the target program, the conditional jump instructions, function call instructions, and memory access instructions contained in all discrete state information can be rewritten, system call information can be added, and storage space initialization logic can be added, so as to generate a benchmark program that can execute independently. The specific process is as Figure 10 shown, including the following steps:

[0136] Regarding the rewriting of conditional jump instructions in the intermediate state, there are two cases. The first case is that the transfer probability of the conditional jump instruction is target1 - A%, target2 - B%. For the case where A or B is 0, this conditional jump instruction has only one jump address, and it is directly rewritten as an unconditional jump instruction (the replacement object corresponding to the above conditional jump instruction), such as jmptarget X. The second case is: the transfer probability of the conditional jump instruction is target1 - A%, target2 - B%. For the case where both addresses have transfer probabilities, here it is assumed that A > B ≠ 0, and let Ratio = int(A / B). Add a j_ratio variable in the target program, and it controls the jump result of the corresponding instruction. The specific jump logic has been described in detail in the above embodiment and will not be elaborated here.

[0137] For function call instructions in the intermediate state, there are two types of function call instructions. One type of instruction has a target address that is a constant included in the instruction, and such instructions do not need to be modified. The other type of instruction has a target address located in a register or storage space (memory), and such function call instructions need to be rewritten. For the case of a single target address, the corresponding replacement object can be simply rewritten, such as jmp target address x; for the case of multiple target addresses, variables are added to control random jumps in the same way as conditional jump instructions with two jump results.

[0138] For memory access instructions in the intermediate state: The address format of memory access instructions is generally: base address + offset, where the base address is generally located in a register. When updating memory access instructions, it is necessary to ensure that the access address falls within the valid memory address range. By analyzing the instruction stream, it can be known whether the base address register of a certain memory access instruction contains a valid linear address. If this condition is not met, additional instructions need to be added before this instruction to set the valid linear address. If the condition is met, the memory access instruction can be directly rewritten as the corresponding replacement object.

[0139] For system call information in the intermediate state: After finding the relevant system call information by analyzing the target program, rewrite the relevant instructions to bypass the original system call logic, and add new system call logic according to the relevant information. All parameter settings are in accordance with the simulation information - system call parameters, and array parameters can use initialized storage spaces.

[0140] The linear addresses accessed by memory-related instructions in the benchmark program need to be initialized before access. Therefore, after replacing some information in the intermediate state with the above simulation information, add memory space initialization logic to the replaced program to obtain the intermediate state merged with the simulation information; specifically, it can be added in the program initialization stage, such as the entry of the main function. Further, the added memory space initialization logic can be to call the mmap operation to establish the mapping relationship between the relevant linear address and the physical page.

[0141] In another embodiment, it may be necessary to establish a direct jump from the main function to an instruction in the simulated instruction stream.

[0142] Finally, generate a benchmark program based on the intermediate state merged with the simulation information. The performance characteristics of the benchmark program are relatively close to those of the target program. All input information relied on by the above method comes from the executable file of the program, and this requirement can be met in all environments where the program can be executed; and no assumptions are made about the hardware platform to be tested. The generated benchmark program simplifies the requirements for the running environment and can be used on the hardware platform in the development stage to predict in advance the performance results of the target program on the new hardware platform.

[0143] It should be understood that although the steps in the respective flowcharts involved in the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the respective flowcharts involved in the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0144] In one embodiment, as Figure 11 shown, a benchmark program generation device is provided. This device can be a software module, a hardware module, or a combination of both to form a part of a computer device. Specifically, the device includes: a target program acquisition module 1110, a status information acquisition module 1120, a simulation information determination module 1130, and a test program generation module 1140, where:

[0145] The target program acquisition module 1110 is used to acquire the target program to be tested;

[0146] The status information acquisition module 1120 is used to acquire status information and system call information associated with instructions during the running of the target program;

[0147] The simulation information determination module 1130 is used to analyze the status information to determine the simulation information corresponding to the target program;

[0148] The test program generation module 1140 is used to combine the target program with the simulation information and the system call information to obtain the benchmark test program corresponding to the target program.

[0149] The above benchmark program generation device obtains a target program to be tested and status information associated with instructions during the operation of the target program, obtains simulation information corresponding to a target query after analyzing the status information, and combines the target program with the simulation information to obtain a benchmark program corresponding to the target program. Among them, the target program runs on an existing hardware platform. By collecting status information related to instructions, analyzing to obtain simulation information, and then combining the target program, a benchmark program is obtained. The benchmark program generated in this way simplifies the requirements for the operating environment and can be used for testing on a hardware platform in the development stage; moreover, all the inputs for generating the benchmark program come from the target program and are independent of the hardware platform to be tested. Even for an unknown hardware platform, a benchmark program can be generated for testing on the new hardware platform to predict the performance of the target program on the new hardware platform.

[0150] In one embodiment, the simulation information includes: the instruction simulation transfer probability of the target program, and the simulated access linear address corresponding to the memory access instruction in the target program. In this embodiment, the simulation information determination module 1130 of the above device includes: an information reading unit, an instruction sequence determination unit, a transfer probability determination unit, and a simulated address selection unit.

[0151] The information reading unit is used to read the non-memory access instructions and the access linear addresses corresponding to the memory access instructions in the status information.

[0152] The instruction sequence determination unit is used to obtain the instruction sequence between two status information according to the non-memory access instructions corresponding to two adjacent status information.

[0153] The transfer probability determination unit is used to determine the instruction simulation transfer probability of the target program based on the instruction sequence.

[0154] The information reading unit is further used to: read the occurrence frequency of each access linear address.

[0155] The simulated address selection unit is used to select the simulated access linear address based on the occurrence frequency of each access linear address.

[0156] In one embodiment, the transfer probability determination unit of the above device includes: a combination determination subunit, which is used to obtain instruction jump combinations composed of two instructions according to the instruction sequence; a statistics subunit, which is used to count the occurrence times of each instruction jump combination in the instruction sequence; and a probability determination subunit, which is used to obtain the instruction simulation transfer probability of the target program based on the occurrence times of each instruction jump combination.

[0157] In one embodiment, the simulated address selection unit of the above device is further used to: select the access linear address with the highest occurrence frequency and determine it as the simulated access linear address.

[0158] In one embodiment, the test program generation module 1140 of the above device includes: a parsing unit, a replacement unit, an adding unit, and a program generation unit, where:

[0159] The parsing unit is configured to parse the target program to obtain the intermediate state of the target program;

[0160] The replacement unit is configured to replace the corresponding intermediate state information in the intermediate state based on the system call information and the simulation information to obtain the replaced program;

[0161] The adding unit is configured to add storage space initialization logic to the replaced program based on the simulated access linear address to obtain the intermediate state incorporating the simulation information;

[0162] The program generation unit is configured to generate a benchmark test program corresponding to the target program according to the intermediate state incorporating the simulation information.

[0163] In one embodiment, the instruction simulation transfer probability of the target program includes: the transfer probability of the conditional jump instruction; the replacement unit of the above device includes: an object determination subunit, configured to determine the replacement object of the conditional jump instruction according to the transfer probability of the conditional jump instruction; a replacement subunit, configured to replace the conditional jump instruction in the intermediate state with the replacement object of the conditional jump instruction.

[0164] In one embodiment, the instruction simulation transfer probability of the target program includes: the transfer probability of the function call instruction; in this embodiment, the replacement unit of the above device includes: an object determination subunit, configured to, if the target address of the function call instruction includes a dynamic target address, determine the replacement object of the function call instruction according to the dynamic target address; a replacement subunit, configured to replace the function call instruction in the intermediate state with the replacement object of the function call instruction.

[0165] In one embodiment, the instruction simulation transfer probability of the target program includes: the transfer probability of the function call instruction; in this embodiment, the replacement unit of the above device includes: an object determination subunit, configured to, if the target address of the function call instruction includes more than two dynamic target addresses, determine the replacement object of the function call instruction according to the transfer probability of the function call instruction and the dynamic target addresses; a replacement subunit, configured to replace the function call instruction in the intermediate state with the replacement object of the function call instruction.

[0166] In one embodiment, the replacement unit of the above device includes: an object determination subunit, which determines the replacement object of the memory access instruction; a replacement subunit, configured to replace the memory access instruction in the intermediate state with the replacement object of the memory access instruction.

[0167] In one embodiment, the replacement unit of the above device includes: an object determination subunit that determines the replacement object of the system call information; and a replacement subunit that replaces the system call information in the intermediate state with the replacement object of the system call information.

[0168] For the specific embodiments of the benchmark program generation device, reference may be made to the embodiments of the benchmark program generation method described above, which will not be elaborated here. Each module in the above benchmark program generation device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor in the computer device in hardware form or be independent of it, or be stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0169] In one embodiment, a computer device is provided. The computer device can be a server, and its internal structure diagram can be as Figure 12 shown. The computer device includes a processor, a memory, and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the basic test program. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it implements a benchmark program generation method.

[0170] Those skilled in the art can understand that Figure 12 the structure shown in

[0171] is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0172] In one embodiment, a computer-readable storage medium is provided, storing a computer program, and when the computer program is executed by a processor, it implements the steps in the above method embodiments.

[0173] In one embodiment, a computer program product or a computer program is provided. The computer program product or the computer program includes computer instructions that are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, causing the computer device to perform the steps in the above method embodiments.

[0174] Those of ordinary skill in the art can understand that all or part of the processes of implementing the methods in the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above method embodiments. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0175] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0176] The above embodiments only represent several implementation manners of this application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of the patent of this application should be subject to the appended claims.

Claims

1. A method for generating a benchmark program, characterized in that, The method includes: Obtain a target program to be tested; During the running of the target program, obtain status information and system call information associated with instructions; Analyze the status information to determine simulation information corresponding to the target program; Combine the target program with the simulation information and system call information to obtain a benchmark test program corresponding to the target program; The simulation information includes: the instruction simulation transfer probability of the target program, and the simulated access linear address corresponding to the memory access instruction in the target program; the analyzing the status information to determine the simulation information corresponding to the target program includes: reading the access linear addresses corresponding to non-memory access instructions and memory access instructions in the status information; obtaining an instruction sequence between two status information according to the non-memory access instructions corresponding to two adjacent status information; determining the instruction simulation transfer probability of the target program based on the instruction sequence; reading the occurrence frequency of each access linear address; selecting a simulated access linear address based on the occurrence frequency of each access linear address; The combining the target program with the simulation information and system call information to obtain a benchmark test program corresponding to the target program includes: parsing the target program to obtain an intermediate state of the target program; replacing corresponding intermediate state information in the intermediate state based on the system call information and simulation information to obtain a replaced program; adding storage space initialization logic to the replaced program based on the simulated access linear address to obtain an intermediate state with combined simulation information; generating a benchmark test program corresponding to the target program according to the intermediate state with combined simulation information.

2. The benchmark program generation method according to claim 1, wherein The determining the instruction simulation transfer probability of the target program based on the instruction sequence includes: Obtaining an instruction jump combination composed of two instructions according to the instruction sequence; Counting the occurrence times of each instruction jump combination in the instruction sequence; Obtaining the instruction simulation transfer probability of the target program based on the occurrence times of each instruction jump combination.

3. The benchmark program generation method according to claim 1, characterized in that, The selecting a simulated access linear address based on the occurrence frequency of each access linear address includes: Selecting the access linear address with the highest occurrence frequency and determining it as the simulated access linear address.

4. The benchmark program generation method according to claim 1, wherein Includes at least one of the following: The first item, The instruction simulation transfer probability of the target program includes: the transfer probability of a conditional jump instruction; the replacing corresponding intermediate state information in the intermediate state based on the system call information and simulation information includes: Determining a replacement object of the conditional jump instruction according to the transfer probability of the conditional jump instruction; Replacing the conditional jump instruction in the intermediate state with the replacement object of the conditional jump instruction; The second item, The instruction simulation transfer probability of the target program includes: the transfer probability of a function call instruction; The replacing corresponding intermediate state information in the intermediate state based on the system call information and simulation information includes: If the target address of the function call instruction includes a dynamic target address, determining a replacement object of the function call instruction according to the dynamic target address; Replace the function call instruction in the intermediate state with the replacement object of the function call instruction; Item 3, The instruction simulation transition probability of the target program includes: the transition probability of the function call instruction; Replacing the corresponding intermediate state information in the intermediate state based on the system call information and simulation information includes: If the target address of the function call instruction includes more than two dynamic target addresses, determine the replacement object of the function call instruction according to the transition probability of the function call instruction and the dynamic target addresses; Replace the function call instruction in the intermediate state with the replacement object of the function call instruction; Item 4, Replacing the corresponding intermediate state information in the intermediate state with the simulation information includes: Determine the replacement object of the memory access instruction; Replace the memory access instruction in the intermediate state with the replacement object of the memory access instruction; Item 5, Replacing the corresponding intermediate state information in the intermediate state with the simulation information includes: Determine the replacement object of the system call information; Replace the system call information in the intermediate state with the replacement object of the system call information.

5. The benchmark program generation method according to any one of claims 2 to 3, characterized in that, Obtaining the instruction sequence between two state information according to the non-memory access instructions corresponding to two adjacent state information includes: Use the first non-memory access instruction among the non-memory access instructions corresponding to two adjacent state information as the head non-memory access instruction, and the second non-memory access instruction among the non-memory access instructions corresponding to two adjacent state information as the tail non-memory access instruction; Try any instruction combination between the head non-memory access instruction and the tail non-memory access instruction to obtain the instruction sequence.

6. A benchmark program generation device, characterized in that, The device includes: A target program acquisition module, configured to acquire a target program to be tested; A state information acquisition module, configured to acquire state information and system call information associated with instructions during the running of the target program; A simulation information determination module, configured to analyze the state information to determine the simulation information corresponding to the target program; A test program generation module, configured to combine the target program with the simulation information and system call information to obtain a benchmark test program corresponding to the target program; The simulation information includes: the instruction simulation transition probability of the target program, the simulated access linear address corresponding to the memory access instruction in the target program; the simulation information determination module includes an information reading unit, an instruction sequence determination unit, a transition probability determination unit, and a simulated address selection unit, where: The information reading unit is configured to read the non-memory access instructions and the access linear addresses corresponding to the memory access instructions in the state information; The instruction sequence determination unit is configured to obtain the instruction sequence between two state information according to the non-memory access instructions corresponding to two adjacent state information; The transition probability determination unit is configured to determine the instruction simulation transition probability of the target program based on the instruction sequence; The information reading unit is further configured to: read the occurrence frequency of each access linear address; The analog address selection unit is used to select an analog access linear address based on the occurrence frequency of each of the access linear addresses; The test program generation module includes a parsing unit, a replacement unit, an adding unit, and a program generation unit, where: The parsing unit is used to parse the target program to obtain the intermediate state of the target program; The replacement unit is used to replace the corresponding intermediate state information in the intermediate state based on the system call information and the simulation information to obtain a replaced program; The adding unit is used to add storage space initialization logic to the replaced program based on the analog access linear address to obtain an intermediate state with merged simulation information; The program generation unit is used to generate a benchmark test program corresponding to the target program according to the intermediate state with merged simulation information.

7. The benchmark test program generation device according to claim 6, characterized in that, The simulation information determination module includes: A combination determination subunit, which is used to obtain an instruction jump combination composed of two instructions each from the instruction sequence; A statistics subunit, which is used to count the occurrence times of each instruction jump combination in the instruction sequence; A probability determination subunit, which is used to obtain the instruction simulation transfer probability of the target program based on the occurrence times of each instruction jump combination.

8. The benchmark program generation device according to claim 6, wherein The analog address selection unit is further used to: select the access linear address with the highest occurrence frequency as the analog access linear address.

9. The benchmark test program generation device according to claim 6, wherein Include at least one of the following: The first item, The instruction simulation transfer probability of the target program includes: the transfer probability of a conditional jump instruction; the replacement unit includes: An object determination subunit, which is used to determine the replacement object of the conditional jump instruction according to the transfer probability of the conditional jump instruction; A replacement subunit, which is used to replace the conditional jump instruction in the intermediate state with the replacement object of the conditional jump instruction; The second item, The instruction simulation transfer probability of the target program includes: the transfer probability of a function call instruction; The replacement unit includes: An object determination subunit, which is used to, if the target address of the function call instruction includes a dynamic target address, determine the replacement object of the function call instruction according to the dynamic target address; A replacement subunit, which is used to replace the function call instruction in the intermediate state with the replacement object of the function call instruction; The third item, The instruction simulation transfer probability of the target program includes: the transfer probability of a function call instruction; The replacement unit includes: An object determination subunit, which is used to, if the target address of the function call instruction includes more than two dynamic target addresses, determine the replacement object of the function call instruction according to the transfer probability of the function call instruction and the dynamic target address; A replacement subunit, which is used to replace the function call instruction in the intermediate state with the replacement object of the function call instruction; The fourth item, The replacement unit includes: An object determination subunit, which is used to determine the replacement object of the storage access instruction; A replacement subunit, which is used to replace the storage access instruction in the intermediate state with the replacement object of the storage access instruction; The fifth item, The replacement unit includes: An object determination subunit, configured to determine a replacement object for the system call information; A replacement subunit, configured to replace the system call information in the intermediate state with the replacement object of the system call information.

10. The benchmark test program generation device according to any one of claims 7 to 8, characterized in that The instruction sequence determination unit is specifically configured to: Use the first non-memory access instruction among the non-memory access instructions corresponding to two adjacent state information as the head non-memory access instruction, and use the second non-memory access instruction among the non-memory access instructions corresponding to two adjacent state information as the tail non-memory access instruction; Try any instruction combination between the head non-memory access instruction and the tail non-memory access instruction to obtain the instruction sequence.

11. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

12. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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