A method and system for accurate reduction of passive parasitic parameter networks

Abstract

The application provides a precise simplification method and system of a passive parasitic parameter network. The method comprises the following steps: obtaining a passive parameter parasitic network of a to-be-processed circuit; obtaining device information of all parasitic parameters; labeling node names of active device ports according to an active device naming rule; if a current parasitic parameter crosses multiple active device ports, deleting the current parasitic parameter; if a branch where the current parasitic parameter is located is an open circuit, deleting the branch and the parasitic parameters thereon; after traversing all parasitic parameters, obtaining a precise passive parasitic parameter network; and performing order reduction processing on the precise passive parasitic parameter network to obtain a simplified passive parasitic parameter network. The method precisely processes the passive parasitic parameter network, excludes active device ports and invalid ports, so that the passive parasitic parameter network can be correctly processed during simplification and order reduction processing, and the efficiency and accuracy of the order reduction and simplification processing are improved due to the exclusion of invalid paths.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a precise simplification method and system for passive parasitic parameter networks. Background Technology

[0002] In integrated circuit design, parasitic parameters are numerous, primarily arising from: resistance, inductance, and capacitance introduced by devices or circuit boards; capacitance formed between parallel conductors; inductance, capacitance, and resistance inherent in the devices themselves; and coupling effects created by neatly arranged inductors. Parasitic parameters are unavoidable in integrated circuit design. These parasitic parameters can be equivalently represented using passive devices (capacitors, resistors, and inductors). Devices equivalent to these parasitic parameters are called parasitic devices. A network composed of parasitic parameters is called a passive parasitic parameter network.

[0003] Because the parasitic parameters in integrated circuits are highly distributed, direct extraction leads to complex parasitic parameter netlists and long simulation times. Therefore, without affecting overall performance, passive parasitic parameter networks can be simplified, and high-order networks can be simplified to low-order networks without compromising the rationality of the simulation.

[0004] However, current methods for reducing the order of passive parasitic parameter networks can easily introduce invalid ports or ports of active devices, such as the gate, source, or drain of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). This leads to invalid operations during the reduction and simplification process, resulting in very low efficiency and even errors. Summary of the Invention

[0005] To address the problem that current methods for simplifying passive parasitic parameter networks often introduce invalid ports or ports of active devices, leading to inefficient operations, low efficiency, or even errors, this application provides a precise simplification method and system for passive parasitic parameter networks.

[0006] The first aspect of this application provides a method for accurately simplifying a passive parasitic parameter network, comprising: obtaining the passive parasitic parameter network of the circuit to be processed; obtaining device information corresponding to all parasitic parameters in the passive parasitic parameter network, wherein the device information includes the node name of the device port corresponding to the parasitic parameter; labeling the node name of the active device port in the passive parasitic parameter network according to the active device naming rules; performing the following operations sequentially on all parasitic parameters: determining whether the current parasitic parameter is the first parasitic parameter, wherein the first parasitic parameter is a parasitic parameter that spans multiple active device ports; if the current parasitic parameter is the first parasitic parameter, deleting the current parasitic parameter to obtain an intermediate passive parasitic parameter network; determining whether the branch where the current parasitic parameter is located is an open circuit after deleting the current parasitic parameter; if the branch where the current parasitic parameter is located is an open circuit after deleting the current parasitic parameter, deleting the branch where the current parasitic parameter is located and the parasitic parameter on the branch from the intermediate passive parasitic parameter network; traversing all parasitic parameters and reducing the order of the accurately simplified passive parasitic parameter network to obtain the simplified passive parasitic parameter network.

[0007] In some embodiments, determining whether the current parasitic parameter is a first parasitic parameter includes: determining whether the current parasitic parameter is a first parasitic parameter based on the node name in the device information of the current parasitic parameter; wherein, if at least two node names in the device information of the current parasitic parameter match the node names of the active device ports, then the current parasitic parameter is a first parasitic parameter.

[0008] In some embodiments, obtaining the passive parasitic network of the circuit to be processed includes: obtaining the layout post-simulation file of the circuit to be processed and the schematic diagram of the circuit to be processed; and obtaining the passive parasitic network of the circuit to be processed from the layout post-simulation file according to the schematic diagram.

[0009] In some embodiments, the naming rules for active devices are obtained by: obtaining the corresponding process documents based on the layout simulation file; and obtaining the naming rules for active devices based on the process documents.

[0010] In some embodiments, the process of reducing the order of the accurate passive parasitic parameter network includes: matrixing the accurate passive parasitic parameter network using the MNA circuit formula to obtain a first matrix; calculating the input and output impedance matrices corresponding to the accurate passive parasitic parameter network based on the first matrix; and obtaining a simplified passive parasitic parameter network using the Arnoldi algorithm based on the input and output impedance matrices and the target order.

[0011] A second aspect of this application provides a precise simplification apparatus for passive parasitic parameter networks, comprising: an acquisition unit, a storage unit, a precision unit, and a reduction unit; wherein the acquisition unit is used to acquire the passive parasitic parameter network of the circuit to be processed; the storage unit is used to acquire device information corresponding to all parasitic parameters in the passive parasitic parameter network, the device information including the node name of the device port corresponding to the parasitic parameter; the precision unit is configured to sequentially perform the following operation on all parasitic parameters: according to the active device naming rules, determine whether the current parasitic parameter is the first parasitic parameter, wherein the first... Parasitic parameters are parasitic parameters that span multiple active device ports. If the current parasitic parameter is the first parasitic parameter, the device corresponding to the current parasitic parameter is deleted to obtain an intermediate passive parasitic parameter network. It is determined whether the branch where the current parasitic parameter is located is an open circuit. If the branch where the current parasitic parameter is located is an open circuit, the branch where the current parasitic parameter is located is deleted from the intermediate passive parasitic parameter network. After traversing all parasitic parameters, the accurate passive parasitic parameter network is obtained. The order reduction unit is used to reduce the order of the accurate passive parasitic parameter network to obtain a simplified passive parasitic parameter network.

[0012] In some embodiments, when determining whether the current parasitic parameter is the first parasitic parameter, the precision unit is configured to: determine whether the current parasitic parameter is the first parasitic parameter based on the node name in the device information of the current parasitic parameter; wherein, if at least two node names in the device information of the current parasitic parameter match the node names of the active device port, then the current parasitic parameter is the first parasitic parameter.

[0013] In some embodiments, the acquisition unit includes a first acquisition module, a second acquisition module, and a positioning module; wherein, the first acquisition module is used to acquire the layout post-simulation file of the circuit to be processed; the second acquisition module is used to acquire the schematic diagram of the circuit to be processed; and the positioning module is used to acquire the passive parasitic network of the circuit to be processed from the layout post-simulation file according to the schematic diagram.

[0014] In some embodiments, the precision simplification system further includes a naming rule unit; wherein the naming rule acquisition unit is used to obtain the corresponding process file based on the layout simulation file, and to obtain the active device naming rule based on the process file.

[0015] In some embodiments, the order reduction unit includes a matrixing module, an impedance calculation module, and an order reduction module; wherein, the matrixing module is used to matrixify the accurate passive parasitic parameter network using the MNA circuit formula to obtain a first matrix; the impedance calculation module is used to calculate the input and output impedance matrices corresponding to the accurate passive parasitic parameter network based on the first matrix; and the order reduction module is used to obtain a simplified passive parasitic parameter network based on the input and output impedance matrices and the target order using the Arnoldi algorithm.

[0016] This application provides a precise and simplified method and system for passive parasitic parameter networks. The method includes acquiring the passive parasitic parameter network of the circuit to be processed; acquiring device information corresponding to all parasitic parameters in the passive parasitic parameter network, the device information including the node name of the device port corresponding to the parasitic parameter; labeling the node name of the active device port in the passive parasitic parameter network according to the active device naming rules; and performing the following operations sequentially on all the parasitic parameters: determining whether the current parasitic parameter is the first parasitic parameter, wherein the first parasitic parameter is a parasitic parameter that spans multiple active device ports; if the current parasitic parameter is the first parasitic parameter... If the parasitic parameter is removed, an intermediate passive parasitic parameter network is obtained. It is then determined whether the branch containing the current parasitic parameter is open-circuited after deletion. If so, the branch containing the current parasitic parameter and the parasitic parameter on that branch are removed from the intermediate passive parasitic parameter network. After traversing all parasitic parameters, a precise passive parasitic parameter network is obtained. The precise passive parasitic parameter network is then reduced in order to obtain a simplified passive parasitic parameter network. This method refines the passive parasitic parameter network by excluding active device ports and invalid ports, ensuring correct simplification and reduction of the passive parasitic parameter network. Furthermore, by eliminating invalid paths, the efficiency of the simplification and reduction process is improved. Attached Figure Description

[0017] Figure 1 Here is an example of the schematic diagram of the circuit to be processed;

[0018] Figure 2 This is an example schematic diagram from the layout simulation file of the circuit to be processed.

[0019] Figure 3 This is a schematic diagram of the passive parasitic parameter network corresponding to the circuit to be processed;

[0020] Figure 4 A schematic diagram illustrating the workflow of a precise and simplified method for passive parasitic parameter networks provided in this application embodiment;

[0021] Figure 5 An example schematic diagram illustrating a precise simplification method for obtaining an intermediate passive parasitic parameter network, as provided in this application embodiment;

[0022] Figure 6 A schematic diagram illustrating an example of the accurate passive parasitic parameter network obtained by the accurate simplification method for a passive parasitic parameter network provided in this application embodiment;

[0023] Figure 7This is an example schematic diagram of the simplified passive parasitic parameter network obtained by a precise simplification method for a passive parasitic parameter network provided in an embodiment of this application. Detailed Implementation

[0024] The terms "first," "second," "third," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar or related objects or entities, and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms are interchangeable where appropriate.

[0025] See Figure 1 This is a schematic example of a circuit to be processed. Device 1 and Device 2 are directly connected by a wire net01. However, a real wire will have parameters such as resistance and / or capacitance. In the post-layout simulation file, the wire can be represented as a network composed of many small capacitors and resistors. See [link to schematic]. Figure 2 R1-R10 and C1-C10 are parasitic parameters introduced by the wire net01. In addition, the device itself also has parasitic parameters. See [link to documentation]. Figure 2 C01-C02 and R0 are parasitic parameters introduced by device 1 and device 2 themselves.

[0026] See Figure 3 ,for Figure 1 The passive parasitic parameter network corresponding to the circuit to be processed is shown. Port1 and port2 are two ports of the passive parasitic parameter network of the circuit to be processed. See also... Figure 2 The port node names of device 1 are p1d (drain), p1b (body), p1s (source), and p1g (gate). The port node names of device 2 are p2d (drain), p2b (body), p2s (source), and p2g (gate).

[0027] To address the problem that current passive parasitic parameter networks (LPNs) are prone to introducing invalid ports or ports of active devices during the reduction and simplification process, leading to invalid operations, very low reduction and simplification efficiency, or even errors, this application provides a precise simplification method and system for LPNs through the following embodiments.

[0028] See Figure 4 The present application provides a precise simplification method for a passive parasitic parameter network, which includes steps 101-107.

[0029] Step 101: Obtain the passive parasitic network of the circuit to be processed.

[0030] In some embodiments, the layout file of the circuit to be processed is obtained, and the schematic diagram of the circuit to be processed is obtained; based on the schematic diagram, the passive parasitic parameter network of the circuit to be processed is obtained from the layout file.

[0031] In one implementation, the Cadence Virtuoso file is used, selecting the calibre file "netlist.gds" corresponding to the layout of the circuit to be processed, and the file "input.scs" corresponding to the schematic of the circuit to be processed. In this application, the schematic corresponding to the circuit to be processed can be selected or annotated in the schematic visualization interface. Based on the devices connected in the schematic, the corresponding passive parasitic parameter network in the post-layout simulation file is determined.

[0032] Cadence is a leading vendor in the EDA (Electronic Design Automation) industry, and one of the three giants of EDA (Cadence, Synopsys, and Mentor Graphics). Its numerous EDA tools hold a leading position in the industry for the design and verification of IC integrated circuit chips and PCB circuit boards. The Cadence Virtuoso system design platform is a system-based holistic solution that provides the ability to drive IC and package simulation from a single schematic to clean LVS (Layout Versus Schematic) layout. It has two main functions: implementation and analysis. The implementation workflow involves creating an IC package schematic using the Virtuoso Schematic Editor, then transferring the schematic to Cadence SiP Layout for physical placement. In addition, it can generate and verify library cells, output a BOM (bill of materials), and perform LVS verification (Layout Versus Schematic checking). The analysis workflow involves extracting and simulating any part of the system (IC-package-PCB) at any layout state. Furthermore, it can automatically generate schematics for PCB and IC package layout, and bind packages to IC models or schematics using Virtuoso ADE Product Suite and The Multi-Mode Simulation interface builds testbenches to simulate the system. The Cadence Sigrity model extracted from the PCB and IC package layout is automatically matched to the generated schematic.

[0033] Step 102: Obtain device information corresponding to all parasitic parameters in the passive parameter parasitic network. The device information includes the node name of the device port corresponding to the parasitic parameter.

[0034] After determining the layout and replicating the corresponding passive parasitic parameter network in the file, the passive parasitic parameter network is read. This involves saving the number of nodes in the passive parasitic parameter network, the name of each node, the type of each parasitic parameter (e.g., capacitance or resistance), the corresponding value of the parasitic parameter, and the connection method. For example, the saving method can be a Python list format as shown in the code. Figure 3 For example, the following information needs to be saved: node names such as "net02" and "net03", the total number of nodes (the length of the list is the total number of nodes, which can be read through Python code), and device information for each parasitic parameter. Taking R1 as an example, its storage format in the list is ['p1g','net03','r','1.3']. The first two items are the names of the nodes it connects to, the third item is its type ('c' for capacitors), and its resistance value (1.3Ω). Taking C01 as an example, its storage format in the list is ['p1d','p1g','c','1.6p'].

[0035] Step 103: According to the naming rules for active devices, mark the node names of the active device ports in the passive parameter parasitic network.

[0036] In some embodiments, the active device naming rules are obtained by the following method: obtaining the layout simulation file of the circuit to be processed; obtaining the corresponding process file based on the layout simulation file; and obtaining the active device naming rules based on the process file.

[0037] In one implementation, the location of the process file described in the "input.scs" file is identified. For example, the process file location is "pdk_path / ... / models / spectre / xxx.lib". The naming rules of active devices under this process are read from the "input.scs" file. Based on the active device naming rules, the port node names of the active devices in the layout simulation file can be identified, and it can be further identified whether the parasitic parameters in the passive parasitic parameter network include active port node names.

[0038] Step 104: Determine whether the current parasitic parameter is the first parasitic parameter, wherein the first parasitic parameter is a parasitic parameter that spans multiple active device ports.

[0039] In some embodiments, it is determined whether the current parasitic parameter is a first parasitic parameter based on the node name in the device information of the current parasitic parameter; wherein, if at least two node names in the device information of the current parasitic parameter match the node name of the active device port, then the current parasitic parameter is a first parasitic parameter.

[0040] For example, if both node names in the device information of a parasitic parameter in a passive parasitic parameter network are active device port node names, then the parasitic parameter is determined to be a parasitic parameter that spans multiple active device ports, i.e., the first parasitic parameter. Figure 2 In this context, parasitic parameters C01, C02, and R0 are the first parasitic parameters.

[0041] Step 105: If the current parasitic parameter is the first parasitic parameter, then delete the current parasitic parameter to obtain an intermediate passive parasitic parameter network.

[0042] In the passive parasitic parameter network, parasitic parameters that are determined to span active devices are deleted. For example, when deleting the first parasitic parameter C01, C01 is deleted from the list storing device information.

[0043] In some embodiments, if the current parasitic parameter is not the first parasitic parameter and the current parasitic parameter is not the last parasitic parameter, then the determination of whether the next parasitic parameter is the first parasitic parameter continues.

[0044] Step 106: Determine whether the branch containing the current parasitic parameter is an open circuit after deleting the current parasitic parameter.

[0045] Step 107: If the branch containing the current parasitic parameter is disconnected after deleting the current parasitic parameter, then delete the branch containing the current parasitic parameter and the parasitic parameter on the branch from the intermediate passive parasitic parameter network.

[0046] In one implementation, after deleting C01, it is determined whether there are other devices with parasitic parameters on the nodes corresponding to the two ports previously connected to C01.

[0047] If there is no device or only one device, the first branch between the two ports is an open circuit, and this first branch is deleted. An example of a case where the first branch is an open circuit is given. See [link to example]. Figure 5 This is a schematic diagram of an example of an intermediate passive parasitic parameter network. From Figure 5 As can be seen, only R0 is connected to the node to the left of R0, so the device corresponding to R0 is open-circuited and needs to be deleted. Next, we check C02, which is connected to R0. Since the node above C02 is only connected to C02, C02 also needs to be deleted, and so on. It should be noted that... Figure 5 Device 2, corresponding to port 1, is a passive device. R0 and C02 are not the first parasitic parameters. The open circuit is caused by the deletion of the first parasitic parameter C01.

[0048] If there are two or more devices on the nodes corresponding to the two ports previously connected to C01, or if this node is a port of an active device, then this node is not yet disconnected and no further action is required. An example is given of a specific case where the first branch is not disconnected. For example... Figure 5 Although R1 in the diagram only has one device, R7, connected to its left node, its left side is a port, so it does not need to be deleted. As another example, Figure 5 R10 and C10 in the diagram have two devices connected to their right nodes (R10 and C10), and the nodes are also connected to the port, so they do not need to be deleted.

[0049] In some embodiments, if the branch containing the current parasitic parameter is not disconnected after the current parasitic parameter is deleted, and the current parasitic parameter is not the last parasitic parameter, then the determination of whether the next parasitic parameter is the first parasitic parameter continues.

[0050] Step 108: After traversing all the parasitic parameters, the accurate passive parasitic parameter network is obtained.

[0051] Repeat steps 104-107 above until all parasitic parameters have been traversed. After deleting all devices corresponding to the first parasitic parameter in the network and the devices whose branches become open circuits as a result, organize the device information of the passive parasitic parameters of the remaining nodes to obtain the accurate passive parasitic parameter network, i.e. Figure 6 The dashed box portion in the document. In one implementation, the list corresponding to the refined passive parasitic parameter network is output and saved as "document".

[0052] Step 109: Reduce the order of the accurate passive parasitic parameter network to obtain a simplified passive parasitic parameter network. Figure 6 The order of the refined passive parasitic parameter network shown is 10. For example, the order is reduced from 10 to 4. It should be noted that the order of reduction is determined based on simulation requirements. Generally, a smaller order results in faster simulation speed but less accurate results; a larger order results in more accurate simulation results but slower simulation speed.

[0053] In some embodiments, the order reduction processing of the accurate passive parasitic parameter network in step 107 includes steps 201-203.

[0054] Step 201: Matrix the precise passive parasitic parameter network using the MNA circuit formula to obtain the first matrix. In one implementation, the first matrix A is established by substituting the MNA (Modified Nodal Analysis) circuit formula into the parasitic parameter netlist. Specifically: if the circuit has N nodes and M ports, then a (N+M)×(N+M) matrix A is constructed, consisting of smaller submatrices G, B, C, and D. Where G is of size N×N, it records the conductivity properties of the accurate passive parasitic parameter network; B and C are of size N×M and M×N respectively, and record the connection of voltage sources in the accurate passive parasitic parameter network; D is of size M×M, and is a zero matrix when only independent sources are considered.

[0055] Step 202: Calculate the input-output impedance matrix corresponding to the refined passive parasitic parameter network based on the first matrix. In one implementation, the input-output admittance of each port in the refined passive parasitic parameter network is calculated based on the first matrix A and the Laplace matrix L, denoted as Y. (s) Specifically, since the input admittance represents the presence of capacitance, and the impedance of the capacitance is frequency-dependent, the input and output admittance expressions include the variable 's'. For example, if the network is a 10-node, 4-port network, a 14×14 matrix A can be obtained according to the MNA circuit formula, and the Laplace matrix L can be calculated using the formula Y. (s) =L T AL performs calculations to obtain a 4×4 input / output impedance matrix Y. (s) .

[0056] Step 203: Based on the input / output impedance matrix and the target order, the Arnoldi algorithm is used to obtain the simplified passive parasitic parameter network. In one implementation, the target order i to be reduced by the user is read, and the target order i should not be greater than the original order j of the parasitic parameter network. For example, if the original order of the parasitic parameter network is 10, then the order to be reduced by the user should not be greater than 10. The input / output impedance matrix Y of the parasitic parameter network is then adjusted according to the target order i. (s) A reduction process is performed. The extracted matrix A is simplified using the Arnoldi algorithm. Specifically, the Krylov subspace of matrix A is solved, and based on the reduction requirement (i.e., the order to be reduced), a dimension-reduced orthogonal solution is found within the Krylov subspace. This dimension-reduced orthogonal solution is then compared with matrix Y. (s) Calculations are performed to obtain the reduced-order matrix.

[0057] For example, if the original passive parasitic parameter network has an input-output impedance of 10th order RC network and the target order is 4th order, then we solve for the 4th order Krylov subspace of matrix A, find the dimension-reduced orthogonal solution X in the 4th order Krylov subspace, and then combine the dimension-reduced orthogonal solution with matrix Y. (s) According to the formula Calculations are performed to obtain the reduced-order matrix. in This is one way to represent a passive parasitic parameter network. The reduced-order passive parasitic parameter network is output and saved for future use.

[0058] For example, see Figure 7 This is a schematic diagram of the simplified passive parasitic parameter network. The output includes simplified parasitic parameters such as "R_1" and "C_1", as well as simplified names of each node, such as "net_02" and "net_03", and the results are saved as "simplified_net".

[0059] The above embodiments provide a method for accurately simplifying a passive parasitic parameter network, including obtaining the passive parasitic parameter network of the circuit to be processed; determining the first parasitic parameter in the passive parasitic parameter network according to the naming rules of active devices; deleting the first parasitic device from the passive parasitic parameter network to obtain an intermediate passive parasitic parameter network; determining whether the first branch is an open circuit; if the first branch is an open circuit, deleting the first branch from the passive parasitic parameter network to obtain an accurate passive parasitic parameter network; and reducing the order of the accurate passive parasitic parameter network to obtain a simplified passive parasitic parameter network. The method first performs accurate processing on the passive parasitic parameter network, eliminating active device ports and invalid ports, ensuring that the simplification and reduction processing of the passive parasitic parameter network can be performed correctly, and improving the efficiency of the reduction and simplification processing because invalid paths are eliminated.

[0060] Corresponding to the aforementioned embodiments of the precise simplification method for passive parasitic parameter networks, this application also provides embodiments of a precise simplification system for passive parasitic parameter networks. The precise simplification system includes: an acquisition unit, a storage unit, a precision unit, and a reduction unit.

[0061] The acquisition unit is used to acquire the passive parameter parasitic network of the circuit to be processed.

[0062] The storage unit is used to obtain device information corresponding to all parasitic parameters in the passive parameter parasitic network, and the device information includes the node name of the device port corresponding to the parasitic parameter.

[0063] The precision unit is configured as follows:

[0064] Perform the following operations sequentially on all the parasitic parameters:

[0065] According to the naming rules of active devices, it is determined whether the parasitic parameter is the first parasitic parameter, wherein the first parasitic parameter is a parasitic parameter that spans multiple active device ports;

[0066] If the parasitic parameter is the first parasitic parameter, then delete the device corresponding to the parasitic parameter to obtain an intermediate passive parasitic parameter network;

[0067] Determine whether the branch containing the parasitic parameter is an open circuit;

[0068] If the branch where the parasitic parameter is located is open, then the branch where the parasitic parameter is located is deleted from the intermediate passive parasitic parameter network.

[0069] After traversing all the parasitic parameters, the accurate passive parasitic parameter network is obtained;

[0070] The order reduction unit is used to reduce the order of the accurate passive parasitic parameter network to obtain a simplified passive parasitic parameter network.

[0071] In some embodiments, when determining whether the current parasitic parameter is a first parasitic parameter, the precision unit is configured to: determine whether the current parasitic parameter is a first parasitic parameter based on the node name in the device information of the current parasitic parameter; wherein, if at least two node names in the device information of the current parasitic parameter match the node name of the active device port, then the current parasitic parameter is a first parasitic parameter.

[0072] In some embodiments, the acquisition unit includes a first acquisition module, a second acquisition module, and a positioning module; wherein, the first acquisition module is used to acquire the layout post-simulation file of the circuit to be processed; the second acquisition module is used to acquire the schematic diagram of the circuit to be processed; and the positioning module is used to acquire the passive parasitic network of the circuit to be processed from the layout post-simulation file according to the schematic diagram.

[0073] In some embodiments, the precise simplification system further includes a naming rule unit; wherein the naming rule acquisition unit is used to obtain the corresponding process file based on the layout simulation file, and to obtain the active device naming rule based on the process file.

[0074] In some embodiments, the order reduction unit includes a matrixing module, an impedance calculation module, and an order reduction module; wherein, the matrixing module is used to matrixify the accurate passive parasitic parameter network using the MNA circuit formula to obtain a first matrix; the impedance calculation module is used to calculate, based on the first matrix, the input and output impedance matrices corresponding to the accurate passive parasitic parameter network; and the order reduction module is used to obtain the simplified passive parasitic parameter network using the Arnoldi algorithm based on the input and output impedance matrices and the target order.

[0075] The effects of the above system in application can be found in the description of the precise simplification method embodiment of the aforementioned passive parasitic parameter network, and will not be repeated here.

[0076] It should be understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0077] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0078] The same or similar parts between the various embodiments of this specification can be referred to mutually. Each embodiment focuses on the differences from other embodiments. In particular, for system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and relevant parts can be referred to the description in the method embodiment section. Those skilled in the art will clearly understand that the technology in the embodiments of this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of this application, in essence or the parts that contribute to the prior art, can be embodied in the form of software products. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application or some parts of the embodiments. The above-described embodiments of this application do not constitute a limitation on the scope of protection of this application.

Claims

1. A method of accurate reduction of a passive parasitic parameter network, characterized in that, The method comprises the following steps: Obtain the passive parameter parasitic network of the circuit to be processed; Obtain the device information corresponding to all parasitic parameters in the passive parameter parasitic network, wherein the device information comprises the node name of the device port corresponding to the parasitic parameter; According to the active device naming rule, mark the node name of the active device port in the passive parameter parasitic network; In sequence, perform the following operations on all the parasitic parameters: Determine whether the current parasitic parameter is the first parasitic parameter, wherein the first parasitic parameter is a parasitic parameter across multiple active device ports; If the current parasitic parameter is the first parasitic parameter, delete the current parasitic parameter to obtain an intermediate passive parasitic parameter network; Determine whether the branch in which the current parasitic parameter is located is an open circuit after the current parasitic parameter is deleted; If the branch in which the current parasitic parameter is located is an open circuit after the current parasitic parameter is deleted, delete the branch in which the current parasitic parameter is located and the parasitic parameters on the branch from the intermediate passive parasitic parameter network; After traversing all the parasitic parameters, obtain a refined passive parasitic parameter network; Reduce the order of the refined passive parasitic parameter network to obtain a simplified passive parasitic parameter network; The method for obtaining the passive parameter parasitic network of the circuit to be processed comprises the following steps: Obtain the post-layout simulation file of the circuit to be processed and the schematic diagram of the circuit to be processed; According to the schematic diagram, obtain the passive parameter parasitic network of the circuit to be processed from the post-layout simulation file; The active device naming rule is obtained by the following method: Obtain the corresponding process file according to the post-layout simulation file; Obtain the active device naming rule according to the process file.

2. The method of claim 1, wherein, The method for determining whether the current parasitic parameter is the first parasitic parameter comprises the following steps: According to the node name in the device information of the current parasitic parameter, determine whether the current parasitic parameter is the first parasitic parameter; If at least two node names in the device information of the current parasitic parameter meet the node name of the active device port, the current parasitic parameter is the first parasitic parameter.

3. The method of claim 1, wherein, The method for reducing the order of the refined passive parasitic parameter network comprises the following steps: Matrix the refined passive parasitic parameter network by using the MNA circuit formula to obtain a first matrix; According to the calculation of the first matrix, obtain the input-output impedance matrix corresponding to the refined passive parasitic parameter network; According to the input-output impedance matrix and the target order, obtain the simplified passive parasitic parameter network by using the Arnoldi algorithm.

4. A system for accurate reduction of passive parasitic parameter networks, characterized by The method comprises the following steps: An obtaining unit, a storage unit, a precision unit and a reduction unit are provided, wherein: The obtaining unit is configured to obtain the passive parameter parasitic network of the circuit to be processed; The storage unit is configured to obtain the device information corresponding to all parasitic parameters in the passive parameter parasitic network, wherein the device information comprises the node name of the device port corresponding to the parasitic parameter; The precision unit is configured to: In sequence, perform the following operations on all the parasitic parameters: According to an active device naming rule, it is judged whether the current parasitic parameter is a first parasitic parameter, wherein the first parasitic parameter is a parasitic parameter across multiple active device ports; If the current parasitic parameter is the first parasitic parameter, a device corresponding to the current parasitic parameter is deleted, and an intermediate passive parasitic parameter network is obtained; It is judged whether a branch in which the current parasitic parameter is located is an open circuit; If the branch in which the current parasitic parameter is located is an open circuit, the branch in which the current parasitic parameter is located is deleted from the intermediate passive parasitic parameter network; After all the parasitic parameters are traversed, a refined passive parasitic parameter network is obtained; The order reduction unit is configured to perform order reduction processing on the refined passive parasitic parameter network, and obtain a simplified passive parasitic parameter network; The obtaining unit comprises a first obtaining module, a second obtaining module, and a positioning module; wherein The first obtaining module is configured to obtain a post-layout simulation file of a to-be-processed circuit; The second obtaining module is configured to obtain a schematic diagram of the to-be-processed circuit; The positioning module is configured to obtain the passive parasitic network of the to-be-processed circuit from the post-layout simulation file according to the schematic diagram; The precision simplification system further comprises a naming rule unit; wherein The naming rule obtaining unit is configured to obtain a corresponding process file according to the post-layout simulation file, and obtain the active device naming rule according to the process file.

5. The system for accurate reduction of passive parasitic parameter networks according to claim 4, wherein, When judging whether the current parasitic parameter is the first parasitic parameter, the precision unit is configured to: According to a node name in device information of the current parasitic parameter, it is judged whether the current parasitic parameter is the first parasitic parameter; If at least two node names in the device information of the current parasitic parameter conform to a node name of an active device port, the current parasitic parameter is the first parasitic parameter.

6. The system for accurate reduction of passive parasitic parameter networks according to claim 4, wherein, The order reduction unit comprises a matrixing module, an impedance calculation module, and an order reduction module; wherein The matrixing module is configured to matrix the refined passive parasitic parameter network using an MNA circuit formula, and obtain a first matrix; The impedance calculation module is configured to calculate an input-output impedance matrix corresponding to the refined passive parasitic parameter network according to the first matrix; The order reduction module is configured to obtain the simplified passive parasitic parameter network by using the Arnoldi algorithm according to the input-output impedance matrix and a target order.

Images