Method for forming a memory device

Abstract

A method for forming a memory device includes providing a substrate; forming a select gate structure on a portion of the substrate, the select gate structure including a select gate and a first hard mask layer on top of the select gate; forming two memory gate structures on sidewalls of the select gate structure, the two memory gate structures being symmetrically distributed about a central axis of the select gate structure, each of the memory gate structures including a memory gate, a top surface of the memory gate being higher than a top surface of the select gate; removing the first hard mask layer to form an opening between the two memory gate structures; and forming a first sidewall on exposed sidewalls of the two memory gate structures, the first sidewall facilitating isolation of the memory gate from the select gate and reducing leakage between the memory gate and the select gate.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a memory device. Background Art

[0002] Non-volatile memory, as an essential storage device in computers, plays a crucial role in storing the information being processed. SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory, based on the highly insulating silicon nitride storage medium, has attracted attention for its superior charge storage capacity, ease of miniaturization, and simplified manufacturing compared to traditional polysilicon floating-gate memory. SONOS devices replace the traditional polysilicon charge storage layer with a charge-trapping silicon nitride layer. Because they store charge using trapped charges, the stored charge is discretely distributed. This eliminates the need for significant leakage currents, significantly improving reliability.

[0003] With the continuous development of semiconductor technology, it is imperative to reduce the size of memory cells. However, this size reduction may lead to more serious problems such as reliability failure and low programming efficiency.

[0004] Therefore, the performance of SONOS devices formed by existing technologies needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a memory device to improve the performance of the formed SONOS device.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a memory device, comprising: providing a substrate; forming a selection gate structure on a portion of the substrate, the selection gate structure including a selection gate and a first hard mask layer located on top of the selection gate; forming two storage gate structures symmetrically distributed with respect to the central axis of the selection gate structure on the sidewalls of the selection gate structure, each of the storage gate structures including a storage gate, and the top surface of the storage gate being higher than the top surface of the selection gate; removing the first hard mask layer to form an opening between the two storage gate structures; and forming a first sidewall on the two storage gate structure sidewalls exposed by the opening.

[0007] Optionally, the selection gate structure and the two storage gate structures are used as a storage unit; before removing the first hard mask layer and after forming the two storage gate structures, the method also includes: injecting first doping ions into the substrate on both sides of the storage unit to form a first source and drain layer.

[0008] Optionally, the substrate includes a storage area and a logic area, and the selection gate structure and the storage gate structure are located in the storage area; the method further includes: after forming the first source and drain layer, forming a logic gate on the logic area.

[0009] Optionally, a storage well region is provided in the storage area, and a logic well region is provided in the logic area; a method for forming the storage well region and the logic well region includes: forming a pad oxide layer on the substrate before forming a select gate structure; forming a third mask layer on the pad oxide layer, the third mask layer exposing the storage area and the logic area; and using the third mask layer as a mask, injecting second doping ions into the substrate to form the storage well region and the logic well region.

[0010] Optionally, the method for forming the selection gate structure and the logic gate includes: forming a selection gate material layer and a hard mask material layer located on the selection gate material layer on the substrate; patterning the hard mask material layer on the storage area to form the first hard mask layer; etching the selection gate material layer using the first hard mask layer as a mask to form the selection gate; after forming the first source and drain layer, patterning the hard mask material layer on the logic area to form a second hard mask layer; etching the selection gate material layer using the second hard mask layer as a mask until the substrate surface is exposed to form the logic gate.

[0011] Optionally, after forming the logic gate, the method further includes: forming a second source and drain layer in the substrate on both sides of the logic gate.

[0012] Optionally, the method for forming the second source and drain layer includes: forming a fourth mask layer on the substrate, the surface of the storage unit and the surface of the logic gate, the fourth mask layer exposing the surface of the logic area on both sides of the logic gate; using the fourth mask layer as a mask, injecting third doping ions into the logic area to form the second source and drain layer.

[0013] Optionally, before forming the second source and drain layer, a second sidewall is formed on the sidewall of the logic gate; the method also includes: using the fourth mask layer as a mask, injecting fourth doping ions into the logic area under the second sidewall to form a first lightly doped area between the second source and drain layer and the logic gate.

[0014] Optionally, before forming the selection gate material layer, a gate dielectric material layer is further formed on the substrate surface; the gate dielectric material layer on the storage area is etched to form a selection gate dielectric layer; and the gate dielectric material layer on the logic area is etched to form a logic gate dielectric layer.

[0015] Optionally, after forming the selection gate and before forming the selection gate dielectric layer, a third sidewall spacer is formed on the sidewall of the selection gate; and after forming the selection gate dielectric layer, the storage gate structure is formed.

[0016] Optionally, the method for forming the third spacer includes: forming a third spacer material layer on the substrate surface, the select gate sidewall and the top surface; and etching back the third spacer material layer until the substrate surface is exposed.

[0017] Optionally, after forming the selection gate and before forming the third sidewall spacer, the method further includes: using the selection gate structure as a mask, injecting fifth dopant ions into the substrate to form a threshold adjustment region on the surface of the substrate.

[0018] Optionally, after forming the two storage gate structures and before forming the first source and drain layer, the method further includes: forming a fourth spacer material layer on the substrate surface, the top and sidewall surfaces of the storage unit.

[0019] Optionally, after forming the source / drain layer, the method further includes: etching back the fourth spacer material layer until the top surface of the memory cell and the substrate surface are exposed, thereby forming a fourth spacer on the sidewall of the memory cell.

[0020] Optionally, after forming the first sidewall spacer, the method further includes: performing metal silicide treatment on the top surface of the selection gate and the top surface of the storage gate exposed by the opening, and forming a silicide layer on the top surface of the selection gate and the top surface of the storage gate.

[0021] Optionally, the storage gate structure includes a storage dielectric layer and a storage gate located on the storage dielectric layer, and the storage dielectric layer is further located between the storage gate and the select gate.

[0022] Optionally, the storage medium layer includes a first storage medium layer, a second storage medium layer located on the first storage medium layer, and a third storage medium layer located on the second storage medium layer; the material of the first storage medium layer is silicon oxide, the material of the second storage medium layer is silicon nitride, and the material of the third storage medium layer is silicon oxide.

[0023] Optionally, the method for forming the storage gate structure includes: forming a storage dielectric material layer and a storage gate material layer located on the surface of the substrate, the sidewalls and the top surface of the select gate structure; etching the storage gate material layer until the surface of the storage dielectric material layer is exposed, and forming the storage gate with the storage gate material layer; etching the storage dielectric material layer until the substrate and the top surface of the select gate structure are exposed, and forming the storage dielectric layer with the storage dielectric material layer.

[0024] Optionally, after forming the storage gate and before forming the storage dielectric layer, the method further includes: using the storage gate and the select gate structure as a mask, injecting sixth doping ions into the surface of the substrate to form a second lightly doped region in the substrate.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0026] In a method for forming a memory device provided by the technical solution of the present invention, the formed memory device occupies a small unit size, and at the same time, the top surface of the memory gate is made higher than the top surface of the selection gate. The first hard mask layer is removed, and an opening is formed between the two memory gate structures. A first sidewall can be formed in a self-aligned manner on the sidewalls of the two memory gate structures exposed by the opening. The first sidewall is beneficial to improving the isolation between the memory gate and the selection gate and reducing leakage between the memory gate and the selection gate. In addition, the first sidewall can be formed in the same process as the metal silicide barrier layer. When the top surface of the memory gate is subsequently subjected to metal silicide treatment, the first sidewall acts as a metal silicide barrier layer.

[0027] Furthermore, the storage gate is formed by a self-alignment process, which is beneficial to saving mask costs.

[0028] Furthermore, using the storage gate and the select gate structure as masks, sixth doping ions are implanted into the substrate surface to form a second lightly doped region in the substrate. The second lightly doped region is formed using a self-aligned process, which helps save mask costs.

[0029] Furthermore, the first source and drain layer is formed by a self-alignment process, which is beneficial to saving mask costs.

[0030] Furthermore, the second lightly doped region of the storage area and the first lightly doped region of the logic area are formed in self-alignment using different processes, which saves mask costs and facilitates adjusting the threshold voltages of the storage gate structure and the logic gate respectively.

[0031] Furthermore, the select gate and the logic gate are formed by etching the same select gate material layer, which is beneficial to saving production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the structure of a storage device;

[0033] Figures 2 to 14 It is a structural diagram of each step of the storage forming method in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0035] As described in the background art, the performance of SONOS devices formed using existing technologies needs to be further improved. This will now be explained and analyzed in conjunction with a memory device.

[0036] Figure 1 It is a structural diagram of a storage device.

[0037] Please refer to Figure 1 The memory device includes: a substrate 100; a selection transistor and a storage transistor adjacent to each other on the substrate 100, the selection transistor including a first gate dielectric layer 101 and a first gate electrode 102 located on the first gate dielectric layer 101; the storage transistor including a second gate dielectric layer and a second gate electrode 106 located on the second gate dielectric layer; the second gate dielectric layer including a first dielectric layer 103, a second dielectric layer 104 located on the first dielectric layer 103, and a third dielectric layer 105 located on the second dielectric layer 104; the first dielectric layer 103 is made of silicon oxide, the second dielectric layer 104 is made of silicon nitride, and the third dielectric layer 105 is made of silicon oxide; the second gate dielectric layer is further located between the first gate electrode 102 and the second gate electrode 106; and sidewall spacers 107 located on the sidewalls of the first gate electrode 102 and the second gate electrode 106.

[0038] The above-mentioned memory device is a SONOS device. The select tube and the storage tube are arranged adjacent to each other. Compared with the separate arrangement of the select tube and the storage tube, this is beneficial to reducing the size of the memory cell. However, due to the small distance between the select tube and the storage tube, when the storage device is operating, applying different voltages to the gates of the select tube and the storage tube can easily lead to top leakage or even breakdown, thereby affecting the performance of the device.

[0039] In order to solve the above problems, the present invention provides a memory device and a method for forming the same, in which the formed memory device occupies a small unit size, and at the same time, the top surface of the storage gate is made higher than the top surface of the selection gate, the first hard mask layer is removed, and an opening is formed between the two memory gate structures. A first sidewall can be self-alignedly formed on the sidewalls of the two memory gate structures exposed by the opening, and the first sidewall is beneficial to improving the isolation between the memory gate and the selection gate and reducing the leakage between the memory gate and the selection gate; in addition, the first sidewall can be formed in the same process as the metal silicide barrier layer, and when the top surface of the memory gate is subsequently subjected to metal silicide treatment, the first sidewall acts as a metal silicide barrier layer.

[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 2 to 14 It is a structural schematic diagram of each step of the method for forming a memory device in an embodiment of the present invention.

[0042] Please refer to Figure 2 , providing a substrate 200.

[0043] In this embodiment, the material of the substrate 200 includes silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0044] In this embodiment, the substrate 200 includes a storage region I and a logic region II. The storage region I is used to form a select gate structure and a storage gate structure, and the logic region II is used to form a logic gate.

[0045] In this embodiment, the storage area I includes a storage well area 201 , and the logic area II includes a logic well area 202 .

[0046] In this embodiment, the method for forming the storage well region 201 and the logic well region 202 includes: before forming the selection gate structure, forming a pad oxide layer 203 on the substrate 200; forming a third mask layer (not shown in the figure) on the pad oxide layer 203, and the third mask layer exposes the storage region I and the logic region II; using the third mask layer as a mask, injecting second doping ions into the substrate 200 to form the storage well region I and the logic well region II.

[0047] In this embodiment, the material of the third mask layer includes photoresist.

[0048] Subsequently, a select gate structure is formed on a portion of the substrate 200, wherein the select gate structure includes a select gate and a first hard mask layer located on top of the select gate. Figures 3 and 4 .

[0049] Please refer to Figure 3 , a selection gate material layer 205 and a hard mask material layer 206 located on the selection gate material layer 205 are formed on the substrate 200 .

[0050] In this embodiment, the select gate material layer 205 is used to form the select gate on the storage area I, and is also used to form the logic gate on the logic area II, which helps to save production costs.

[0051] In this embodiment, before forming the select gate material layer 205, a gate dielectric material layer 204 is formed on the surface of the substrate 200. The gate dielectric material layer 204 is used to form a select gate dielectric layer and a logic gate dielectric layer, which helps to save production costs.

[0052] Please refer to Figure 4 , patterning the hard mask material layer 206 on the storage area I to form the first hard mask layer 207; using the first hard mask layer 207 as a mask, etching the selection gate material layer 205 to form the selection gate 208.

[0053] The material of the hard mask material layer 206 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the hard mask material layer 206 is silicon nitride.

[0054] Subsequently, the gate dielectric material layer 204 on the storage region I is etched to form a select gate dielectric layer.

[0055] In this embodiment, after forming the selection gate 208 and before forming the selection gate dielectric layer, please refer to Figure 5 .

[0056] Please refer to Figure 5 A third spacer 210 is formed on the sidewall of the selection gate 208 .

[0057] The material of the third spacer 210 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the third spacer 210 is silicon oxide.

[0058] In this embodiment, the method for forming the third sidewall spacer 210 includes: forming a third sidewall spacer material layer (not shown in the figure) on the surface of the substrate 200, the sidewall and top surface of the selection gate 208; and etching back the third sidewall spacer material layer until the surface of the substrate 200 is exposed.

[0059] In this embodiment, after forming the select gate 208 and before forming the third spacer 210 , fifth dopant ions are implanted into the substrate 200 using the select gate structure as a mask to form a threshold adjustment region 209 on the surface of the substrate 200 .

[0060] In this embodiment, the gate dielectric material layer 204 on the storage region I is etched to form a select gate dielectric layer 211. Specifically, after forming the threshold adjustment region 209, the gate dielectric material layer 204 on the storage region I is etched using the third sidewall spacer 210 as a mask until the surface of the substrate 200 is exposed, thereby forming the select gate dielectric layer 211.

[0061] Subsequently, two storage gate structures are formed on the sidewalls of the select gate structure and are symmetrically distributed around the central axis of the select gate structure. Each storage gate structure includes a storage gate, and the top surface of the storage gate is higher than the top surface of the select gate.

[0062] Specifically, after forming the select gate dielectric layer 211 , the storage gate structure is formed.

[0063] In this embodiment, the method for forming the storage gate structure is described in detail. Figures 6 and 7 .

[0064] Please refer to Figure 6 A storage dielectric material layer 212 and a storage gate material layer 213 located on the surface of the storage dielectric material layer 212 are formed on the surface of the substrate 200, the sidewalls and the top surface of the select gate structure.

[0065] In this embodiment, the storage medium material layer 212 includes a first storage medium material layer (not shown in the figure), a second storage medium material layer (not shown in the figure) located on the first storage medium material layer, and a third storage medium material layer (not shown in the figure) located on the second storage medium material layer; the material of the first storage medium material layer is silicon oxide, the material of the second storage medium material layer is silicon nitride, and the material of the third storage medium material layer is silicon oxide.

[0066] Please refer to Figure 7 , etching the storage gate material layer 213 until the surface of the storage dielectric material layer 212 is exposed, and forming the storage gate 214 with the storage gate material layer 213; etching the storage dielectric material layer 212 until the substrate 200 and the top surface of the selection gate structure are exposed, and forming the storage dielectric layer 215 with the storage dielectric material layer 212.

[0067] The storage gate 214 is formed by a self-alignment process, which helps to save mask costs.

[0068] In this embodiment, after forming the storage gate 214 and before forming the storage dielectric layer 215 , sixth doping ions are implanted into the surface of the substrate 200 using the storage gate 214 and the selection gate structure as masks to form a second lightly doped region 216 in the substrate 200 .

[0069] The second lightly doped region 216 is formed by a self-aligned process, which is beneficial to saving mask costs.

[0070] In this embodiment, the storage gate structure includes a storage dielectric layer 215 and a storage gate 214 located on the storage dielectric layer 215 . The storage dielectric layer 215 is also located between the storage gate 214 and the select gate 208 .

[0071] In this embodiment, the storage medium layer 215 includes a first storage medium layer (not shown in the figure), a second storage medium layer (not shown in the figure) located on the first storage medium layer, and a third storage medium layer (not shown in the figure) located on the second storage medium layer. The first storage medium layer is made of silicon oxide, the second storage medium layer is made of silicon nitride, and the third storage medium layer is made of silicon oxide. Specifically, the first storage medium layer is formed by the first storage medium material layer, the second storage medium layer is formed by the second storage medium material layer, and the third storage medium layer is formed by the third storage medium material layer.

[0072] Subsequently, the first hard mask layer is removed to form an opening between the two storage gate structures.

[0073] In this embodiment, the select gate structure and the two storage gate structures are used as storage units; before removing the first hard mask layer and after forming the two storage gate structures, please refer to Figure 8 .

[0074] Please refer to Figure 8 , first doping ions are implanted into the substrate 200 on both sides of the memory cell to form a first source and drain layer 218 .

[0075] The first source / drain layer 218 is formed by a self-alignment process, which is beneficial to saving mask costs.

[0076] In this embodiment, after forming the two storage gate structures and before forming the first source / drain layer 218 , a fourth spacer material layer 217 is formed on the surface of the substrate 200 and on the top and sidewall surfaces of the storage unit.

[0077] In this embodiment, after forming the first source and drain layer 218, please refer to Figure 9 .

[0078] Please refer to Figure 9 , the fourth spacer material layer 217 is etched back until the top surface of the memory cell and the surface of the substrate 200 are exposed, and a fourth spacer 219 is formed on the sidewall of the memory cell.

[0079] The material of the fourth spacer 219 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the fourth spacer 219 is silicon oxide.

[0080] Subsequently, after forming the first source and drain layer 218, a logic gate is formed on the logic region I. Specifically, after forming the fourth sidewall 219, the logic gate is formed. For the method of forming the logic gate, please refer to Figure 10 .

[0081] Please refer to Figure 10 After forming the first source and drain layer 217, the hard mask material layer 206 on the logic region II is patterned to form a second hard mask layer 220; using the second hard mask layer 220 as a mask, the select gate material layer 205 is etched until the surface of the substrate 200 is exposed to form the logic gate 221.

[0082] In this embodiment, the gate dielectric material layer 204 on the logic region II is etched to form a logic gate dielectric layer 222 .

[0083] It should be noted that a dummy unit C is formed between the logic gate 221 and the memory unit. The dummy unit C is an additional device formed by the technical method of this embodiment and is in a dummy state here.

[0084] In this embodiment, after forming the logic gate 221, please refer to Figure 11 .

[0085] Please refer to Figure 11 , a second source and drain layer 223 is formed in the substrate 200 on both sides of the logic gate 221 .

[0086] The method for forming the second source and drain layer 223 includes: forming a fourth mask layer (not shown in the figure) on the substrate 200, the surface of the storage unit and the surface of the logic gate 221, the fourth mask layer exposing the surface of the logic region II on both sides of the logic gate 221; using the fourth mask layer as a mask, injecting third doping ions into the logic region II to form the second source and drain layer 223.

[0087] In this embodiment, the material of the fourth mask layer includes photoresist.

[0088] In this embodiment, before forming the second source / drain layer 223 , a second spacer 224 is formed on the sidewall of the logic gate 221 .

[0089] The material of the second sidewall spacer 224 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the second sidewall spacer 224 is silicon oxide.

[0090] In this embodiment, fourth doping ions are further implanted into the logic region II under the second sidewall spacer 224 using the fourth mask layer as a mask to form a first lightly doped region 225 between the second source / drain layer 223 and the logic gate 221 .

[0091] In this embodiment, the first lightly doped region 225 and the second source / drain layer 223 are formed using the same mask, which is beneficial to saving production costs.

[0092] At this point, the second lightly doped region of the storage area I and the first lightly doped region of the logic area II are self-aligned and formed using different processes, which saves mask costs and facilitates adjusting the threshold voltages of the storage gate structure and the logic gate 221 respectively.

[0093] Please refer to Figure 12 , removing the first hard mask layer 207 and forming an opening 226 between the two storage gate structures.

[0094] In this embodiment, the second hard mask layer 220 and the first hard mask layer 207 are removed during the same etching process.

[0095] Please refer to Figure 13 A first spacer 227 is formed on the two sidewalls of the storage gate structure exposed by the opening 226 .

[0096] The material of the first sidewall spacer 227 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the first sidewall spacer 227 is silicon oxide.

[0097] In this embodiment, the first sidewall spacer 227 is formed by a self-alignment process, which is beneficial to saving mask costs.

[0098] In this embodiment, the first sidewall spacer 227 and the metal silicide barrier layer (not shown in the figure) are formed in the same process.

[0099] In this embodiment, the method for forming the first sidewall 227 includes: forming a first sidewall material layer (not shown in the figure) on the surface of the substrate 200, the surface of the storage gate 214, the surface of the logic gate 221, the sidewall and bottom surface of the opening 226; and etching back the first sidewall material layer until the surface of the substrate 200 is exposed to form the first sidewall 227.

[0100] In this embodiment, after forming the first sidewall 227, please refer to Figure 14 .

[0101] Please refer to Figure 14 , performing metal silicide treatment on the top surface of the selection gate 208 and the top surface of the storage gate 214 exposed by the opening 226 , forming a silicide layer 228 on the top surface of the selection gate 208 and the top surface of the storage gate 214 .

[0102] At this point, the formed memory device occupies a small unit size, and the first sidewall 227 is beneficial to improving the isolation between the storage gate 214 and the selection gate 208, and reducing the leakage between the storage gate 214 and the selection gate 208; in addition, the first sidewall 227 can be formed in the same process as the metal silicide barrier layer, and when the top surface of the storage gate 214 is subsequently subjected to metal silicide treatment, the first sidewall 227 acts as a metal silicide barrier layer.

[0103] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a memory device, characterized in that: include: Providing a substrate, the substrate comprising a storage area and a logic area; forming a select gate material layer and a hard mask material layer on the select gate material layer on the substrate; patterning the hard mask material layer on the storage area to form a first hard mask layer; Using the first hard mask layer as a mask, etching the select gate material layer to form the select gate, thereby forming a select gate structure on the storage area, the select gate structure including the select gate and the first hard mask layer located on top of the select gate; Two storage gate structures are formed on the sidewalls of the select gate structure and are symmetrically distributed with the central axis of the select gate structure as an axis, each of the storage gate structures includes a storage gate, and the top surface of the storage gate is higher than the top surface of the select gate, and the select gate structure and the two storage gate structures serve as a storage unit; Implanting first dopant ions into the substrate on both sides of the memory cell to form a first source and drain layer; forming a fourth sidewall on the sidewall of the storage unit; After forming the first source and drain layer, patterning the hard mask material layer on the logic area to form a second hard mask layer; Using the second hard mask layer as a mask, etching the select gate material layer until the substrate surface is exposed to form a logic gate on the logic region; After forming the logic gate and after forming the fourth spacer, removing the first hard mask layer to form an opening between the two memory gate structures; A first spacer is formed on the two sidewalls of the storage gate structure exposed by the opening.

2. The method for forming a memory device according to claim 1, wherein: The storage area has a storage well area, and the logic area has a logic well area. The method for forming the storage well area and the logic well area includes: before forming a select gate structure, forming a pad oxide layer on the substrate; forming a third mask layer on the pad oxide layer, the third mask layer exposing the storage area and the logic area; using the third mask layer as a mask, injecting second doping ions into the substrate to form the storage well area and the logic well area.

3. The method for forming a memory device according to claim 1, wherein: After forming the logic gate, the method further includes: forming a second source and drain layer in the substrate on both sides of the logic gate.

4. The method for forming a memory device according to claim 3, wherein: The method for forming the second source and drain layer includes: forming a fourth mask layer on the substrate, the surface of the storage unit and the surface of the logic gate, the fourth mask layer exposing the surface of the logic area on both sides of the logic gate; using the fourth mask layer as a mask, injecting third doping ions into the logic area to form the second source and drain layer.

5. The method for forming a memory device according to claim 4, wherein: Before forming the second source and drain layer, a second sidewall is formed on the sidewall of the logic gate; the method also includes: using the fourth mask layer as a mask, injecting fourth doping ions into the logic area under the second sidewall to form a first lightly doped area between the second source and drain layer and the logic gate.

6. The method for forming a memory device according to claim 1, wherein: Before forming the selection gate material layer, a gate dielectric material layer is formed on the substrate surface; the gate dielectric material layer on the storage area is etched to form a selection gate dielectric layer; and the gate dielectric material layer on the logic area is etched to form a logic gate dielectric layer.

7. The method for forming a memory device according to claim 6, wherein: After forming the selection gate and before forming the selection gate dielectric layer, a third spacer is formed on the sidewall of the selection gate; after forming the selection gate dielectric layer, the storage gate structure is formed.

8. The method for forming a memory device according to claim 7, wherein: The method for forming the third spacer includes: forming a third spacer material layer on the substrate surface, the select gate sidewall and the top surface; and etching back the third spacer material layer until the substrate surface is exposed.

9. The method for forming a memory device according to claim 7, wherein: After forming the selection gate and before forming the third sidewall spacer, the method further includes: using the selection gate structure as a mask, implanting fifth doping ions into the substrate to form a threshold adjustment region on the surface of the substrate.

10. The method for forming a memory device according to claim 1, wherein: After forming the two storage gate structures and before forming the first source and drain layer, the method further includes: forming a fourth spacer material layer on the substrate surface, the top and the sidewall surface of the storage unit.

11. The method for forming a memory device according to claim 10, wherein: After forming the source and drain layers, the method further includes etching back the fourth spacer material layer until the top surface of the memory cell and the substrate surface are exposed, thereby forming a fourth spacer on the sidewall of the memory cell.

12. The method for forming a memory device according to claim 1, wherein: After forming the first sidewall spacer, the method further includes: performing metal silicide treatment on the top surface of the selection gate and the top surface of the storage gate exposed by the opening, and forming a silicide layer on the top surface of the selection gate and the top surface of the storage gate.

13. The method for forming a memory device according to claim 1, wherein: The storage gate structure includes a storage dielectric layer and a storage gate located on the storage dielectric layer. The storage dielectric layer is also located between the storage gate and the select gate.

14. The method for forming a memory device according to claim 13, wherein: The storage medium layer includes a first storage medium layer, a second storage medium layer located on the first storage medium layer, and a third storage medium layer located on the second storage medium layer; The material of the first storage medium layer is silicon oxide, the material of the second storage medium layer is silicon nitride, and the material of the third storage medium layer is silicon oxide.

15. The method for forming a memory device according to claim 13, wherein: The method for forming the storage gate structure includes: forming a storage dielectric material layer and a storage gate material layer located on the surface of the substrate, the sidewalls and the top surface of the select gate structure; etching the storage gate material layer until the surface of the storage dielectric material layer is exposed, and forming the storage gate with the storage gate material layer; etching the storage dielectric material layer until the substrate and the top surface of the select gate structure are exposed, and forming the storage dielectric layer with the storage dielectric material layer.

16. The method for forming a memory device according to claim 15, wherein: After forming the storage gate and before forming the storage dielectric layer, the method further includes: using the storage gate and the select gate structure as masks, implanting sixth doping ions into the surface of the substrate to form a second lightly doped region in the substrate.

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