Semiconductor structure

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure, comprising: bit lines extending along a first direction, word lines extending along a second direction, the first direction being one of a direction perpendicular to a substrate surface or a direction parallel to the substrate surface, and the second direction being the other one of a direction perpendicular to the substrate surface or a direction parallel to the substrate surface; a first active pillar comprising a first region and a second region arranged in sequence along a third direction, and a second active pillar comprising a third region and a fourth region arranged in sequence along the third direction, the second region and the third region being opposite to each other along a direction parallel to the substrate surface; a part of a storage structure surrounding the first region of the first active pillar, and a part of the bit lines being electrically connected to one end of the second region away from the storage structure; and a part of the storage structure surrounding the fourth region of the second active pillar, and a part of the bit lines being electrically connected to one end of the third region away from the storage structure. The semiconductor structure provided by the embodiment of the present disclosure can at least reduce parasitic capacitance and improve integration.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, in order to improve the integration density of integrated circuits while increasing the operating speed of memory and reducing its power consumption, the feature size of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices is constantly shrinking. MOSFET devices face a series of challenges. For example, to reduce the linewidth of devices, semiconductor structures have begun to evolve from buried word line structures to Gate-All-Around (GAA) transistor structures. However, the integration density of memory devices is mainly determined by the area occupied by a unit memory cell, meaning that the storage capacity is also limited by size. Furthermore, the reduction in device linewidth leads to a further reduction in the distance between adjacent word lines or bit lines, resulting in a larger parasitic capacitance between adjacent word lines or bit lines, which affects the performance of word lines or bit lines.

[0003] How to reduce device linewidth, further reduce parasitic capacitance, and improve integration density has become an important problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] This disclosure provides a semiconductor structure that at least helps to reduce parasitic capacitance and improve integration.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate, the surface of which has word lines, bit lines, active pillars, and a memory structure; the bit lines extend along a first direction, and the word lines extend along a second direction, the first direction being either a direction perpendicular to the substrate surface or a direction parallel to the substrate surface, and the second direction being either a direction perpendicular to the substrate surface or a direction parallel to the substrate surface; the active pillars include a first active pillar and a second active pillar spaced apart along a direction parallel to the substrate surface, the first active pillar including a first region and a second region arranged sequentially along a third direction, the second active pillar including a third region and a fourth region arranged sequentially along a third direction, the second region and the third region facing each other along a direction parallel to the substrate surface; a portion of the memory structure surrounds the first region of the first active pillar, and a portion of the bit lines are electrically connected to the end of the second region away from the memory structure; a portion of the memory structure surrounds the fourth region of the second active pillar, and a portion of the bit lines are electrically connected to the end of the third region away from the memory structure.

[0006] In some embodiments, the first active post of the second region includes a first source-drain region, a first channel region, and a second source-drain region arranged sequentially along a third direction, and a portion of the bit line is electrically connected to the first active post of the second source-drain region; the second active post of the third region includes a third source-drain region, a second channel region, and a fourth source-drain region extending along a third direction, and a portion of the bit line is electrically connected to the second active post of the third source-drain region.

[0007] In some embodiments, the first direction is perpendicular to the substrate surface, the second direction is parallel to the substrate surface, and the first channel region and the second channel region are directly opposite each other along the second direction.

[0008] In some embodiments, the first active post and the second active post are arranged along a second direction, and the word line is electrically connected to the first active post and the second active post arranged along the second direction; the word line surrounds the first channel region and the second channel region.

[0009] In some embodiments, along a third direction, the spacing between the bit line and the word line electrically connected to the first active post is less than or equal to the width of the end of the first active post near the bit line and the side of the word line.

[0010] In some embodiments, the first active post surrounds a portion of the bit line; or, the bit line surrounds a portion of the first active post.

[0011] In some embodiments, along a third direction, the spacing between the bit line and the word line electrically connected to the second active post is less than or equal to the width of the end of the second active post near the bit line and the side of the word line.

[0012] In some embodiments, the first direction is parallel to the substrate surface, and the second direction is perpendicular to the substrate surface; the second source / drain region and the third source / drain region are directly opposite each other along the first direction.

[0013] In some embodiments, the first active post and the second active post are arranged along a first direction, and the bit line is electrically connected to the first active post and the second active post arranged along the first direction.

[0014] In some embodiments, a first active post surrounds the word line, and a second active post surrounds the word line.

[0015] In some embodiments, along the first direction, the width of the word line is 1 / 3 to 2 / 3 times the width of the active column.

[0016] In some embodiments, the first active post and the second active post are arranged at equal intervals along a direction parallel to the substrate surface.

[0017] In some embodiments, the first active pillars are arranged in a direction perpendicular to the substrate surface, and the first spacing between adjacent first active pillars in the direction perpendicular to the substrate surface is greater than the second spacing between adjacent first active pillars and second active pillars.

[0018] In some embodiments, the first active pillars are arranged in a direction perpendicular to the substrate surface, and the first spacing between adjacent first active pillars in a direction perpendicular to the substrate surface is greater than or equal to three times the second spacing between adjacent first active pillars and second active pillars.

[0019] In some embodiments, the character lines include a first character line and a second character line; along a first direction, the first character line and the second character line are respectively located on opposite sides of a first active post; along the first direction, the first character line and the second character line are respectively located on opposite sides of a second active post.

[0020] The technical solutions provided in this disclosure have at least the following advantages:

[0021] In the technical solution provided by this disclosure, the bit line extends along a first direction, and the word line extends along a second direction. The first direction is either a direction perpendicular to the substrate surface or a direction parallel to the substrate surface, and the second direction is either a direction perpendicular to the substrate surface or a direction parallel to the substrate surface. The memory structure surrounds the first region of the first active pillar and the fourth region of the second active pillar. The integration density of the 3D memory device can be improved by stacking transistors and capacitors in a three-dimensional manner on the substrate, thereby increasing the storage density of the semiconductor structure. The support regions of the first region of the first active pillar and the fourth region of the second active pillar can serve as supports for the memory structure. The memory structure can be one transistor corresponding to one capacitor structure (1T-1C). Within a limited device unit area, the area occupied by the memory structure is maximized, which is beneficial to improving the storage density and thus improving the integration density. When the bit lines are electrically connected to the ends of the second region of the first active pillar and the ends of the second active pillar of the third region, the bit lines exhibit a staggered arrangement trend, which increases the spacing between adjacent bit lines, reduces parasitic capacitance, and thus improves the read and write speed of the semiconductor structure; or the word lines exhibit a staggered arrangement trend, which increases the spacing between adjacent word lines, thereby reducing parasitic capacitance. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0024] Figure 2 A schematic cross-sectional view of a semiconductor structure along the A-A' section, provided in an embodiment of this disclosure;

[0025] Figure 3 A schematic cross-sectional view of a semiconductor structure along the B-B' section, provided in an embodiment of this disclosure;

[0026] Figure 4 A schematic diagram of the top surface of a semiconductor structure provided in an embodiment of this disclosure;

[0027] Figure 5 A schematic diagram of a semiconductor structure provided in another embodiment of this disclosure;

[0028] Figure 6 A schematic cross-sectional view of a semiconductor structure along section A-A' provided in another embodiment of this disclosure;

[0029] Figure 7 A schematic cross-sectional view of a semiconductor structure along the B-B' section, provided in another embodiment of this disclosure;

[0030] Figure 8 A schematic diagram of the top surface of a semiconductor structure provided in another embodiment of this disclosure;

[0031] Figure 9 A schematic diagram of a semiconductor structure provided in yet another embodiment of this disclosure;

[0032] Figures 10 to 31 This is a schematic diagram of the structure corresponding to each step in the method for preparing a semiconductor structure according to an embodiment of this disclosure. Detailed Implementation

[0033] As can be seen from the background technology, the existing semiconductor structure has parasitic capacitance and poor integration.

[0034] This disclosure provides a semiconductor structure in which bit lines extend along a first direction and word lines extend along a second direction. The first direction is either perpendicular to or parallel to the substrate surface, and the second direction is either perpendicular to or parallel to the substrate surface. A memory structure surrounds a first region of a first active pillar and a fourth region of a second active pillar. By stacking transistors and capacitors in a three-dimensional manner on a substrate, the integration density of the 3D memory device can be improved, thereby increasing the storage density of the semiconductor structure. The support regions of the first region of the first active pillar and the fourth region of the second active pillar can serve as supports for the memory structure. The memory structure can be one transistor corresponding to one capacitor structure (1T-1C). Within a limited device unit area, maximizing the area occupied by the memory structure is beneficial for increasing storage density and thus improving integration. When the bit lines are electrically connected to the ends of the second region of the first active pillar and the ends of the second active pillar of the third region, the bit lines exhibit a staggered arrangement trend, which increases the spacing between adjacent bit lines, reduces parasitic capacitance, and thus improves the read and write speed of the semiconductor structure; or the word lines exhibit a staggered arrangement trend, which increases the spacing between adjacent word lines, thereby reducing parasitic capacitance.

[0035] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0036] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure; Figure 2 A schematic cross-sectional view of a semiconductor structure along the A-A' section, provided in an embodiment of this disclosure; Figure 3 A schematic cross-sectional view of a semiconductor structure along the B-B' section, provided in an embodiment of this disclosure; Figure 4 A schematic diagram of the top surface of a semiconductor structure provided in an embodiment of this disclosure; Figure 5 A schematic diagram of a semiconductor structure provided in another embodiment of this disclosure; Figure 6 A schematic cross-sectional view of a semiconductor structure along section A-A' provided in another embodiment of this disclosure; Figure 7 A schematic cross-sectional view of a semiconductor structure along the B-B' section, provided in another embodiment of this disclosure; Figure 8 A schematic diagram of the top surface of a semiconductor structure provided in another embodiment of this disclosure; Figure 9 This is a schematic diagram of a semiconductor structure provided in yet another embodiment of the present disclosure.

[0037] This disclosure provides, in one aspect, a semiconductor structure, with reference to... Figures 1 to 4 The semiconductor structure includes: a substrate 100, the surface of which has word lines 120, bit lines 130, active pillars, and a memory structure 140; the bit lines 130 extend along a first direction, and the word lines 120 extend along a second direction, the first direction being a direction Z perpendicular to the surface of the substrate 100, and the second direction being a direction Y parallel to the surface of the substrate 100; the active pillars include a first active pillar 111 and a second active pillar 112 arranged at intervals along a direction Y parallel to the surface of the substrate 100, the first active pillar 111 including a first region 121 and a second region 122 arranged sequentially along a third direction X, and the second active pillar 112 including a third region 121 and a second region 122 arranged sequentially along a third direction X. Regions 123 and 124 are connected. Regions 122 and 123 are aligned in a direction Y parallel to the surface of the substrate 100. A portion of the storage structure 140 surrounds the first region 121 of the first active post 111 and is connected to the end of the first active post 111 of the second region 122 near the first region 121. A portion of the bit line 130 is electrically connected to the end of the second region 122 away from the storage structure 140. A portion of the storage structure 140 surrounds the fourth region 124 of the second active post 112 and is connected to the end of the second active post 112 of the third region 123 near the fourth region 124. A portion of the bit line 130 is electrically connected to the end of the third region 123 away from the storage structure 140.

[0038] In some embodiments, the substrate 100 may be made of a semiconductor material. Specifically, the semiconductor material may be any one of silicon, germanium, silicon germanium, or silicon carbide.

[0039] In some embodiments, the first active post 111 extends along a third direction X, the first active post 111 of the second region 122 includes a first source / drain region 141, a first channel region 142 and a second source / drain region 143 arranged sequentially along a third direction X, and a portion of the bit line 130 is electrically connected to the first active post 111 of the second source / drain region 143; the second active post 112 of the third region 123 includes a third source / drain region 144, a second channel region 145 and a fourth source / drain region 146 extending along a third direction X, and a portion of the bit line 130 is electrically connected to the second active post 112 of the third source / drain region 144. The first active post 111 of the first channel region 142 and the second active post 112 of the second channel region 145 are directly opposite each other along a direction Y parallel to the surface of the substrate 100. The first active post 111 of the second source / drain region 143 and the second active post 112 of the fourth source / drain region 146 are directly opposite each other along a direction Y parallel to the surface of the substrate 100. The first active post 111 of the first source / drain region 141 and the second active post 112 of the third source / drain region 144 are directly opposite each other along a direction Y parallel to the surface of the substrate 100. The first active post 111 and the second active post 112 are arranged along a direction Y parallel to the surface of the substrate 100. The word line 120 is electrically connected to the first active post 111 and the second active post 112 arranged along a direction Y parallel to the surface of the substrate 100. The word line 120 surrounds the first active post 111 of the first channel region 142 and the second active post 112 of the second channel region 145. In this structure, the first source-drain region 141 and the fourth source-drain region 146 can be drains, the second source-drain region 143 and the third source-drain region 144 can be sources, the bit line 130 is electrically connected to the source of the semiconductor structure, and the memory structure 140 is electrically connected to the drain of the semiconductor structure. The memory structure 140 surrounds the first region 121 of the first active pillar 111 and the fourth region 124 of the second active pillar 112. The first region 121 and the fourth region 124 serve as the support structure of the memory structure 140, which reduces the subsequent process steps for fabricating the support layer of the memory structure 140 and the area occupied by the support layer. Conversely, it can increase the storage area of ​​the semiconductor structure and improve the storage density and integration of the semiconductor structure.

[0040] In some embodiments, the material of the second active pillar 112 can be the same as the material of the first active pillar 111, and the material of the first active pillar 111 includes an amorphous material. The amorphous material has internal gaps, resulting in higher carrier mobility, which can reduce the thickness of the first active pillar 111, thereby reducing the linewidth of the semiconductor structure within a limited cell area and further improving the storage density of the semiconductor structure. The amorphous material includes at least one of indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium gallium zinc tin oxide (IGZTO), or indium tungsten oxide (IWO). In other embodiments, the material of the first active pillar 111 can be doped polycrystalline silicon, undoped polycrystalline amorphous silicon, or single-crystal silicon. The doping element can be an N-type element or a P-type element. The N-type element can be a group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), and the P-type element can be a group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In). In some other embodiments, the material of the second active post 112 may be different from the material of the first active post 111.

[0041] In some embodiments, the doping element types of the first source / drain region 141 and the second source / drain region 143 of the first active pillar 111 are different from the doping ion types of the first channel region 142. In this case, the semiconductor structure is a junction transistor. Here, "junction" refers to the presence of a PN junction, meaning the transistor formed by the first active pillar 111 has a PN junction. This is a majority carrier-based conductive device, thus avoiding the problems of minority carrier storage and diffusion. Furthermore, the high majority carrier velocity is beneficial for improving the conductivity of the semiconductor channel. In other embodiments, the first source / drain region 141, the first channel region 142, and the second source / drain region 143 are doped with the same doping ions. In this case, the semiconductor structure is a junctionless transistor. Here, "junctionless" refers to the absence of a PN junction, meaning the transistor formed by the first active pillar 111 does not have a PN junction. On the one hand, no additional doping is required for the doped region, thus avoiding the problem of difficult-to-control doping processes in the doped region. Especially as transistor sizes shrink further, the doping concentration becomes even more difficult to control if additional doping is applied to the doped region. On the other hand, since the device is a junctionless transistor, it is beneficial to avoid the phenomenon of fabricating ultra-steep PN junctions at the nanoscale by using ultra-steep source-drain concentration gradient doping processes. Therefore, it can avoid problems such as threshold voltage drift and increased leakage current caused by abrupt doping changes, which helps to suppress short-channel effects and allows it to still operate at the nanometer scale. This contributes to further improving the integration density and electrical performance of semiconductor structures. The second active pillar 112 can be a junction-type transistor or a junctionless transistor.

[0042] In some embodiments, the first active pillar 111 and the second active pillar 112 are arranged at equal intervals along a direction Y parallel to the surface of the substrate 100. This allows the first active pillar 111 and the second active pillar 112 to be fabricated in the same process, reducing the number of process steps and the number of masks used to form the first active pillar 111 and the second active pillar 112, thereby reducing costs. The distance between the bit line 130 electrically connected to the first active pillar 111 and the bit line 130 electrically connected to the second active pillar 112 can be maximized within a limited area, reducing parasitic capacitance between adjacent bit lines 130 and improving the read / write speed of the semiconductor structure.

[0043] In some embodiments, the first active pillars 111 are arranged along a direction Z perpendicular to the surface of the substrate 100, and the first spacing d1 between adjacent first active pillars 111 along the direction Z perpendicular to the surface of the substrate 100 is greater than the second spacing d2 between adjacent first active pillars 111 and second active pillars 112. When forming word lines 120 surrounding the first channel region 142 and the second channel region 145, word lines 120 extending along a direction Y parallel to the surface of the substrate 100 can be formed quickly. The word lines 120 surrounding the first channel region 142 and the word lines 120 surrounding the second channel region 145 can be tightly connected or have small gaps, so that the word lines 120 between adjacent transistors are well connected, reducing the process complexity of the word lines 120 and avoiding excessively large defects in the word lines 120 due to excessively fast deposition growth rate, thereby affecting the electrical performance of the word lines 120. The larger spacing area is used to form air gaps or to form isolation layers between adjacent word lines 120, reducing the influence of parasitic capacitance between adjacent word lines 120. Furthermore, the first active pillars 111 are arranged in a direction perpendicular to the surface of the substrate 100, and the first spacing d1 between adjacent first active pillars 111 in the direction perpendicular to the surface of the substrate 100 is greater than or equal to three times the second spacing d2 between adjacent first active pillars 111 and second active pillars 112. Similarly, the second active pillars 112 are arranged in a direction perpendicular to the surface of the substrate 100, and the third spacing between adjacent second active pillars 112 in the direction perpendicular to the surface of the substrate 100 is greater than the second spacing d2 between adjacent first active pillars 111 and second active pillars 112.

[0044] In some embodiments, along a third direction X, the spacing between the bit line 130 and the word line 120, which are electrically connected to the first active pillar 111, is less than or equal to the width of the end of the first active pillar 111 near the bit line 130 and the side of the word line 120, to ensure a good electrical connection between the bit line 130 and the active pillar. In a specific example, the side of the bit line 130 abuts against the side of the first active pillar 111, and the area of ​​the contact surface between the bit line 130 and the first active pillar 111 is 1 / 3 to 3 of the area of ​​the side of the first active pillar 111. A larger contact area between the bit line 130 and the first active pillar 111 results in better electrical connection performance between the bit line 130 and the first active pillar 111, thereby improving the read / write speed of the semiconductor structure. In another specific example, the width of bit line 130 in the direction Y parallel to the surface of substrate 100 is less than the width of the first active post 111, and the first active post 111 surrounds a portion of bit line 130; or, the width of bit line 130 in the direction Y parallel to the surface of substrate 100 is greater than the width of the first active post 111, and it surrounds a portion of the first active post 111. Similarly, in the third direction X, the distance between bit line 130, which is electrically connected to second active post 112, and word line 120 is less than or equal to the width of the end of second active post 112 near bit line 130 and the side of word line 120.

[0045] In some embodiments, the bit line 130 extends along the direction Z perpendicular to the surface of the substrate 100. The bit line 130 is a metallic bit line, and the material of the bit line 130 can be metals such as tungsten, copper, molybdenum, and silver. Metals have low resistance, which is beneficial to improving the conductivity between the bit line 130 and the first active pillar 111. In other embodiments, the bit line 130 can be a semiconductor bit line, and the material of the semiconductor bit line can be silicon, germanium, germanium silicon, silicon carbide, or polycrystalline silicon. Furthermore, the semiconductor bit line is doped with the same type of dopant element as the first active pillar 111 or the second active pillar 112 electrically connected to the bit line 130. The dopant element can act as a charge carrier, which can improve the migration and diffusion of charge carriers within the bit line 130 and between the first active pillar 111 or the second active pillar 112, thereby improving the conductivity between the bit line 130 and the first active pillar 111 or the second active pillar 112.

[0046] In some embodiments, word line 120 serves as the gate of a semiconductor structure. Word line 120 surrounds the first active pillar 111 of the first channel region 142 and the second active pillar 112 of the second channel region 145. That is, the semiconductor structure is a GAA structure. The GAA structure can realize that the gate surrounds the channel region of the semiconductor on all four sides. It can largely solve the problems of leakage current, capacitance effect and short channel effect caused by the reduction of gate pitch size. It reduces the area occupied by word line 120 in the vertical direction, which is beneficial to enhance gate control performance and improve the integration of semiconductor structure.

[0047] In some embodiments, the word line 120 is made of any one of tungsten, tantalum, molybdenum, titanium nitride, or tantalum nitride, forming a metal gate line. In other embodiments, the word line 120 is made of doped polysilicon. Since the band gap of polysilicon is similar to that of the active pillar material serving as the channel, and the work function of polysilicon can be changed by controlling the doping concentration, it is beneficial to reduce the threshold voltage between the gate and the active pillar in the channel region. The doping element type of the doped polysilicon may be the same as or different from the doping element type of the active pillar in the channel region.

[0048] In some embodiments, the memory structure 140 can be a capacitor structure, which can be a columnar capacitor structure or a barrel capacitor structure. The semiconductor structure can form one transistor corresponding to one capacitor structure (1T-1C). A first dielectric layer 113 is provided between adjacent capacitor structures. The material of the first dielectric layer 113 can include carbon oxide, silicon oxide, silicon nitride, silicon nitride, or other materials with a low dielectric constant K. This reduces parasitic capacitance between adjacent memory structures 140, lowers leakage current in the integrated circuit, and reduces signal crosstalk between adjacent memory structures 140, thereby allowing for higher integration density in the semiconductor structure. For example, carbon oxide can specifically be silicon carbide, silicon oxide can specifically be silicon oxide, silicon nitride can specifically be silicon nitride, silicon nitride can specifically be silicon carbide, and the material with a low dielectric constant K can specifically be silicon oxide or polyimide nanomaterials.

[0049] In some embodiments, the storage structure 140 includes a stacked first electrode, a second dielectric layer, and a second electrode. The first electrode may be made of titanium, titanium nitride, ruthenium, cobalt, nickel, or tungsten. The second dielectric layer may be made of silicon oxide, silicon nitride, or any one or more high dielectric constant materials, including hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate. The second electrode may be made of titanium, titanium nitride, ruthenium, cobalt, nickel, or tungsten. In other embodiments, the second electrode includes a stacked first sub-electrode and a second sub-electrode. The first sub-electrode may be made of titanium, titanium nitride, ruthenium, cobalt, nickel, or tungsten, and the second sub-electrode may be made of doped polycrystalline silicon.

[0050] In some embodiments, the semiconductor structure further includes an insulating layer 106, which is located between the word line 120 and the bit line 130, and also between the word line 120 and the memory structure 140, serving as an insulating layer. The insulating layer 106 may be made of silicon nitride, silicon oxide, or other materials with a high dielectric constant K.

[0051] In some embodiments, the semiconductor structure further includes a gate dielectric layer 107 and an isolation layer 108. The gate dielectric layer 107 is located between the word line 120 and the first active pillar 111 of the first channel region 142, and between the word line 120 and the second active pillar 112 of the second channel region 145. The gate dielectric layer 107 may be made of silicon oxide, silicon carbide, silicon nitride, or other materials with high dielectric constant, to suppress short-channel effects, thereby suppressing tunneling leakage current and other conditions. The isolation layer 108 is located between adjacent active pillars. Specifically, the isolation layer 108 is located between adjacent word lines 120 along a direction Z perpendicular to the surface of the substrate 100. The isolation layer 108 is used to isolate adjacent word lines 120, preventing electrical connection between adjacent word lines 120 and short circuits. The isolation layer 108 may be made of silicon oxide or other insulating materials with low dielectric constant.

[0052] In some implementations, the word lines 120 gradually decrease in length along the direction Y parallel to the surface of the substrate 100, forming a stepped structure, so as to facilitate the subsequent formation of a wire structure connecting the individual word lines 120.

[0053] The above embodiments are described with the first direction being Z, which is perpendicular to the substrate surface, and the second direction being Y, which is parallel to the substrate surface. Another embodiment of this disclosure also provides a semiconductor structure. The semiconductor structure provided in this other embodiment is largely the same as the semiconductor structure provided in the foregoing embodiments, with the main difference being that the first direction is Y, which is parallel to the substrate surface, and the second direction is Z, which is perpendicular to the substrate surface. That is, the bit line extends along the direction Y, which is parallel to the substrate surface, and the word line extends along the direction Z, which is perpendicular to the substrate surface. The same technical features as in the above embodiments will not be elaborated further here.

[0054] refer to Figures 5-8The semiconductor structure includes: a substrate 200, the surface of which has word lines 220, bit lines 230, active pillars, and a memory structure 240; the bit lines 230 extend along a first direction, and the word lines 220 extend along a second direction, the first direction being a direction Y parallel to the surface of the substrate 200, and the second direction being a direction Z perpendicular to the surface of the substrate 200; active pillars, including a first active pillar 211 and a second active pillar 212 spaced apart along a direction Y parallel to the surface of the substrate 200, the first active pillar 211 including a first region 221 and a second region 222 sequentially arranged along a third direction X, and the second active pillar 212 including a third region sequentially arranged along a third direction X. Regions 223 and 224, 222 and 223 are aligned in a direction Y parallel to the surface of substrate 200; a portion of memory structure 240 surrounds the first region 221 of the first active post 211 and is connected to the end of the first active post 211 of the second region 222 near the first region 221, and a portion of bit line 230 is electrically connected to the end of the second region 222 away from memory structure 240; a portion of memory structure 240 surrounds the fourth region 224 of the second active post 212 and is connected to the end of the second active post 212 of the third region 223 near the fourth region 224, and a portion of bit line 230 is electrically connected to the end of the third region 223 away from memory structure 240.

[0055] In some embodiments, the second source / drain region 243 and the third source / drain region 244 are directly opposite each other along a direction Y parallel to the surface of the substrate 200. The first active pillar 211 and the second active pillar 212 are arranged along a first direction, and any bit line 230 is electrically connected to the first active pillar 211 and the second active pillar 212 arranged along a direction Y parallel to the surface of the substrate 200. By having multiple transistors sharing the bit line 230 along a direction Y parallel to the surface of the substrate 200, the number of bit lines 230 is reduced, thereby improving the integration density of the semiconductor structure.

[0056] In some embodiments, a first active pillar 211 surrounds a word line 220, and a second active pillar 212 surrounds a word line 220. This increases the length of the first channel region 242 and the second channel region 245, thereby largely solving problems such as leakage current, capacitance effect, and short-channel effect caused by the reduction of the gate pitch size.

[0057] In some embodiments, along a direction Y parallel to the surface of the substrate 200, the width of the word line 220 is 1 / 3 to 2 / 3 times the width of the active pillar. Optionally, the width of the word line 220 is 1 / 3 to 1 / 2 times the width of the active pillar. The width of the word line 220 is 0.36, 0.41, 0.43, or 0.49 times the width of the active pillar. This ensures that the lengths of the first channel region 242 and the second channel region 245, as well as the width of the word line 220, are appropriate. On the one hand, the lengths of the first channel region 242 and the second channel region 245 indicate that the first active pillar 211 and the second active pillar 212 have sufficient area to provide charge carriers. The area of ​​the word line 220 allows the word line to have sufficient control capability, thereby improving the stability of the semiconductor structure. Along the direction Y parallel to the surface of the substrate 200, the width of the word line 220 is 1 / 3 to 2 / 3 times the width of the first active pillar 211, and the width of the word line 220 is 1 / 3 to 2 / 3 times the width of the second active pillar 212. The width of the first active pillar 211 and the width of the second active pillar 212 can be the same, and the width of the word line 220 surrounded by the first active pillar 211 and the width of the word line 220 surrounded by the second active pillar 212 can be the same or different.

[0058] In the technical solutions provided in the embodiments of this disclosure, such as Figures 1 to 4 As shown, the semiconductor structure includes: a substrate 100, and bit lines 130, word lines 120, active pillars, and a memory structure 140 located on the substrate 100; the bit lines 130 extend along a direction Z perpendicular to the surface of the substrate 100, and the word lines 120 extend along a direction Y parallel to the surface of the substrate 100 (or as shown in the diagram). Figures 5 to 8 As shown, bit lines 230 extend along a direction Y parallel to the surface of substrate 200, and word lines 220 extend along a direction Z perpendicular to the surface of substrate 200. The memory structure 140 surrounds the first region 121 of the first active pillar 111 and the fourth region 124 of the second active pillar. This means that the integration density of 3D memory devices can be improved by stacking transistors and capacitors in a three-dimensional manner on substrate 100, thereby increasing the storage density of the semiconductor structure. The first region 121 of the first active pillar 111 and the fourth region 124 of the second active pillar can serve as supports for the memory structure 140. Within a limited device cell area, the area occupied by the memory structure 140 is maximized, which is beneficial for increasing storage density. When bit lines 130 are electrically connected to the ends of the second region 122 of the first active pillar 111 and the second active pillar 112 of the third region 123, respectively, the bit lines 130 exhibit a staggered arrangement trend, increasing the spacing between adjacent bit lines 130, reducing parasitic capacitance, and thus improving the read / write speed of the semiconductor structure (or as...). Figures 5 to 8 As shown, the word lines 220 exhibit a staggered arrangement trend, increasing the spacing between adjacent word lines 220, thereby reducing parasitic capacitance.

[0059] refer to Figure 9 Another embodiment of this disclosure provides a semiconductor structure, including: a substrate 300, the surface of which has word lines 320, bit lines 330, active pillars, and a memory structure 340; the bit lines 330 extend along a first direction, and the word lines 320 extend along a second direction, the first direction being a direction Y parallel to the surface of the substrate 300, and the second direction being a direction Z perpendicular to the surface of the substrate 300; active pillars, the active pillars including a first active pillar 311 and a second active pillar 312 spaced apart along a direction Y parallel to the surface of the substrate 300, the first active pillar 311 including a first region 321 and a second region 322 sequentially arranged along a third direction X, the second active pillar 312 including a first region 321 and a second region 322 sequentially arranged along a third direction X. The third region 323 and the fourth region 324 are arranged in a second arrangement. The second region 322 and the third region 323 are directly opposite each other in a direction Y parallel to the surface of the substrate 300. Part of the storage structure 340 surrounds the first region 321 of the first active post 311 and is connected to the end of the first active post 311 of the second region 322 that is close to the first region 321. Part of the bit line 330 is electrically connected to the end of the second region 322 that is away from the storage structure 340. Part of the storage structure 340 surrounds the fourth region 324 of the second active post 312 and is connected to the end of the second active post 312 of the third region 323 that is close to the fourth region 324. Part of the bit line 330 is electrically connected to the end of the third region 323 that is away from the storage structure 340.

[0060] In some embodiments, word lines 320 include a first word line 325 and a second word line 326; along a direction Y parallel to the surface of the substrate 300, the first word line 325 and the second word line 326 are respectively located on opposite sides of the first active pillar 311; along a direction Y parallel to the surface of the substrate 300, the first word line 325 and the second word line 326 are respectively located on opposite sides of the second active pillar 312. Thus, etching of the first active pillar 311 and the second active pillar 312 is unnecessary, thereby ensuring the integrity of the first active pillar 311 and the second active pillar 312. The first active pillar 311 and the second active pillar 312 have sufficient stress and area to serve as a support layer for the memory structure 340, improving the stability of the semiconductor structure. The first word line 325 and the second word line 326 can improve the gate's control over the channel region, thereby making the turn-off / turn-on of the channel region more sensitive.

[0061] Accordingly, one embodiment of this disclosure provides a method for fabricating a semiconductor structure, which can be used to form the above-mentioned... Figures 1 to 4 The semiconductor structure shown is identical or corresponding to those in the above embodiments and will not be described in detail below.

[0062] Figures 10-31 This is a schematic diagram of the structure corresponding to each step in the fabrication method of a semiconductor structure provided in an embodiment of this disclosure. Wherein, Figures 10 to 20This is a schematic cross-sectional view of each step in the fabrication method of the semiconductor structure provided in an embodiment of the present disclosure, corresponding to the cross-section along A-A'. Figures 21 to 31 This is a schematic diagram of the top surface of each step in the fabrication method of the semiconductor structure provided in an embodiment of this disclosure. The fabrication method of the semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings. It can be understood that... Figures 5-9 The method for fabricating the semiconductor structure shown is similar to Figures 1-4 The method for fabricating the semiconductor structure shown ( Figures 10-31 Similarly, the embodiments disclosed herein use... Figures 1-4 The method for fabricating the semiconductor structure shown is illustrated as an example.

[0063] refer to Figure 10 A substrate 100 is provided; a semiconductor layer 102 and a first oxide layer 101 are sequentially formed on the surface of the substrate 100 by alternating intervals. The semiconductor layer 102 is used for the subsequent formation of active pillars.

[0064] In some embodiments, a semiconductor layer 102 and a first oxide layer 101 are formed using a chemical deposition process or a physical deposition process. The materials of the semiconductor layer 102 and the first oxide layer 101 have different etching rates in the same etching process. The material of the semiconductor layer 102 includes a semiconductor material or an amorphous material, and the material of the first oxide layer 101 is silicon oxide or silicon nitride.

[0065] refer to Figure 21 A patterned semiconductor layer 102 and a first oxide layer 101 are formed to create a first groove 103, the bottom of which exposes the substrate. The first groove 103 can be used as an isolation region for transistors adjacent along a direction Y parallel to the substrate surface. Specifically, along B-B' (refer to...) Figure 1 The semiconductor layer 102, the first oxide layer 101, and a portion of the substrate are etched in cross-section to form the first groove 103. The first groove 103 is formed using a dry etching process.

[0066] In some embodiments, the width of the first groove 103 is smaller than the thickness of the first oxide layer 101, thereby ensuring the formation of the subsequent first active pillar.

[0067] refer to Figure 11 as well as Figure 22 A first mask layer and a second mask layer are formed on the top surface of the first oxide layer 101. The extension direction of the first mask layer is opposite to that of the second mask layer, and the first mask layer and the second mask layer have an overlapping region along a direction parallel to the substrate surface. The overlapping region is used to form a transistor structure. Using the first mask layer and the second mask layer as masks, the semiconductor layer 102 and the first oxide layer 101 are patterned, and then the first mask layer and the second mask layer are removed.

[0068] refer to Figure 12 as well as Figure 23 A sacrificial layer 104 is formed, which fills the first groove 103 (reference). Figure 21 The sacrificial layer 104 material includes oxides or polycrystalline silicon, and the oxides may include silicon oxide, aluminum oxide, or titanium oxide.

[0069] refer to Figure 13 as well as Figure 24 The first oxide layer 101 and the sacrificial layer 104 are etched to form a second groove 105 that exposes the substrate 100 and the semiconductor layer 102. The extension direction of the second groove 105 intersects the extension direction of the first groove 103, and both the extension direction of the second groove 105 and the extension direction of the first groove 103 are parallel to the surface of the substrate 100.

[0070] Specifically, the second groove 105 extends parallel to the substrate surface Y, while the first groove 103 extends in the third direction X. The extension direction of the second groove 105 is perpendicular to the extension direction of the first groove 103. The second groove 105 may expose the end of the semiconductor layer 102 or not. The sacrificial layer 104 and the first oxide layer 101 are removed using either a dry etching process or a wet etching process.

[0071] refer to Figure 14 as well as Figure 25 An insulating layer 106 is formed, which fills the second groove 105 (reference). Figure 11 The insulating layer 106 is located between adjacent semiconductor layers 102.

[0072] refer to Figure 15 as well as Figure 26 Remove the sacrificial layer 104 and the first oxide layer 101 located between the insulating layers 106 to expose the sides of the semiconductor layer 102.

[0073] refer to Figure 16 as well as Figure 27 For the exposed semiconductor layer 102 (reference) Figure 15 The semiconductor layer 102 is smoothed to make its cross-sectional shape, along the direction Y parallel to the surface of the substrate 100, elliptical or near-elliptical. This reduces surface damage to the first active pillar 111 and the second active pillar 112, lowers surface defects in the first active pillar 111 and the second active pillar 112, and helps reduce the impedance between the first active pillar 111 and the second active pillar 112 and the subsequently formed word lines. In other embodiments, the semiconductor layer 102 (see reference) may not be used. Figure 15 Smooth the surface.

[0074] In some embodiments, the first active post 111 includes a first region 121 and a second region 122 arranged sequentially along a third direction X, and the second active post 112 includes a third region 123 and a fourth region 124 arranged sequentially along a third direction X. The second region 122 and the third region 123 face each other in a direction Y parallel to the surface of the substrate 100. The first active post 111 in the second region 122 includes a first source / drain region 141, a first channel region 142, and a second source / drain region 143 arranged sequentially along a third direction X. The bit line formed subsequently is electrically connected to the first active post 111 in the second source / drain region 143. The second active post 112 in the third region 123 includes a third source / drain region 144, a second channel region 145, and a fourth source / drain region 146 extending along a third direction X. The bit line formed subsequently is electrically connected to the second active post 112 in the third source / drain region 144.

[0075] refer to Figure 2 , Figure 17 as well as Figure 28 A gate dielectric layer 107 is formed, which surrounds the first active pillar 111 and the second active pillar 112; a conductive layer is formed, which surrounds the gate dielectric layer 107 and serves as a word line 120.

[0076] refer to Figure 18 as well as Figure 29 An isolation layer 108 is formed between word lines 120 in the direction Z perpendicular to the surface of the substrate 100.

[0077] refer to Figure 19 as well as Figure 30 A through hole 109 is formed, which exposes the sides of the first active post 111 and the second active post 112.

[0078] In some embodiments, during the formation of the via 109, a portion of the first active post 111 and the second active post 112 may be etched, thereby increasing the contact area between the subsequently formed bit line and the first active post 111 and the second active post 112.

[0079] refer to Figure 20 as well as Figure 31 Bit line 130 is formed, and bit line 130 fills the via 109 (reference). Figure 19 Bit line 130 is electrically connected to the first active post 111 of the second source / drain region 143; part of bit line 130 is electrically connected to the second active post 112 of the third source / drain region 144.

[0080] refer to Figures 1 to 4A storage structure 140 is formed, wherein a portion of the storage structure 140 surrounds the first region 121 of the first active pillar 111 and is connected to the end of the first active pillar 111 of the second region 122 near the first region 121; a portion of the storage structure 140 surrounds the fourth region 124 of the second active pillar 112 and is connected to the end of the second active pillar 112 of the third region 123 near the fourth region 124.

[0081] In some embodiments, the memory structure 140 is a capacitor structure. The memory structure 140 may include multiple capacitor structures, each corresponding to an active pillar. That is, the memory cell may include a memory cell of a three-dimensional (3D) DRAM with a 1T-1C (1 transistor-1 capacitor) structure, and a first dielectric layer is provided between adjacent capacitor structures.

[0082] Specifically, the formation steps of the storage structure 140 include etching away the remaining first oxide layer 101 (see reference). Figure 10 A capacitor region is formed, exposing the surface of the first active pillar 111 of the first source / drain region 141, the surface of the first active pillar 111 of the first region 121, the surface of the second active pillar 112 of the fourth source / drain region 146, and the second active pillar 112 of the fourth region 124; a storage structure 140 and a first dielectric layer 113 are formed within the capacitor region.

[0083] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the surface of which has word lines, bit lines, active pillars, and memory structures; The bit line extends along a first direction, and the word line extends along a second direction. The first direction is either a direction perpendicular to the substrate surface or a direction parallel to the substrate surface, and the second direction is either a direction perpendicular to the substrate surface or a direction parallel to the substrate surface. An active column, comprising a first active column and a second active column arranged at intervals along a direction parallel to the surface of the substrate, the first active column comprising a first region and a second region arranged sequentially along a third direction, the second active column comprising a third region and a fourth region arranged sequentially along the third direction, the second region and the third region facing each other along a direction parallel to the surface of the substrate, the third direction having an angle with the plane formed by the first direction and the second direction; Part of the memory structure surrounds a first region of the first active pillar, and part of the bit line is electrically connected to the end of the second region away from the memory structure; part of the memory structure surrounds a fourth region of the second active pillar, and part of the bit line is electrically connected to the end of the third region away from the memory structure.

2. The semiconductor structure according to claim 1, characterized in that, The first active post of the second region includes a first source-drain region, a first channel region, and a second source-drain region arranged sequentially along the third direction, and a portion of the bit line is electrically connected to the first active post of the second source-drain region; the second active post of the third region includes a third source-drain region, a second channel region, and a fourth source-drain region extending along the third direction, and a portion of the bit line is electrically connected to the second active post of the third source-drain region.

3. The semiconductor structure according to claim 2, characterized in that, The first direction is perpendicular to the surface of the substrate, the second direction is parallel to the surface of the substrate, and the first channel region and the second channel region are directly opposite each other along the second direction.

4. The semiconductor structure according to claim 3, characterized in that, The first active post and the second active post are arranged along the second direction, and the word line is electrically connected to the first active post and the second active post arranged along the second direction; the word line surrounds the first channel area and the second channel area.

5. The semiconductor structure according to claim 3, characterized in that, Along the third direction, the distance between the bit line and the word line electrically connected to the first active post is less than or equal to the width of the end of the first active post near the bit line and the side of the word line.

6. The semiconductor structure according to claim 5, characterized in that, The first active post surrounds a portion of the bit line; or, the bit line surrounds a portion of the first active post.

7. The semiconductor structure according to claim 5, characterized in that, Along the third direction, the distance between the bit line and the word line electrically connected to the second active post is less than or equal to the width of the end of the second active post near the bit line and the side of the word line.

8. The semiconductor structure according to claim 2, characterized in that, The first direction is parallel to the substrate surface, and the second direction is perpendicular to the substrate surface; the second source / drain region and the third source / drain region are directly opposite each other along the first direction.

9. The semiconductor structure according to claim 8, characterized in that, The first active post and the second active post are arranged along the first direction, and the bit line is electrically connected to the first active post and the second active post arranged along the first direction.

10. The semiconductor structure according to claim 8, characterized in that, The first active post surrounds the word line, and the second active post surrounds the word line.

11. The semiconductor structure according to claim 10, characterized in that, Along the first direction, the width of the word line is 1 / 3 to 2 / 3 times the width of the active column.

12. The semiconductor structure according to claim 1, characterized in that, Along a direction parallel to the surface of the substrate, the first active post and the second active post are arranged at equal intervals.

13. The semiconductor structure according to claim 1 or 12, characterized in that, The first active pillars are arranged in a direction perpendicular to the surface of the substrate, and the first spacing between adjacent first active pillars in the direction perpendicular to the surface of the substrate is greater than the second spacing between adjacent first active pillars and second active pillars.

14. The semiconductor structure according to claim 13, characterized in that, The first active pillars are arranged in a direction perpendicular to the surface of the substrate, and the first spacing between adjacent first active pillars in the direction perpendicular to the surface of the substrate is greater than or equal to three times the second spacing between adjacent first active pillars and second active pillars.

15. The semiconductor structure according to claim 1, characterized in that, The character lines include a first character line and a second character line; Along the first direction, the first character line and the second character line are respectively located on opposite sides of the first active column; along the first direction, the first character line and the second character line are respectively located on opposite sides of the second active column.

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