Normally-off power switch with integrated fail-safe pull-down circuit and controllable turn-off time

Abstract

A normally-off power switch with integrated fail-safe pull-down circuit and controllable turn-off time is disclosed. A semiconductor device includes a normally-off power transistor and a first fail-safe pull-down circuit integrated in a semiconductor die. A gate of the normally-off power transistor is electrically connected to a control terminal of the semiconductor die. The first fail-safe pull-down circuit includes a first always-on pull-down transistor and a turn-off time control circuit integrated in the semiconductor die. A gate of the first always-on pull-down transistor is electrically connected to a first reference terminal of the semiconductor die. The first always-on pull-down transistor is configured to pull down the gate of the normally-off power transistor to a voltage lower than a threshold voltage of the normally-off power transistor when no voltage is applied across the control terminal and the first reference terminal. The turn-off time control circuit is configured to control a turn-off time of the normally-off power transistor.

Description

Background Technology

[0001] Gallium nitride (GaN)-based switches and other similar high electron mobility transistors (HEMTs) based on heterojunctions offer high voltage support, low drain-to-source on-resistance, low gate drive charge requirements, and fast switching. As a result of these characteristics, GaN-based switches are increasingly used in applications requiring high efficiency and high frequency support, particularly switching power converters. However, compared to conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) and bipolar junction transistors (BJTs), some GaN-based switches have unique gate drive requirements and typically require complex gate drive circuitry.

[0002] In its natural state, a GaN-based switch is a normally-on (depletion-type) device. When no voltage is applied to its gate relative to its source, such a device conducts current from its drain to its source and requires a negative voltage to be applied to its gate to force the device into a non-conducting (blocking) state. This normally-on behavior is unsuitable for most applications. Therefore, modifications to GaN-based switches have been developed to transform them into normally-off (enhancement-type) devices. For example, a p-doped GaN layer introduced between the gate metal and the heterostructure of the GaN-based switch has the effect of raising the switch's on / off or voltage threshold to a positive value, thereby providing a normally-off device. Enhancement-type switches based on such gate structures are known as gate-injected transistors (GITs).

[0003] GaN-based gate-to-interface (GITs) have relatively low threshold voltages for switching between their conduction (on) and blocking (off) states. This threshold voltage is typically in the range of 1.2 to 3.5 V, significantly lower than the corresponding threshold of 5 V for other power MOSFETs. Additionally, HEMTs incorporating GaN-based GITs have low gate-to-source and gate-to-drain capacitances, significantly smaller than their counterparts in other power MOSFETs. While the low threshold voltage and low gate capacitance of GaN-based GITs advantageously provide fast switching speeds and low gate charge requirements, these characteristics also make GaN-based GITs susceptible to undesirable turn-on due to voltage disturbances at the gate during intervals intended to keep the GIT in its non-conducting (blocking) state. For example, noise at the gate can cause its voltage to rise above the GIT's threshold voltage, despite the intention to keep the gate at a low voltage. Such noise can occur during operating intervals intended to keep the GIT in its non-conducting state, and during startup intervals where the gate may not yet have been provided with a drive control signal. Additionally, after the control voltage transitions from a high (on) voltage level to a low (off) voltage level, the gate voltage may be prone to ringing. The ringing voltage level may exceed the threshold voltage of the GIT, thereby unintentionally turning on the GIT.

[0004] The above problem is typically solved using complex circuitry custom-designed to drive GaN-based gate sensors (GITs) or similar enhanced HEMTs. Such circuitry typically drives a negative voltage onto the gate to turn off the GIT, thereby providing a sufficient margin between the gate drive voltage and the turn-on threshold voltage. This margin allows the GaN-based GIT to be reliably held in its non-conducting (blocking) state. A resistor-resistor-capacitor (RRC) circuit is often included in the drive circuit to provide a high current when the GaN-based GIT initially transitions to a conducting state. A lower current is then provided to maintain the conducting state of the GIT. When the GaN-based GIT transitions to an off state, the RRC circuit additionally has the effect of applying a relatively high amplitude negative voltage, which dissipates to zero over the off interval. As described above, a typical drive circuit includes at least two, and often as many as four, driver switches, each of which must be controlled and provides three or four voltage levels to the gate.

[0005] The typical GIT driver circuit described above has several problems. First, the negative voltage supplied at the gate during the turn-off interval causes a large, required voltage swing when the GIT transitions to its conduction state, thus slowing down the GIT transition and the possible switching speed. Second, RRC-based dissipation means that the level of the negative voltage will vary depending on the switching duty cycle, resulting in inconsistent transition times, which complicates the use and control of the GIT. Third, while the negative voltage described above reliably keeps the GIT off during steady-state operation, a pseudo-non-zero voltage during the initial startup interval may undesirably turn the GIT on before the negative voltage is driven to the gate. Fourth, the negative voltage adds bias to the effective reverse body diode voltage, thereby increasing the threshold voltage of the effective reverse body diode and increasing associated losses. Finally, the driver circuit is quite complex and requires fairly complex control of the switches within the driver circuit itself. Summary of the Invention

[0006] According to an embodiment of a semiconductor device, the semiconductor device includes: a normally off power transistor integrated in a semiconductor die, wherein the gate of the normally off power transistor is electrically connected to a control terminal of the semiconductor die; and a first fail-safe pull-down circuit, comprising: a first normally on pull-down transistor integrated in the semiconductor die, wherein the gate of the first normally on pull-down transistor is electrically connected to a first reference terminal of the semiconductor die, wherein the first normally on pull-down transistor is configured to pull down the gate of the normally off power transistor to a voltage below a threshold voltage of the normally off power transistor when no voltage is applied across the control terminal and the first reference terminal; and a turn-off time control circuit configured to control the turn-off time of the normally off power transistor.

[0007] According to an embodiment of a semiconductor die, the semiconductor die includes: a control terminal; a first reference terminal; a normally off power transistor having a gate electrically connected to the control terminal; and a first fail-safe pull-down circuit, including: a first normally on pull-down transistor having a gate electrically connected to the first reference terminal, wherein the first normally on pull-down transistor is configured to pull down the gate of the normally off power transistor to a voltage below a threshold voltage of the normally off power transistor when no voltage is applied across the control terminal and the first reference terminal; and a first resistor connected in series between the gate of the first normally on pull-down transistor and the gate of the normally off power transistor.

[0008] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and reviewing the accompanying drawings. Attached Figure Description

[0009] The elements in the accompanying drawings are not necessarily to scale. The same reference numerals indicate corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Embodiments are depicted in the accompanying drawings and described in detail below.

[0010] Figure 1 The illustration shows an embodiment of a semiconductor device, which includes a normally off power transistor integrated in a semiconductor die, the semiconductor die having a first fail-safe pull-down circuit for controlling the turn-off time.

[0011] Figure 2 The illustration shows an embodiment of a semiconductor device, which includes a normally-on power transistor integrated in a semiconductor die, the semiconductor die having a fail-protected pull-down circuit and a second fail-protected pull-down circuit for enhanced turn-off time control.

[0012] Figure 3 The diagram corresponds to Figure 2 Examples of waveforms for semiconductor devices.

[0013] Figure 4 The diagram is for use Figure 2 Simulation results of turn-off dv / dt conversion rate for semiconductor devices with different programmable gate path resistors.

[0014] Figure 5 The illustration shows an example of two fail-safe pull-down circuits implemented in a transformer-based switching device.

[0015] Figure 6 The illustration shows an embodiment of a transformer-based switching device that includes a first fail-protection pull-down circuit but does not include a second fail-protection pull-down circuit.

[0016] Figure 7 The illustration shows an embodiment of a semiconductor device including two fail-safe pull-down circuits and a resistor modulation circuit for controlling the on-time.

[0017] Figure 8 The illustration shows an embodiment of a semiconductor device that includes a resistor modulation circuit and a first fail-protection pull-down circuit, but does not include a second fail-protection pull-down circuit. Detailed Implementation

[0018] The embodiments described herein provide circuits and devices including a fail-protected pull-down circuit and a controllable turn-off time for the gate of a power switch. While the described example is explained in the case of a gallium nitride (GaN)-based gate-injected transistor (GIT) as the power switch, the technology can be applied to other transistor or semiconductor types, particularly including other enhancement-mode high electron mobility transistors (HEMTs) characterized by low turn-on / turn-off threshold voltages and low gate capacitance. The fail-protected pull-down circuit prevents the power switch from being unintentionally turned on due to spurious noise or ringing, does not require a negative voltage at the gate of the power switch, and provides a controllable turn-off time for the power switch. Additional fail-protected pull-down circuitry can be provided to ensure that the power switch remains off when in a power-off state—during which no switching of the power switch occurs. Therefore, many problems associated with applying a negative voltage to the gate of the power switch are avoided.

[0019] Embodiments are primarily described in the case of power switching devices in which the fail-safe pull-down circuit and the power switch (e.g., GIT) are integrated within the same GaN semiconductor die. However, the die can similarly be constructed from some other group III / V semiconductor or silicon-based semiconductor. The described integration of the fail-safe pull-down circuit and the power switch offers significant advantages in reliably maintaining the desired off (non-conductive) state of the power switch with a controllable off-time. In particular, such integration minimizes the parasitic inductance between the gate of the power switch and the fail-safe pull-down circuit, thereby constraining voltage ringing that may occur when the control voltage driven to the gate transitions between high and low voltage levels. The reduced ringing effectively clamps the gate-to-source voltage of the power switch to near zero during the off-time interval, preventing unintentional turn-on of the power switch. Integrating the fail-safe pull-down circuit in close proximity to the power switch also reduces interconnect paths (e.g., traces, terminals), thereby minimizing the possibility of noise coupling to the gate. This also prevents unintentional turn-on of the power switch, especially when no drive signal is applied to the gate during the startup interval. Controllable turn-off time provides a controlled turn-off speed for the power switch, for example, in high-power applications that may be subject to stringent EMI (electromagnetic interference) requirements and / or for added end-user configurability. Where the clamping capability of the main fail-safe pull-down circuit is limited under no-power / startup conditions, an additional fail-safe pull-down circuit ensures that the power switch remains open in the power-off state.

[0020] Although embodiments have been described primarily as integrated power switching devices comprising both a fail-protected pull-down circuit and a normally-off power transistor, the fail-protected pull-down circuit and normally-off power transistor can be provided on separate dies, i.e., they do not need to be monolithically integrated. Such a solution provides an improvement over existing circuitry used to control the GIT, but may not achieve the significant advantages of reduced noise (improved reliability) offered by integrated power devices.

[0021] Fail-protected pull-down circuits and normally-off power transistors can be provided on separate dies integrated within the same package (i.e., within a system-in-package or multi-chip module). Compared to solutions scattered across separate packages, such a system-in-package achieves reduced parasitics and improved reliability, but may not achieve the same performance level as solutions where the fail-protected pull-down circuits and normally-off power transistors are integrated on the same die.

[0022] Normally off power transistors (NOTs) can be controlled by drivers that are significantly simpler than typical drivers used to control gate transistors (GITs) and, in particular, avoid the complex switching sequences (state machines) within the driver and the circuitry used to generate negative voltages. Furthermore, NOTs can be controlled using only two voltage levels instead of the three or four voltage levels typically required to drive a GIT. Fail-protection pull-down circuits do not require separate control signaling and are efficiently controlled using the same two-level voltage signal driving the gate of the NOT (e.g., GIT). Therefore, the drivers described herein for controlling NOTs can be similar to other gate drivers, including those used in driving conventional MOSFETs.

[0023] Figure 1 The illustration shows an embodiment of a semiconductor device 100 including a normally off power transistor "T_Power" integrated in a semiconductor die 102. The normally off power transistor T_Power functions as a power switch, for example, as part of a switching power converter or other type of electrical power conversion or inverter system. In one embodiment, the semiconductor die 102 is a GaN die and the normally off power transistor T_Power is a GaN-based HEMT, such as GIT, which is a type of enhancement-mode HEMT. However, the semiconductor die 102 may include other group III / V semiconductors or silicon-based semiconductors, and / or the normally off power transistor T_Power may be another type of normally off power MOSFET.

[0024] Normally off power transistor T_Power has a drain "D" that is electrically connected to the first load terminal "D" of semiconductor die 102. POWERThe source terminal "S" is electrically connected to the second load terminal "S" of the semiconductor die 102. POWER ", and the gate "G" which is electrically connected to the control terminal "G" of the semiconductor die 102. POWER Each terminal D, S, G, "REF2", "REF1" of the semiconductor die 102 can be implemented as one or more bonding pads, pins, Cu pillars, etc. In each case, terminals D, S, G, REF2, REF1 provide external electrical access to the internal circuitry included in the semiconductor die 102.

[0025] Normally off power transistors (T_Power) are normally off devices, but can have relatively low threshold voltages for turning on or off, for example, in the range of 1.2 to 3.5V for GaN-based GITs. In addition to the potentially low gate capacitance of the normally off power transistor T_Power, this can also make it prone to unintentionally transitioning to a conducting state.

[0026] To prevent such unintentional switching, the semiconductor device 100 further includes a first fail-safe pull-down circuit 104. (As in...) Figure 1 As configured, during periods when the voltage supplied across the control terminal G and the first reference terminal REF1 of the semiconductor die 102 is lower than the turn-on voltage for the normally off power transistor T_Power, or when that voltage is not driven (e.g., when it is floating), the first fail-protection pull-down circuit 104 pulls the gate G of the normally off power transistor T_Power down. POWER Heyuanji S POWER The circuits are shorted together, resulting in no positive control voltage V. Power_GS This is used to connect the normally off power transistor T_Power. The first reference terminal REF1 can be an effective Kelvin source terminal or another type of dedicated small signal terminal, which is electrically connected to the source S of the normally off power transistor T_Power via the first fail-safe pull-down circuit 104. POWER The first reference terminal REF1 is the gate G of the normally off power transistor T_Power. POWER The external driver circuit provides a reference terminal.

[0027] The first fail-safe pull-down circuit 104 includes a first normally-on pull-down transistor T_PD1 integrated in the same semiconductor die 102 as the normally-off power transistor T_Power. For the illustrated example where the normally-off power transistor T_Power is a GaN-based GIT (enhancement-mode HEMT), the first normally-on pull-down transistor T_PD1 of the first fail-safe pull-down circuit 104 can be a depletion-mode GaN-based HEMT. When its gate-to-source voltage V... PD_GSFor a sufficiently negative value, for example, below the turn-off threshold voltage V typically in the range of -4V to -7V. PD_THR When this occurs, such a pull-down device is turned off (set to blocking mode). Otherwise, this includes when a zero pull-down gate-to-source voltage V is applied. PD_GS When there is no voltage across the gate "G" of the first normally-on pull-down transistor T_PD1 PD1 "and the source pole" S PD1 "When effectively driven, the first normally-on pull-down transistor T_PD1 conducts. The first normally-on pull-down transistor T_PD1 is positioned in the same semiconductor die 102 as the normally-off power transistor T_Power and is close to the gate G of the normally-off power transistor T_Power." POWER Heyuanji S POWER The way it is positioned makes it unlikely that the normally off power transistor T_Power will unintentionally switch to its on state.

[0028] The gate G of the first normally-on pull-down transistor T_PD1 in the first failure protection pull-down circuit 104 PD1 The first reference terminal REF1 is electrically connected to the semiconductor die 102. When no voltage is applied across the control terminal G and the first reference terminal REF1 of the semiconductor die 102, the first normally-on pull-down transistor T_PD1 will turn off the gate G of the normally-off power transistor T_Power. POWER Pull down to a voltage lower than the threshold voltage of the normally off power transistor T_Power.

[0029] The first fail-safe pull-down circuit 104 may further include a gate G connected to the first normally-on pull-down transistor T_PD1. PD1 Heyuanji S PD1 The pull-down control circuit 106 is located between the gates of the first normally-on pull-down transistor T_PD1 and the gate G. PD1 Heyuanji S PD1 A voltage is provided between them. For example, when an on-state voltage is applied between the control terminal G and the first reference terminal REF1 of the semiconductor die 102, the pull-down control circuit 106 can provide voltage relative to the source S of the first normally-on pull-down transistor T_PD1. PD1 The gate G of the first normally-on pull-down transistor T_PD1 PD1 A negative voltage is applied, and this is done autonomously, meaning that no separate external signal is required to control the pull-down control circuit 106. The pull-down control circuit 106 also autonomously discharges the negative voltage when the turn-on voltage is not applied between the control terminal G and the first reference terminal REF1 of the semiconductor die 102.

[0030] In one embodiment, the pull-down control circuit 106 includes a voltage clamp 108 and a pull-down resistor R. PD1During the interval when the normally off power transistor T_Power is turned on (conducted), the voltage clamp 108 generates a negative threshold voltage V lower than that required to turn off the first normally on pull-down transistor T_PD1. PD_THR Pull-down gate-to-source voltage V PD_GS The voltage clamp 108 can be, or can be modeled as, a diode with a threshold voltage. For example, the voltage clamp 108 can be, or can be modeled as... Figure 1 The Zener diode is indicated in the image. The forward threshold voltage for a typical diode is lower than the turn-off threshold voltage V of the first normally-on pull-down transistor T_PD1. PD_THR The amplitude. Therefore, the voltage clamp 108 may include several diodes cascaded (stacked) in series to achieve the clamping voltage VCL required to turn off the first normally-on pull-down transistor T_PD1, i.e., VCL > |V PD_THR |

[0031] Pull-down resistor R of pull-down control circuit 106 PD1 Ensure that the first normally-on pull-down transistor T_PD1 is reconnected under no-power / signal conditions. For example, if no voltage is driven across the control terminal G and the first reference terminal REF1 of semiconductor die 102, then the pull-down resistor R... PD1 Ensure the gate G of the first normally-on pull-down transistor T_PD1 PD1 Heyuanji S PD1 Pulled to the same voltage, for example, V PD_GS =0, thus turning on the first normally-on pull-down transistor T_PD1 to enable the gate G of the power transistor. POWER Short circuit to the source S of the power transistor POWER If the power transistor T_Power and the pull-down transistor T_PD1 are integrated in the same semiconductor die 102, then the pull-down resistor R PD1 It can also be integrated into the same semiconductor 102. In the example of the GaN semiconductor die 102, the pull-down resistor R... PD1 It can also be made of GaN. Specifically, the pull-down resistor R of the first fail-safe pull-down circuit 104... PD1 It may include one or more two-dimensional electron gas (2DEG) regions of GaN semiconductor die 102—which is essentially a gateless GaNHEMT.

[0032] Semiconductor device 100 also includes turn-off time control circuitry 110 for controlling the turn-off time of normally off power transistor T_Power. In some applications, such as high-power applications subject to stringent EMI requirements, a controlled turn-off speed for normally off power transistor T_Power may be desirable. A controlled turn-off speed for normally off power transistor T_Power also provides further end-user configurability.

[0033] The turn-off time control circuit 110 provides a controlled turn-off time for the normally off power transistor T_Power. The controlled turn-off time can be fixed (i.e., programmable at one time) or programmable (i.e., reprogrammable).

[0034] In one embodiment, the turn-off time control circuit 110 includes a first resistor R integrated in the same semiconductor die 102 as the normally off power transistor T_Power and the first normally on pull-down transistor T_PD1. OFF1 The first resistor R of the turn-off time control circuit 110 OFF1 The drain "D" of the first normally-on pull-down transistor T_PD1 is connected in series with ground. PD1 "and the gate G of the normally off power transistor T_Power" POWER Between. In the example of GaN semiconductor die 102, the first resistor R of the turn-off time control circuit 110... OFF1 It can also be made of GaN. In particular, the first resistor R OFF1 This may include one or more two-dimensional electron gas (2DEG) regions of a GaN semiconductor die 102—essentially a gateless GaN HEMT. More generally, the first resistor R OFF1 The resistance value at least partially determines the turn-off time of the normally off power transistor T_Power.

[0035] For example, the off-time control circuit 110 may also include a second resistor R. OFF2 It is located outside the semiconductor die 102 and is connected to the first resistor R. OFF1 Parallel electrical connection. In this example, R OFF1 ||R OFF2 Determine the turn-off time for the normally off power transistor T_Power. OFF1 It can have more than R OFF2 High resistance. In this case, R can be used. OFF2 To turn off the normally off power transistor T_Power more quickly, which may be more beneficial for low-power applications. OFF2 It can have a fixed resistance that is determined once. Alternatively, as by Figure 1 As indicated by the dashed slash in the image, R OFF2It may have a programmable resistor, and it can be adjusted accordingly, for example, based on the testing or monitoring of the semiconductor device 100. For example, R OFF2 This can be a programmable resistor included in a controller (not shown), which is configured to control the shutdown of the normally off power transistor T_Power during normal (field) operation. The controller can adjust R based on the operating state of the semiconductor device 100. OFF2 The value of .

[0036] Semiconductor die 102 may also include a first resistor R electrically connected to the off-time control circuit 110. OFF1 And the drain D of the first normally-on pull-down transistor T_PD1 PD1 The second reference terminal REF2 between nodes 112. If R is used OFF2 Then the second reference terminal REF2 of the semiconductor die 102 is the second resistor R of the turn-off time control circuit 110. OFF2 Provides an external electrical connection point. The first resistor R of the turn-off time control circuit 110. OFF1 Second resistor R OFF2 It is electrically connected in parallel between the control terminal G and the second reference terminal REF2 of semiconductor die 102. If the second resistor R is not used... OFF2 Therefore, the second reference terminal REF2 can be omitted. In this case, only the first resistor R... OFF1 Controls the turn-off of the normally off power transistor T_Power.

[0037] The first resistor R of the off-time control circuit 110 OFF1 The resistance can be set relatively high, for example, between 10Ω and 50Ω, so that even if the second resistor R of the turn-off time control circuit 110 is omitted... OFF2 It can also slow down the switching of the normally off power transistor T_Power, while still setting the slowest possible switching speed for T_Power. The turn-off speed of the normally off power transistor T_Power can be adjusted by including the switching speed with R... OFF1 Parallel R OFF2 To increase. R OFF2 The value can be less than R OFF1 And R OFF2 It can be placed as close as possible to the control terminal G and the second reference terminal REF2 of the semiconductor die 102 to minimize the parasitic inductance in the circuit. If R OFF2 If R is included in the shutdown time control circuit 110, then OFF2 and R OFF1 They can operate in parallel, and the total turn-off resistance as seen from the normally off power transistor T_Power becomes:

[0038] (1)

[0039] Where R para It is the inherent parasitic resistance of the monolithic turn-off path. R para It should be more than R OFF1 and R OFF2 Much smaller, thus without R OFF2 In the case of R OFF1 The gate impedance of the normally off power transistor T_Power should be controlled. This is achieved by connecting R... OFF2 The turn-off resistor R as seen from the normally off power transistor T_Power turn-off The turn-off speed of the normally off power transistor T_Power can be reduced by adjusting the gate G of the normally off power transistor T_Power. POWER The impedance is used for control.

[0040] Figure 2 The figure shows another embodiment of the semiconductor device 200, which includes a normally off power transistor T_Power, a first fail-safe pull-down circuit 104, and a turn-off time control circuit 110. Figure 2 The embodiments shown are similar to Figure 1 The embodiments shown are similar. However, the difference is that... Figure 2 The semiconductor device 200 shown further includes a second fail-protection pull-down circuit 202 integrated in the same semiconductor die 102 as the normally off power transistor T_Power and the first fail-protection pull-down circuit 104.

[0041] When the normally off power transistor T_Power is in a state where the switching of the normally off power transistor T_Power does not occur, the second failure protection pull-down circuit 202 will pull down the gate G of the normally off power transistor T_Power. POWER The voltage is pulled down to a level below the threshold voltage of the normally off power transistor T_Power. The power-off state can correspond to a low-power or no-power state, where the normally off power transistor T_Power does not switch for an extended period. For example, the power-off state can be a no-power state where no power is supplied to the semiconductor die 102, or an on-state where the normally off power transistor T_Power gradually transitions from a no-power state to a normal-power state.

[0042] The first resistor R of the off-time control circuit 110 OFF1 It can have relatively high resistance, as explained above, for example, between 10Ω and 50Ω. If R OFF1If the voltage is relatively high, the clamping capability of the first normally-on pull-down transistor T_PD1 in the first fail-safe pull-down circuit 104 may be limited. In this case, the pull-down effect provided by the first normally-on pull-down transistor T_PD1 in the power-off state may be weakened, which may lead to unintentional connection of the normally-off power transistor T_Power.

[0043] The second fail-safe pull-down circuit 202 compensates for the first resistor R of the turn-off time control circuit 110. OFF1 Any pull-down weakening caused by this. More specifically, the second fail-safe pull-down circuit 202 includes a second normally-on pull-down transistor T_PD2. Similar to the first normally-on pull-down transistor T_PD1, the second normally-on pull-down transistor T_PD2 is electrically connected to the gate G of the normally-off power transistor T_Power. POWER Heyuanji S POWER Between, and the gate G of the second normally-on pull-down transistor T_PD2 PD2 For example, through diode D B Electrically connected to the first reference terminal REF1 of semiconductor die 102. However, unlike the first normally-on pull-down transistor T_PD1, the drain D of the second normally-on pull-down transistor T_PD2... PD2 and the gate G of the normally off power transistor T_Power POWER No additional resistors are inserted in the path between them, making the second normally-on pull-down transistor T_PD2 stronger than the first normally-on pull-down transistor T_PD1. The pull-down provided by the first normally-on pull-down transistor T_PD1 is compensated or enhanced by the second normally-on pull-down transistor T_PD2, thereby preventing unintentional connection of the normally-off power transistor T_Power when in a power-off state.

[0044] Since the focus may be primarily on the weakened pull-down during the off-state of the normally-on power transistor T_Power, where the switching of the normally-on power transistor T_Power does not occur, the second fail-safe pull-down circuit 202 may further include a pull-down control circuit 204 to control when the second normally-on pull-down transistor T_PD2 conducts and when it does not conduct. When the second normally-on pull-down transistor T_PD2 does not conduct, the second normally-on pull-down transistor T_PD2 does not compensate the gate G of the power transistor. POWER The dropdown menu.

[0045] Pull-down control circuit 204 is connected to the gate G of the second normally-on pull-down transistor T_PD2. PD2 The source S of the second normally-on pull-down transistor T_PD2 PD2 Between. When the normally off power transistor T_Power is in the off state, the pull-down control circuit 204 will turn on the gate G of the second normally on pull-down transistor T_PD2. PD2 It remains above the turn-off voltage of the second normally-on pull-down transistor T_PD2.

[0046] In the illustrated example where the normally off power transistor T_Power is a GaN-based GIT (Enhancement-Type HEMT), the second normally on pull-down transistor T_PD2 of the second fail-safe pull-down circuit 202 can be a depletion-type GaN-based HEMT. When its gate-to-source voltage V... PD_GS When sufficiently negative, for example, below the turn-off threshold voltage V typically in the range of -4V to -7V. PD_THR When this occurs, such a pull-down device is turned off (set to blocking mode). Otherwise, this includes when a zero pull-down gate-to-source voltage V is applied. PD_GS2 When there is no voltage across the gate "G" of the second normally-on pull-down transistor T_PD2 PD2 "and the source pole" S PD2 "When driving is performed effectively, the second normally-on pull-down transistor T_PD2 conducts. In this case, G..." PD2 Maintaining the voltage above the turn-off voltage of the second normally-on pull-down transistor T_PD2 means that the pull-down control circuit 204 of the second fail-safe pull-down circuit 202 will... PD2 Maintaining the gate on above the negative threshold voltage ensures that the normally off power transistor T_Power remains off.

[0047] When the normally off power transistor T_Power is in a normal switching state, where it is successively turned on and off in response to the switch control signal input to the control terminal G of the semiconductor die 102, the pull-down control circuit 204 of the second fail-protection pull-down circuit 202 will pull the gate G of the second normally on pull-down transistor T_PD2. PD2 The voltage at the point drops below the turn-off voltage of the second normally-on pull-down transistor T_PD2. In one embodiment, the pull-down control circuit 204 of the second fail-safe pull-down circuit 202 includes a gate G electrically connected to the gate of the second normally-on pull-down transistor T_PD2. PD2 The source S of the second normally-on pull-down transistor T_PD2 PD2 The capacitor C between B The pull-down control circuit 204 of the second fail-safe pull-down circuit 202 further includes a gate G electrically connected to the second normally-on pull-down transistor T_PD2. PD2 The source S of the second normally-on pull-down transistor T_PD2 PD2 The resistor R between H .

[0048] Capacitors and resistors for C B R HThe RC time constant determines when the second normally-on pull-down transistor T_PD2 will turn on again after it has been previously turned off. Whenever the normally-off power transistor T_Power turns on, capacitor C... B It is recharged. When the normally off power transistor T_Power is in the normal switching state, the capacitor C B voltage V CB The gate G of the second normally-on pull-down transistor T_PD2 is continuously turned on. PD2 The voltage is maintained below the turn-off voltage of the second normally-on pull-down transistor T_PD2 to ensure that the second normally-on pull-down transistor T_PD2 remains off when the normally-off power transistor T_Power is in the normal switching state. In one embodiment, the capacitor and resistor pair C is selected. B R H The RC time constant ensures that when the normally off power transistor T_Power remains off for 1ms or longer, the capacitor voltage V... CB It rises above the turn-off voltage of the second normally-on pull-down transistor T_PD2.

[0049] As explained above, the initial switching on or startup from a no-power state is typically problematic because the main power switch must be clamped. Using the technique presented here, once power is applied between the control terminal and the first reference terminal REF1 of the semiconductor die 102, the capacitor C... B Charging begins. Once capacitor C... B voltage V CB When the turn-off voltage of the second normally-on pull-down transistor T_PD2 is reached, the second normally-on pull-down transistor T_PD2 will turn off and no longer contribute to the pull-down function.

[0050] Capacitors and resistors for C B R H The RC time constant can be programmed to take a longer time to re-turn on the second normally-on pull-down transistor T_PD2, as the additional pull-down function provided by the second normally-on pull-down transistor T_PD2 is most needed during the no-power state. Therefore, the capacitor and resistor are related to C. B R H The RC time constant can be programmed so that the second normally-on pull-down transistor T_PD2 is re-energized when the no-power state lasts for a long period (e.g., 1 ms or longer). The first fail-safe pull-down circuit 104 continues to operate during the normal on / off switching of the normally-off power transistor T_Power. Whenever the normally-off power transistor T_Power is energized, capacitor C... B It is "top-off" to a fully charged state, and the second normally-on pull-down transistor T_PD2 remains off. In one embodiment, capacitor C BIt is implemented as a metal-insulator-metal capacitor and the resistor R H It is a standard GaN resistor.

[0051] Figure 3 The diagram illustrates various waveforms obtained from simulation, including the gate-to-source voltage "NON VGS" of the second normally-on pull-down transistor T_PD1, the gate-to-source voltage "VGS" of the normally-off power transistor T_Power, the drain-to-source voltage "VDS" of the normally-off power transistor T_Power, and the gate current "Igate" of the normally-off power transistor T_Power. Capacitor C B Ensure that once the "Vsig" signal is applied to the control terminal G of semiconductor die 102, the second normally-on pull-down transistor T_PD2 is turned off, and ensure that as long as the capacitor C is connected... B voltage V CB Unless discharged below the turn-off threshold voltage of the second normally-on pull-down transistor T_PD2, the second normally-on pull-down transistor T_PD2 remains off. As long as frequent turn-on signals are applied to the control terminal G of the semiconductor die 102, the second normally-on pull-down transistor T_PD2 remains off and contributes little to the system's steady-state energy loss. If the turn-off period of the normally-off power transistor T_Power lasts for a sufficiently long period (toff), the second normally-on pull-down transistor T_PD2 turns on again. The off period can be calculated as follows:

[0052] (2)

[0053] Where Vth2 is the turn-off threshold voltage of the second normally-on pull-down transistor T_PD2, and V0 is the capacitor C when the normally-off power transistor T_Power is turned off. B The initial voltage.

[0054] like Figure 3 As indicated by the dashed waveform in the image, it can be achieved by including R OFF2 This controls the turn-off dv / dt delay for the normally off power transistor T_Power. It's worth noting that this can be achieved by appropriately adjusting R. OFF1 and R OFF2 This controls the turn-off "VDS" waveform for the normally off power transistor T_Power. Figure 4 China has emphasized this aspect even more. Figure 4 It shows that for only R OFF1 =100Ω (without R) OFF2 For R OFF1 =100Ω and R OFF2 =10Ω, and for R OFF1 =100Ω and R OFF2Simulation results of the dv / dt slew rate of the power switch off for a 50Ω capacitor. Capacitor voltage V CB For the normally off power transistor T_Power, it remains mostly at approximately -8V during the entire on / off switching period, and according to R... H The value of R decays slowly. H Examples can range from 1MΩ to 5MΩ.

[0055] Because of R OFF2 (If used) it is located outside the semiconductor die 102, so some parasitic inductance will be related to R. OFF2 Series connection. Simulation results show little to no difference between it and 0nH and 4nH, where 4nH may be achieved using an external resistor. With R OFF2 Poor design of a 20nH series circuit may affect turn-off behavior, but with R OFF2 Compared to the influence of the value, this influence is insignificant.

[0056] The pull-down control circuit 204 of the second fail-safe pull-down circuit 202 may further include a diode D. B This is used to isolate the first fail-protection pull-down circuit 104 from the second fail-protection pull-down circuit 202. In the illustrated example, diode D... B With capacitor C B A diode D is connected in series and electrically to the first reference terminal REF1 of semiconductor die 102 to provide fail-safe pull-down circuit isolation. B To prevent interference between the parallel-connected failure protection pull-down circuits 104 and 202.

[0057] The second fail-safe pull-down circuit 202 is optional. Depending on the ohm rating of the normally off power transistor T_Power, the second fail-safe pull-down circuit 202 can be omitted. For example, if the normally off power transistor T_Power is a high-ohm device, then a high value of R... OFF1 It might be good enough so that even R OFF2 The gate of the unconnected power transistor is also clamped. POWER In this case, the second fail-safe pull-down circuit 202 can be omitted.

[0058] The programmable shutdown fail-protection pull-down technology described herein can be applied to any power switching concept employing fail-protection pull-down circuits. The following describes some embodiments of additional power switching systems incorporating one or both of the fail-protection pull-down circuits 104, 202.

[0059] Figure 5 The illustration shows an embodiment of two fail-safe pull-down circuits 104 and 202 implemented in a transformer-based switching device 300.Figure 5 The transformer-based switching device 300 shown in the figure is... Figure 1 and Figure 2 The semiconductor devices 100 and 200 shown in the diagram are similar. However, the difference is that AC energy is supplied from a transformer (not shown) to the differential control inputs IN+ / IN- of the transformer-based switching device 300. Figure 5 In the middle, if the external connection is R OFF2 The die terminals marked "G" and "REF2" allow R OFF1 and R OFF2 The parallel connection is as explained previously. Rectifier 302 converts the AC energy at the differential control inputs IN+ / IN- into a DC voltage suitable for turning on and off the normally off power transistor T_Power. For example, rectifier 302 can convert the AC energy at the differential control inputs IN+ / IN- into a DC gate-to-source voltage V. GS DC gate-to-source voltage V GS A voltage greater than the threshold voltage of the normally off power transistor T_Power plus the clamping voltage of the clamping diode (which is greater than the threshold voltage of the normally on device T_PD1, for example, 3.3V + 7V) is applied to connect the normally off power transistor T_Power. In the illustrated example, rectifier 302 is implemented as two half-bridges, each half-bridge formed by a first gate-controlled diode Q1 / Q3 connected in series with a second gate-controlled diode Q2 / Q4. Other types of rectifier devices can be used, such as diodes, synchronous rectifier devices, etc.

[0060] Figure 6 The illustration shows another embodiment of a transformer-based switching device 400. Figure 6 The embodiments shown are similar to Figure 5 The embodiments shown are similar. However, the difference is that... Figure 6 The transformer-based switching device 400 includes a first fail-protection pull-down circuit 104 but does not include a second fail-protection pull-down circuit 202. Figure 5 The transformer-based switching device 300 in the middle can be implemented in low-ohm GaN applications, while Figure 6 The transformer-based switching device 400 can be implemented in high-ohm GaN applications where additional gate clamping / pull-down functionality provided by the second fail-safe pull-down circuit 202 is not required.

[0061] Figure 7The illustration shows another embodiment of a semiconductor device 500 including two fail-protected pull-down circuits 104, 202. In the illustrated example, the semiconductor device 500 also includes both the fail-protected pull-down circuits 104, 202 and a resistor modulation circuit 502. The resistor modulation circuit 502 implements on-time control for the normally off power transistor T_Power and includes a voltage clamp 504 that autonomously provides desired control for the first normally on pull-down transistor T_PD1 of the first fail-protected pull-down circuit 104. The voltage clamp 504 is configured to generate a negative threshold voltage V lower than the negative threshold voltage V required to turn off the first normally on pull-down transistor T_PD1 during the interval when the normally off power transistor T_Power is on (conducting). PD_THR Pull-down gate-to-source voltage V PD_GS The voltage clamp 504 can be, or can be modeled as, a diode with a threshold voltage. The forward threshold voltage for a typical diode is lower than the turn-off threshold voltage V of the first normally-on pull-down transistor T_PD1. PD_THR The amplitude. Although illustrated as a single diode, voltage clamp 504 can actually include several individual diodes cascaded (stacked) in series to achieve the clamping voltage V required to turn off the first normally-on pull-down transistor T_PD1. CL V CL >|V PD_THR |

[0062] The resistor modulation circuit 502 also includes a modulation switch Q. MOD It changes the resistance of the gate path loop of the normally off power transistor T_Power when the normally off power transistor T_Power is turned on and the first normally on pull-down transistor T_PD1 is turned off. This gate path loop is the current loop from the control terminal G of the semiconductor die 102 to the first reference terminal REF1, and when the normally off power transistor T_Power is turned on, it includes the gate of the normally off power transistor T_Power, the source of the normally off power transistor T_Power, and the path back to the first reference terminal REF1 through the first fail-safe pull-down circuit 104. When the modulation switch Q... MOD When connected, via modulation switch Q MOD A low-impedance path is formed with voltage clamp 504, and modulation switch Q MOD Each of the voltage clamps 504 provides negligible resistance. When the modulation switch Q... MOD When turned off, instead, current is forced to flow through resistor R. BYP At least with the modulation switch Q MOD The current path compared to resistor R BYP Provides a high-impedance path. When the modulation switch Q... MOD The low-impedance path presented during switching on provides a high-current transition pulse. When the modulation switch Q...MOD The high-impedance path presented during turn-off provides a low level of current to maintain the on-state of the normally off power transistor T_Power.

[0063] The modulation switch Q shown in the figure MOD It is a normally-on (depletion-type) HEMT, and preferably integrated with a normally-off power transistor T_Power in the same GaN die 102. Modulation switch Q MOD With associated gate-to-source capacitance C GS It can be a modulation switch Q, rather than a separate component. MOD The inherent capacitance. This capacitance C GS exist Figure 7 The value is explicitly shown because it affects the duration of the high-current pulse. Modulation resistor R MOD The gate of the first reference terminal REF1 and the first normally-on pull-down transistor T_PD1 are coupled to the modulation switch Q. MOD The gate, and the modulation resistor R MOD The resistor is selected to achieve the desired duration of the high-current pulse. An additional resistor R... SS It can be coupled between the first reference terminal REF1 and the source node / potential of semiconductor device 500. Modulation resistor R MOD and / or an additional resistor R SS This can be an external resistor. In this case, the semiconductor die 102 may include a resistor R for connection. MOD R SS Additional terminals Rm and Ks, wherein terminal Ks can be an effective Kelvin source terminal or electrically connected to the source S of normally off power transistor T_Power. POWER Another type of dedicated small signal terminal.

[0064] Figure 8 The illustration shows another embodiment of a semiconductor device 600 including a resistor modulation circuit 502. Figure 8 The embodiments shown are similar to Figure 7 The embodiments shown are similar. However, the difference is that... Figure 8 The semiconductor device 600 includes a first fail-protection pull-down circuit 104 but does not include a second fail-protection pull-down circuit 202. Figure 7 The semiconductor device 500 in the middle can be implemented in low-ohm GaN applications, while Figure 8 The semiconductor device 600 can be implemented in high-ohmic GaN applications where additional gate clamping / pull-down functionality provided by the second fail-safe pull-down circuit 202 is not required.

[0065] Although this disclosure is not limited thereto, the examples numbered below illustrate one or more aspects of this disclosure.

[0066] Example 1. A semiconductor device comprising: a normally off power transistor integrated in a semiconductor die, wherein the gate of the normally off power transistor is electrically connected to a control terminal of the semiconductor die; and a first fail-safe pull-down circuit including a first normally on pull-down transistor integrated in the semiconductor die, wherein the gate of the first normally on pull-down transistor is electrically connected to a first reference terminal of the semiconductor die, wherein the first normally on pull-down transistor is configured to pull down the gate of the normally off power transistor to a voltage below a threshold voltage of the normally off power transistor when no voltage is applied across the control terminal and the first reference terminal; and a turn-off time control circuit configured to control the turn-off time of the normally off power transistor.

[0067] Example 2. The semiconductor device of Example 1, wherein the off-time control circuitry includes a first resistor integrated in the semiconductor die and electrically connected in series between the gates of a first normally-on pull-down transistor and a normally-off power transistor.

[0068] Example 3. The semiconductor device of Example 2, wherein the off-time control circuitry further includes a second resistor external to the semiconductor die and electrically connected in parallel with the first resistor.

[0069] Example 4. The semiconductor device of Example 3, wherein the first resistor has a higher resistance than the second resistor.

[0070] Example 5. A semiconductor device of Example 3 or 4, wherein the second resistor has a fixed resistance.

[0071] Example 6. A semiconductor device of Example 3 or 4, wherein the second resistor has a programmable resistance.

[0072] Example 7. A semiconductor device of any one of Examples 3, 4 and 6, wherein the second resistor is a programmable resistor included in a controller configured to control the switch of a normally off power transistor.

[0073] Example 8. A semiconductor device of any one of Examples 3 to 7, wherein the semiconductor die includes a second reference terminal electrically connected to a node between a first resistor and a first normally-on pull-down transistor, and wherein both the first resistor and the second resistor are electrically connected between a control terminal and the second reference terminal.

[0074] Example 9. A semiconductor device of any one of Examples 1 to 8, wherein the first fail-safe pull-down circuit further includes a pull-down control circuit connected between the gate and the source of the first normally-on pull-down transistor, and wherein the pull-down control circuit is configured to autonomously apply a negative voltage relative to the source of the first normally-on pull-down transistor to the gate of the first normally-on pull-down transistor when an on-state voltage is applied between a control terminal and a first reference terminal, and to autonomously discharge the negative voltage when an on-state voltage is not applied between the control terminal and the first reference terminal.

[0075] Example 10. A semiconductor device of any one of Examples 1 to 9, further comprising: a second fail-safe pull-down circuit configured to pull down the gate of the normally off power transistor to a voltage below the threshold voltage of the normally off power transistor when the normally off power transistor is in an off state in which no switching of the normally off power transistor occurs.

[0076] Example 11. The semiconductor device of Example 10, wherein the second fail-safe pull-down circuit includes: a second normally-on pull-down transistor integrated in a semiconductor die, wherein the gate of the second normally-on pull-down transistor is electrically connected to a first reference terminal, for example, via a diode; and a pull-down control circuit connected between the gate of the second normally-on pull-down transistor and the source of the second normally-on pull-down transistor, wherein the pull-down control circuit is configured to hold the gate of the second normally-on pull-down transistor above the turn-off voltage of the second normally-on pull-down transistor when the normally-off power transistor is in a de-energized state.

[0077] Example 12. The semiconductor device of Example 11, wherein the pull-down control circuit is configured to reduce the voltage at the gate of the second normally-on pull-down transistor to below the turn-off voltage of the second normally-on pull-down transistor when the normally-off power transistor is in a normal switching state in which the normally-off power transistor is successively turned on and off in response to a switch control signal input to the control terminal.

[0078] Example 13. A semiconductor device of Example 11 or 12, wherein the pull-down control circuitry includes: a capacitor electrically connected between the gate of a second normally-on pull-down transistor and the source of a second normally-on pull-down transistor; and a third resistor electrically connected between the gate of the second normally-on pull-down transistor and the source of the second normally-on pull-down transistor.

[0079] Example 14. The semiconductor device of Example 13, wherein the RC time constant of the capacitor and resistor determines when a second normally-on pull-down transistor is turned on again after it has been previously turned off.

[0080] Example 15. A semiconductor device of Example 13 or 14, wherein a capacitor is recharged whenever a normally off power transistor is turned on, and wherein when the normally off power transistor is in a normal switching state in which the normally off power transistor is successively turned on and off in response to a switch control signal input to a control terminal, the voltage of the capacitor continuously holds the gate of a second normally on pull-down transistor below the turn-off voltage of the second normally on pull-down transistor.

[0081] Example 16. The semiconductor device of Example 15, wherein when the normally off power transistor remains off for 1 ms or longer, the capacitor voltage rises above the turn-off voltage of the second normally on pull-down transistor.

[0082] Example 17. A semiconductor device of any one of Examples 13 to 16, wherein the pull-down control circuitry further includes: a diode connected in series with a capacitor and electrically connected to a first reference terminal such that the diode isolates the first fail-protected pull-down circuitry from the second fail-protected pull-down circuitry.

[0083] Example 18. A semiconductor device of any one of Examples 1 to 17, wherein the semiconductor die is a GaN die, wherein the normally off power transistor is a normally off GaN HEMT (high electron mobility transistor), and wherein the first normally on pull-down transistor is a normally on GaN HEMT.

[0084] Example 19. A semiconductor device of any one of Examples 1 to 18, wherein the semiconductor die includes a second reference terminal electrically connected to a node between a first resistor and a first normally-on pull-down transistor.

[0085] Example 20. A semiconductor die includes: a control terminal; a first reference terminal; a normally off power transistor having a gate electrically connected to the control terminal; and a first fail-safe pull-down circuit including: a first normally on pull-down transistor having a gate electrically connected to the first reference terminal, wherein the first normally on pull-down transistor is configured to pull down the gate of the normally off power transistor to a voltage below a threshold voltage of the normally off power transistor when no voltage is applied across the control terminal and the first reference terminal; and a first resistor electrically connected in series between the gate of the first normally on pull-down transistor and the gate of the normally off power transistor.

[0086] Example 21. The semiconductor die of Example 20 further includes: a second fail-safe pull-down circuit configured to pull down the gate of the normally off power transistor to a voltage below the threshold voltage of the normally off power transistor when the normally off power transistor is in an off state in which the switching of the normally off power transistor does not occur.

[0087] Example 22. The semiconductor die of Example 20 or 21 further includes: a second reference terminal electrically connected to a node between a first resistor and the drain of a first normally-on pull-down transistor.

[0088] As used herein, the terms “having,” “containing,” “including,” and “including” are open-ended terms that indicate the presence of the stated element or feature but do not exclude additional elements or features. The quantifiers “a,” “one,” and the pronoun “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0089] It should be understood that, unless otherwise specifically indicated, the features of the various embodiments described herein can be combined with each other.

[0090] While specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various substitutions and / or equivalent implementations may be made in place of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor device, comprising: A normally off power transistor integrated in a semiconductor die, wherein the gate of the normally off power transistor is electrically connected to the control terminal of the semiconductor die; as well as The first fail-safe pull-down circuit includes: A first normally-on pull-down transistor integrated in a semiconductor die, wherein the gate of the first normally-on pull-down transistor is electrically connected to a first reference terminal of the semiconductor die, wherein the first normally-on pull-down transistor is configured to pull down the gate of a normally-off power transistor to a voltage lower than the threshold voltage of the normally-off power transistor when no voltage is applied across the control terminal and the first reference terminal; as well as A turn-off time control circuit, configured to control the turn-off time of normally off power transistors. The off-time control circuit includes a first resistor integrated in the semiconductor die and connected in series between the gates of the first normally-on pull-down transistor and the normally-off power transistor.

2. The semiconductor device of claim 1, wherein the off-time control circuit further includes a second resistor, the second resistor being external to the semiconductor die and electrically connected in parallel with the first resistor.

3. The semiconductor device of claim 2, wherein the first resistor has a higher resistance than the second resistor.

4. The semiconductor device of claim 2, wherein the second resistor has a fixed resistance.

5. The semiconductor device of claim 2, wherein the second resistor has a programmable resistor.

6. The semiconductor device of claim 2, wherein the second resistor is a programmable resistor included in a controller configured to control the switch of a normally off power transistor.

7. The semiconductor device of claim 2, wherein the semiconductor die includes a second reference terminal electrically connected to a node between a first resistor and a first normally-on pull-down transistor, and wherein both the first resistor and the second resistor are electrically connected between a control terminal and a second reference terminal.

8. The semiconductor device of claim 1, wherein the first fail-safe pull-down circuit further comprises a pull-down control circuit connected between the gate of the first normally-on pull-down transistor and the source of the first normally-on pull-down transistor, and wherein the pull-down control circuit is configured to autonomously apply a negative voltage relative to the source of the first normally-on pull-down transistor to the gate of the first normally-on pull-down transistor when an on-state voltage is applied between the control terminal and the first reference terminal, and to autonomously discharge the negative voltage when an on-state voltage is not applied between the control terminal and the first reference terminal.

9. The semiconductor device according to claim 1, further comprising: The second fail-safe pull-down circuit is configured to pull down the gate of the normally off power transistor to a voltage lower than the threshold voltage of the normally off power transistor when the normally off power transistor is in a de-energized state during which the switching of the normally off power transistor does not occur.

10. The semiconductor device of claim 9, wherein the second fail-safe pull-down circuit comprises: A second normally-on pull-down transistor integrated in a semiconductor die, wherein the gate of the second normally-on pull-down transistor is electrically connected to a first reference terminal; as well as A pull-down control circuit is connected between the gate of the second normally-on pull-down transistor and the source of the second normally-on pull-down transistor, wherein the pull-down control circuit is configured to hold the gate of the second normally-on pull-down transistor above the turn-off voltage of the second normally-on pull-down transistor when the normally-off power transistor is in a de-energized state.

11. The semiconductor device of claim 10, wherein the pull-down control circuit is configured to reduce the voltage at the gate of the second normally-on pull-down transistor to below the turn-off voltage of the second normally-on pull-down transistor when the normally-off power transistor is in a normal switching state in which the normally-off power transistor is successively turned on and off in response to a switch control signal input to the control terminal.

12. The semiconductor device of claim 10, wherein the pull-down control circuit comprises: A capacitor is electrically connected between the gate of the second normally-on pull-down transistor and the source of the second normally-on pull-down transistor; as well as The third resistor is electrically connected between the gate of the second normally-on pull-down transistor and the source of the second normally-on pull-down transistor.

13. The semiconductor device of claim 12, wherein the RC time constant of the capacitor and resistor determines when the second normally-on pull-down transistor is turned on again after it has been previously turned off.

14. The semiconductor device of claim 12, wherein the capacitor is recharged whenever the normally off power transistor is turned on, and wherein when the normally off power transistor is in a normal switching state in which the normally off power transistor is successively turned on and off in response to a switch control signal input to the control terminal, the voltage of the capacitor continuously holds the gate of the second normally on pull-down transistor below the turn-off voltage of the second normally on pull-down transistor.

15. The semiconductor device of claim 14, wherein when the normally off power transistor remains off for 1 ms or longer, the capacitor voltage rises above the turn-off voltage of the second normally on pull-down transistor.

16. The semiconductor device of claim 12, wherein the pull-down control circuit further comprises: A diode, which is connected in series with a capacitor and electrically connected to a first reference terminal, such that the diode isolates the first fail-safe pull-down circuit from the second fail-safe pull-down circuit.

17. The semiconductor device of claim 1, wherein the semiconductor die is a GaN die, wherein the normally off power transistor is a normally off GaN HEMT (high electron mobility transistor), and wherein the first normally on pull-down transistor is a normally on GaNHEMT.

18. The semiconductor device of claim 1, wherein the semiconductor die includes a second reference terminal electrically connected to a node between the first resistor and the first normally-on pull-down transistor.

19. A semiconductor die, comprising: Control terminals; First reference terminal; Normally off power transistor, which has a gate that is electrically connected to a control terminal; as well as The first fail-safe pull-down circuit includes: A first normally-on pull-down transistor has a gate electrically connected to a first reference terminal, wherein the first normally-on pull-down transistor is configured to pull down the gate of a normally-off power transistor to a voltage below a threshold voltage of the normally-off power transistor when no voltage is applied across the control terminal and the first reference terminal. as well as The first resistor is connected in series between the gates of the first normally-on pull-down transistor and the normally-off power transistor.

20. The semiconductor die according to claim 19, further comprising: The second fail-safe pull-down circuit is configured to pull down the gate of the normally off power transistor to a voltage lower than the threshold voltage of the normally off power transistor when the normally off power transistor is in a de-energized state during which the switching of the normally off power transistor does not occur.

21. The semiconductor die according to claim 19, further comprising: The second reference terminal is electrically connected to the node between the first resistor and the drain of the first normally-on pull-down transistor.

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