Classification and sorting system and method based on cascaded H-bridge DC side capacitor voltage balance

Abstract

The present invention discloses a classification and sorting system based on the voltage balance of the DC side capacitors of a cascaded H-bridge, comprising a cascaded H-bridge module, a sampling module, a sorting algorithm module, a submodule switch state calculation module, an integer module, a decimal module, and a switch generation module; the classification and sorting method of the present invention classifies the submodules according to their different states of being on and off at the end of the current cycle, and sums the capacitor voltages of the submodules in the on state at the end of the current cycle u sum The absolute value of the reference voltage output by the cascaded H-bridge |u ref Compare the capacitor voltages based on the comparison results, calculate the number of newly added or removed submodules, and determine the next cycle's operating mode based on the integer portion of the newly removed submodules and the submodules requiring PWM modulation, based on the operating modes of the previous and current cycles. This invention can reduce the switching frequency of the submodules and minimize switching losses in the switch tubes.

Description

Technical Field

[0001] The present invention relates to a classification and sorting method for capacitor voltage balance, and in particular to a classification and sorting system and method based on cascaded H-bridge DC side capacitor voltage balance. Background Art

[0002] Cascaded H-bridges, consisting of structurally identical H-bridge units, facilitate modular design. They eliminate the need for large-capacity energy storage components like capacitors and inductors, making it easy to expand the number of power levels and effectively improving the voltage and power ratings of power electronic devices. By cascading power modules, the device's voltage level can be adjusted by varying the number of modules in series. This flexible circuit structure is more practical and economical, offering significant advantages in high-voltage, high-power systems. The cascaded H-bridge multilevel topology is widely used in high-power applications such as active power filters and static VAR compensators. However, the main circuit topology of the cascaded H-bridge can lead to unbalanced and unstable DC-side capacitor voltages, necessitating voltage balancing.

[0003] The main modulation strategies for cascaded H-bridges include carrier phase-shift modulation and sorting algorithm modulation. Carrier phase-shift modulation uses a regular sampling method and modulates the signal once every half cycle or a full cycle. The phases of the phase-shifted carriers are offset by a certain angle and compared with the modulating signal, with the duty cycle changing sequentially. However, sorting algorithm modulation can achieve switching state changes for all submodules within a single switching cycle, resulting in a faster switching speed. The main idea behind traditional sorting algorithm modulation is to minimize the DC-side capacitor voltage deviation of each submodule at any given time. Voltage and current sampling modules continuously sample the capacitor voltage values and bridge arm current directions of each submodule. The actual capacitor voltages of each module are then sorted, and the corresponding drive signals are assigned to the appropriate submodules. Traditional sorting algorithms control the signal according to the specified positive bridge arm current direction. If the measured bridge arm current is positive, the corresponding number of submodules are activated in ascending capacitor voltage order, while the remaining submodules are deactivated. If the measured bridge arm current is negative, the corresponding number of submodules are activated in the reverse order, while the remaining submodules are deactivated. In this continuous switching process, half a cycle or a whole cycle always ensures that the sub-module with lower voltage is charged and discharged first, ensuring that the capacitor voltages of each sub-module on the cascade H-bridge reach a dynamic balance.

[0004] Traditional sorting algorithms determine the order of capacitor charging and discharging based on capacitor voltage levels. This modulation method has inherent flaws. It fails to consider the potential for frequent switching of a submodule's switches when capacitor voltages are very close or when voltage sensors have errors, and fails to consider the need to reduce the switching frequency of the switching devices. High frequencies inevitably lead to increased switching losses, and frequent switching also has a certain impact on the lifespan of the submodules. Therefore, it is necessary to improve the modulation strategy of the traditional sorting algorithm to minimize the number of switching cycles while ensuring balanced capacitor voltages. Summary of the Invention

[0005] Purpose of the invention: The purpose of the present invention is to provide a classification and sorting system and method based on the voltage balance of the cascaded H-bridge DC side capacitors, which can reduce the switching loss of the switching tube and average the loss of the switching tube inside the sub-module.

[0006] Technical solution: The classification and sorting system of the present invention includes a cascade H-bridge module, a sampling module, a sorting algorithm module, a submodule switch state calculation module, an integer module, a decimal module, and a switch generation module;

[0007] The input end of the cascade H-bridge module is connected to the output end of the switch generation module, and the output end is connected to the sampling module;

[0008] The sampling module collects the current i flowing into the cascade H bridge s and the capacitor voltages of N submodules are sent to the sorting algorithm module;

[0009] The sorting algorithm module sorts the capacitor voltages of the input state submodule or the removed state submodule at the end of this cycle, and sends the sorting result to the submodule switch state calculation module;

[0010] The output end of the submodule switch state calculation module is connected to the integer module; the submodule switch state switching module in the integer module switches the switch state of the submodule;

[0011] The output end of the integer module is connected to the decimal module; the modulation comparison module in the decimal module performs PWM modulation on each submodule;

[0012] The output end of the decimal module is connected to the switch generating module.

[0013] The classification and sorting method of the present invention comprises the following steps:

[0014] S1, connect N submodules in series to form a cascade H-bridge;

[0015] S2, the sampling module collects the current i flowing into the cascade H bridge sand the capacitor voltage u of N submodules c1 、u c2 、u c3 、……、u cN ;

[0016] S3, in the sorting algorithm module, the capacitor voltage u of N submodules is calculated based on the different states of the submodules at the end of this cycle. c1 、u c2 、u c3 、……、u cN Classify; at the end of this cycle, the sum of the capacitor voltages of the submodules in the active state is recorded as u sum , and the absolute value of the output reference voltage given by the cascaded H-bridge |u ref | Compare, sort the capacitor voltages according to the comparison results;

[0017] S4, submodule working state calculation, according to Δu, calculate the number of submodules in the next cycle that are newly put into operation or the number of submodules in the new removal state, where Δu = |u ref |-u sum ;

[0018] S5, in the submodule switch state switching module of the integer module, the switch state of the first K submodules is switched. When a new integer is added, the first K submodules are switched from the cut-off state to the put-in state;

[0019] When a new integer is removed, the first K submodules are switched from the input state to the removed state, according to the last removed state setting;

[0020] S6, in the modulation comparison module of the decimal module, PWM modulation is performed on the K+1th submodule. The K+1th submodule needs to determine the order of activation or deactivation in the next cycle based on its state at the end of the current cycle;

[0021] S7, the switch generation module transmits the switch signal to all sub-modules in the cascade H-bridge module.

[0022] Further, in step S3, when this cycle ends, u sum <|u ref |, then sort the capacitor voltages of the submodules in the cut-off state at the end of this cycle;

[0023] When u sum >|u ref |, then sort the capacitor voltages of the submodules that are in the ON state at the end of this cycle;

[0024] When u sum =|u ref |, then at the end of this cycle, the capacitor voltages of the submodules will not be sorted.

[0025] Further, in step S4,

[0026] 41) When u sum <|u ref |, let i s *u ref >0, the capacitor voltages of the submodules in the cut-off state are sequentially input in ascending order. When the sum of the capacitor voltages of the K submodules before the cut-off state is less than Δu, and the sum of the capacitor voltages of the K+1 submodules before the cut-off state is greater than Δu, the K submodules before the cut-off state enter the integer module, and the K+1 submodule enters the decimal module;

[0027] Assume i s *u ref <0, the capacitor voltages of the submodules in the cut-off state are put into operation in descending order. When the sum of the capacitor voltages of the K submodules before the cut-off state is less than Δu, and the sum of the capacitor voltages of the K+1 submodules before the cut-off state is greater than Δu, the K submodules before the cut-off state enter the integer module, and the K+1 submodule enters the decimal module.

[0028] 42) When u sum >|u ref |, let i s *u ref >0, the capacitor voltages of the submodules in the input state are cut off in descending order. When the sum of the capacitor voltages of the K submodules before the input state is less than -Δu, and the sum of the capacitor voltages of the K+1 submodules before the input state is greater than -Δu, the K submodules before the input state enter the integer module, and the K+1 submodule enters the decimal module;

[0029] Assume i s *u ref <0, the capacitor voltages of the submodules in the input state are cut off in ascending order. When the sum of the capacitor voltages of the K submodules before the input state is less than -Δu, and the sum of the capacitor voltages of the K+1 submodules before the input state is greater than -Δu, the K submodules before the input state enter the integer module, and the K+1 submodule enters the decimal module;

[0030] 43) When u sum =|u ref |, each submodule maintains its original input state or original cut-off state.

[0031] Furthermore, in step S6, when the current cycle ends, the submodule works in the cut-off state, and the (1-D)T s Time, first keep the working mode of the submodule unchanged, and then switch to the input state, where D represents the duty cycle;

[0032] When this cycle ends, the submodule is in the input state, and the DT at the beginning of the next cycle s Time, first keep the working mode of the submodule unchanged, and then switch to the cut-off state, set according to the last cut-off state; Ts represents the equivalent switching period.

[0033] Further, in step S6, the cascade H-bridge switch state is divided into an input mode and a cut-off state according to the basis of the last cut-off state setting;

[0034] When a submodule switches from the on state to the off state, the mode of the submodule in the last off state determines the mode of the submodule in the next cycle off state.

[0035] Compared with the prior art, the present invention has the following significant effects:

[0036] 1. Under the premise of ensuring the voltage balance of the capacitors on the DC side of the cascaded H-bridge, the switching order of the sub-module states in the next cycle is determined according to the working status of the sub-modules in the current cycle, minimizing the number of sub-module mode switching and the switching action frequency, effectively reducing the switching loss of the switch tube;

[0037] 2. For two removal modes with the same effect, the submodules are made to enter the two removal modes in turn, thereby averaging the losses of the switch tubes inside the submodules. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a structural block diagram of the present invention;

[0039] Figure 2 This is a flow chart of the sorting method;

[0040] Figure 3(a) is a detailed implementation diagram of the new investment;

[0041] Figure 3(b) shows the specific implementation diagram of the newly added resection. DETAILED DESCRIPTION

[0042] The present invention will be described in further detail below with reference to the accompanying drawings and specific implementations.

[0043] like Figure 1 The system structure of the present invention includes a cascade H-bridge module, a sampling module, a sorting algorithm module, a sub-module switch state calculation module, an integer module, a decimal module, and a switch generation module.

[0044] The input end of the cascade H-bridge module is connected to the switch generation module, and the output end is connected to the sampling module;

[0045] The input end of the sampling module is connected to the cascade H-bridge module, and the output end is connected to the sorting algorithm module;

[0046] The input end of the sorting algorithm module is connected to the sampling module, and the output end is connected to the submodule switch state calculation module;

[0047] The input end of the submodule switch state calculation module is connected to the sorting algorithm module, and the output end is connected to the integer module;

[0048] The input end of the integer module is connected to the submodule switch state calculation module, and the output end is connected to the decimal module;

[0049] The input end of the decimal module is connected to the integer module, and the output end is connected to the switch generation module;

[0050] The input end of the switch generation module is connected to the decimal module, and the output end is connected to the cascade H-bridge module;

[0051] The classification and sorting algorithm of the present invention comprises the following steps:

[0052] Step 1: Connect N submodules in series to form a cascade H-bridge.

[0053] Step 2: The sampling module collects the current i flowing into the cascade H-bridge s and the capacitor voltage u of N submodules c1 、u c2 、u c3 、……、u cN .

[0054] Step 3: In the sorting algorithm module, the capacitor voltage u of N submodules is calculated based on the different states of the submodules at the end of this cycle. c1 、u c2 、u c3 、……、u cN Classification; at the end of this cycle, the sum of the capacitor voltages of the submodules in the input state is recorded as u sum , and the absolute value of the output reference voltage given by the cascaded H-bridge |u ref |Compare and sort different capacitor voltages according to the comparison results.

[0055] like Figure 2 As shown, when this cycle ends, the capacitor voltage and u sum Less than the absolute value of the output reference voltage given by the cascaded H-bridge |u ref |, then sort the capacitor voltages of the submodules in the cut-off state at the end of this cycle;

[0056] When this cycle ends, the capacitor voltage and u sum Greater than the absolute value of the output reference voltage given by the cascaded H-bridge |u ref |, then the capacitor voltages of the submodules put into state at the end of this cycle will be sorted.

[0057] Input state submodule capacitor voltage and u sum Equal to the absolute value of the output reference voltage given by the cascaded H-bridge |u ref |, the capacitor voltages of each submodule are not sorted.

[0058] Step 4: Calculate the working status of the submodule, according to the absolute value of the output reference voltage given by the cascaded H bridge |u ref |Sum the voltage of the submodule capacitor in the state at the end of this cycle u sum The difference Δu is used to calculate the number of submodules that are newly put into operation or the number of submodules that are newly removed in the next cycle.

[0059] 1) When u sum <|u ref |, assuming i s *u ref >0, the capacitor voltages of the submodules in the cut-off state are sequentially input in ascending order. When the sum of the capacitor voltages of the K submodules before the cut-off state is less than Δu, and the sum of the capacitor voltages of the K+1 submodules before the cut-off state is greater than Δu, the K submodules before the cut-off state enter the integer module, and the K+1 submodule enters the decimal module. As shown in Figure 3(a), the input state u c3 +u c4 +u c6 +u c8 =u sum <|u ref |, remember |u ref |-u sum =Δu, then u in the cut-off state c7 Enter the integer module, u c1 Enter the decimal module; assume i s *u ref <0, the capacitor voltages of the submodules in the cut-off state are sequentially put into operation from large to small. When the sum of the capacitor voltages of the K submodules before the cut-off state is less than Δu, and the sum of the capacitor voltages of the K+1 submodules before the cut-off state is greater than Δu, the K submodules before the cut-off state enter the integer module, and the K+1 submodule enters the decimal module. As shown in Figure 3(a), the input state u c3 +u c4 +u c6 +u c8 =u sum <|u ref |, remember |u ref |-u sum =Δu, then u in the cut-off state c2 Carry out the decimal module.

[0060] 2) When u sum >|u ref |, assuming is *u ref >0, the capacitor voltages of the submodules in the input state are cut off in descending order. When the sum of the capacitor voltages of the K submodules before the input state is less than -Δu, and the sum of the capacitor voltages of the K+1 submodules before the input state is greater than -Δu, the K submodules before the input state enter the integer module, and the K+1 submodule enters the decimal module, as shown in Figure 3(b). c3 +u c4 +u c6 +u c8 =u sum >|u ref |, remember |u ref |-u sum =Δu, then u in the input state c4 Enter the integer module, u c3 Enter the decimal module; assume i s *u ref <0, the capacitor voltages of the submodules in the input state are cut off in order from small to large. When the sum of the capacitor voltages of the K submodules before the input state is less than -Δu, and the sum of the capacitor voltages of the K+1 submodules before the input state is greater than -Δu, the K submodules before the input state enter the integer module, and the K+1 submodule enters the decimal module, as shown in Figure 3(b). c3 +u c4 +u c6 +u c8 =u sum >|u ref |, remember |u ref |-u sum =Δu, then u in the input state c8 、u c6 Enter the integer module, u c3 Enter the Decimal module.

[0061] 3) When u sum =|u ref |, the submodule status in the original input state or cut-off state remains unchanged.

[0062] Step 5: In the submodule switch state switching module of the integer module, the switch states of the first K submodules are switched. When a new integer is added, the first K submodules are switched from the cut-off state to the put-in state; when a new integer is cut off, the first K submodules are switched from the put-in state to the cut-off state, according to the last cut-off state setting.

[0063] Step 6: In the modulation comparison module of the decimal module, PWM modulation is performed on the K+1th submodule. The submodule needs to determine the order of input or removal in the next cycle according to its state at the end of this cycle; when the submodule works in the removed state at the end of this cycle, the (1-D)T at the beginning of the next cycle s Time, first keep the working mode of the submodule unchanged, and then switch to the input state, where D represents the duty cycle; when the submodule works in the input state at the end of this cycle, DT at the beginning of the next cycle s Time, first keep the working mode of the submodule unchanged, and then switch to the cut-off state, set according to the last cut-off state; T s represents the equivalent switching period.

[0064] Based on the last cut-off state setting, the cascaded H-bridge switch state is divided into the on state (positive on mode (1, 0, 0, 1), negative on mode (0, 1, 1, 0)) and the cut-off state ((1, 0, 1, 0) and (0, 1, 0, 1)). When a submodule switches from the on state to the cut-off state, the mode of the submodule in the last cut-off state determines the mode of the cut-off state in the next cycle. If the last cut-off mode of the submodule was (1, 0, 1, 0), the cut-off mode of the submodule in the next cycle is (0, 1, 0, 1); if the last cut-off mode of the submodule was (0, 1, 0, 1), the cut-off mode of the submodule in the next cycle is (1, 0, 1, 0).

[0065] Step 7: The switch generating module transmits the driving signals generated in the on state and the off state to all sub-modules in the cascade H-bridge module.

[0066] While ensuring voltage balance on the DC-side capacitors of the cascaded H-bridge, the switching order of the submodule states in the next cycle is determined based on the submodule's operating status in the current cycle. This minimizes the number of submodule mode switches and the frequency of switching operations, effectively reducing the switching losses of the switch tubes. Furthermore, for two ablation modes with the same effect, the submodules are rotated between these two ablation modes, thereby averaging the losses of the submodule's internal switch tubes.

[0067] The basic principles, main features, and advantages of the present invention are shown and described above. Those skilled in the art should understand that the present invention is not limited to the specific embodiments described above. The specific embodiments and descriptions in the specification are merely intended to further illustrate the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and modifications are intended to fall within the scope of the present invention. The scope of the present invention is defined by the claims and their equivalents.

Claims

1. A classification and sorting system based on cascaded H-bridge DC-side capacitor voltage balance, characterized in that: Including cascade H-bridge module, sampling module, sorting algorithm module, sub-module switch state calculation module, integer module, decimal module, switch generation module; The input end of the cascade H-bridge module is connected to the output end of the switch generation module, and the output end is connected to the sampling module; The sampling module collects the current i flowing into the cascade H bridge s and the capacitor voltages of N submodules are sent to the sorting algorithm module; The sorting algorithm module sorts the capacitor voltages of the input state submodule or the removed state submodule at the end of this cycle, and sends the sorting result to the submodule switch state calculation module; The output end of the submodule switch state calculation module is connected to the integer module; the submodule switch state switching module in the integer module switches the switch state of the submodule; The output end of the integer module is connected to the decimal module; the modulation comparison module in the decimal module performs PWM modulation on each submodule; The output end of the decimal module is connected to the switch generating module.

2. A classification and sorting method based on cascaded H-bridge DC-side capacitor voltage balance, used in the classification and sorting system according to claim 1, characterized in that: The steps include: S1, connect N submodules in series to form a cascade H-bridge; S2, the sampling module collects the current i flowing into the cascade H bridge s and the capacitor voltage u of N submodules c1 、u c2 、u c3 、……、u cN ; S3, in the sorting algorithm module, the capacitor voltage u of N submodules is calculated based on the different states of the submodules at the end of this cycle. c1 、u c2 、u c3 、……、u cN Classify; at the end of this cycle, the sum of the capacitor voltages of the submodules in the active state is recorded as u sum , and the absolute value of the output reference voltage given by the cascaded H-bridge |u ref | Compare, sort the capacitor voltages according to the comparison results; S4, submodule working state calculation, according to Δu, calculate the number of submodules in the next cycle that are newly put into operation or the number of submodules in the new removal state, where Δu = |u ref |-u sum ; S5, in the submodule switch state switching module of the integer module, the switch state of the first K submodules is switched. When a new integer is added, the first K submodules are switched from the cut-off state to the put-in state; When a new integer is removed, the first K submodules are switched from the input state to the removed state, according to the last removed state setting; S6, in the modulation comparison module of the decimal module, PWM modulation is performed on the K+1th submodule. The K+1th submodule needs to determine the order of activation or deactivation in the next cycle based on its state at the end of the current cycle; S7, the switch generation module transmits the switch signal to all sub-modules in the cascade H-bridge module.

3. The classification and sorting method based on cascaded H-bridge DC-side capacitor voltage balance according to claim 2, characterized in that: In step S3, when this cycle ends, u sum <|u ref |, then sort the capacitor voltages of the submodules in the cut-off state at the end of this cycle; When u sum >|u ref |, then sort the capacitor voltages of the submodules that are in the ON state at the end of this cycle; When u sum =|u ref |, then at the end of this cycle, the capacitor voltages of the submodules will not be sorted.

4. The classification and sorting method based on cascaded H-bridge DC-side capacitor voltage balance according to claim 2, characterized in that: In step S4, 41) When u sum <|u ref |, let i s *u ref >0, the capacitor voltages of the submodules in the cut-off state are sequentially input in ascending order. When the sum of the capacitor voltages of the K submodules before the cut-off state is less than Δu, and the sum of the capacitor voltages of the K+1 submodules before the cut-off state is greater than Δu, the K submodules before the cut-off state enter the integer module, and the K+1 submodule enters the decimal module; Assume i s *u ref <0, the capacitor voltages of the submodules in the cut-off state are put into operation in descending order. When the sum of the capacitor voltages of the K submodules before the cut-off state is less than Δu, and the sum of the capacitor voltages of the K+1 submodules before the cut-off state is greater than Δu, the K submodules before the cut-off state enter the integer module, and the K+1 submodule enters the decimal module. 42) When u sum >|u ref |, let i s *u ref >0, the capacitor voltages of the submodules in the input state are cut off in descending order. When the sum of the capacitor voltages of the K submodules before the input state is less than -Δu, and the sum of the capacitor voltages of the K+1 submodules before the input state is greater than -Δu, the K submodules before the input state enter the integer module, and the K+1 submodule enters the decimal module; Assume i s *u ref <0, the capacitor voltages of the submodules in the input state are cut off in ascending order. When the sum of the capacitor voltages of the K submodules before the input state is less than -Δu, and the sum of the capacitor voltages of the K+1 submodules before the input state is greater than -Δu, the K submodules before the input state enter the integer module, and the K+1 submodule enters the decimal module; 43) When u sum =|u ref |, each submodule maintains its original input state or original cut-off state.

5. The classification and sorting method based on cascaded H-bridge DC-side capacitor voltage balance according to claim 2, characterized in that: In step S6, when the current cycle ends, the submodule works in the cut-off state, and the (1-D)T s Time, first keep the working mode of the submodule unchanged, and then switch to the input state, where D represents the duty cycle, T s represents the equivalent switching period; When this cycle ends, the submodule is in the input state, and the DT at the beginning of the next cycle s Time, first keep the working mode of the submodule unchanged, and then switch to the cut-off state, set according to the last cut-off state; Ts represents the equivalent switching period.

6. The classification and sorting method based on cascaded H-bridge DC-side capacitor voltage balance according to claim 5, characterized in that: In step S6, the cascaded H-bridge switch state is divided into an on-state and a cut-off state according to the last cut-off state setting; When a submodule switches from the on state to the off state, the mode of the submodule in the last off state determines the mode of the submodule in the next cycle off state.

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