Signal Strength Indicator Circuit and Transmission Circuit

Abstract

A signal strength indicator circuit is used to detect the output power of an output signal output by a power amplifier, and it includes a voltage gain circuit, a current gain circuit, a multiplier, and a buffer stage. The voltage gain circuit is used to provide a first voltage gain to the output signal to generate a first value of the indicator voltage when the potential of the output signal is not greater than a threshold value, and to provide a second voltage gain to the output signal to generate a second value of the indicator voltage when the potential of the output signal is greater than the threshold value. The first voltage gain is greater than the second voltage gain. The current gain circuit is used to generate an indicator current according to an input signal corresponding to the output signal. The multiplier is used to multiply the indicator voltage by the indicator current to generate an indicator power. The buffer stage is used to convert the indicator power into an indicator signal to indicate the output power of the output signal.

Description

Technical Field

[0001] This invention application relates to a circuit, especially an intensity indicator circuit and related transmission circuit. Background Art

[0002] Transmission circuits are applied to various different wireless communications, and different transmission protocols specify the transmission power of the transmission circuit and the power range it can have. In the prior art, the transmission circuit uses a power detector to detect the intensity of the output signal and generates a transmitted signal intensity indicator based on the detected intensity, which is used to indicate the transmission power of the transmission circuit. However, different transmission devices (such as antennas) or environmental factors (such as temperature) may cause the transmission power to change, thereby making the intensity of the output signal not conform to the specifications of the transmission protocol. Moreover, the transmission power ranges specified by some transmission protocols can reach 35 dB, and the power detectors in the prior art cannot cover such a measurement range, resulting in inaccurate measurements. Therefore, how to adjust the measurement range of the power detector to cover the power range specified by the transmission protocol has become one of the problems that the field is extremely eager to solve. Summary of the Invention

[0003] The present invention discloses a signal intensity indicator circuit for detecting the output power of an output signal output by a power amplifier, which includes a voltage gain circuit, a current gain circuit, a multiplier, and a buffer stage. The voltage gain circuit is used to provide a first voltage gain to the output signal to generate a first value of the indicator voltage when the potential of the output signal is not greater than the threshold, and to provide a second voltage gain to the output signal to generate a second value of the indicator voltage when the potential of the output signal is greater than the threshold. The first voltage gain is greater than the second voltage gain. The current gain circuit is used to generate an indicator current based on an input signal corresponding to the output signal. The multiplier is used to multiply the indicator voltage by the indicator current to generate an indicator power. The buffer stage is used to convert the indicator power into an indicator signal to indicate the output power of the output signal.

[0004] The present invention discloses a transmission circuit, which includes a power amplifier, a processing circuit, and a signal intensity indicator circuit. The power amplifier is used to amplify an input signal according to the power gain value of the power amplifier to generate an output signal. The processing circuit is used to adjust the power gain according to the indicator signal. The signal intensity indicator circuit has multiple power detection ranges, and is used to detect the power of the output signal by using one of the multiple power detection ranges to generate an indicator signal.

[0005] Compared with the prior art, the signal intensity indicator circuit and the transmission circuit of the present application use multiple different power detection ranges corresponding to multiple different gains to detect the intensity of the output signal, so as to improve the dynamic range of the signal intensity indicator circuit.

[0006] The features, operations, and effects of the present invention application will be described in detail below in conjunction with the accompanying drawings and preferred embodiments. Description of the Drawings

[0007] Various aspects of the present application can be best understood when reading the following embodiments and the accompanying drawings. It should be noted that, according to the standard operating habits in the art, the various features in the drawings are not drawn to scale. In fact, in order to clearly describe, the sizes of some features may be deliberately enlarged or reduced.

[0008] Figure 1 Schematic diagram of the transmission circuit in some embodiments of the present invention.

[0009] Figure 2 Schematic diagram of the signal strength indicator circuit in some embodiments of the present invention.

[0010] Symbol Description

[0011] 10: Transmission circuit

[0012] 11: Processing circuit

[0013] 12: Signal strength indicator circuit

[0014] 13: Output load

[0015] 122: Voltage gain circuit

[0016] 123: Current gain circuit

[0017] 124: Multiplier

[0018] ADC: Analog-to-digital converter

[0019] C1: Capacitor

[0020] C10: Capacitor

[0021] C2: Capacitor

[0022] C3: Capacitor

[0023] C4: Capacitor

[0024] C5: Capacitor

[0025] C6: Capacitor

[0026] C7: Capacitor

[0027] C8: Capacitor

[0028] C9: Capacitor

[0029] I-: Negative indicator current

[0030] I+: Positive indicator current

[0031] Iind: Indicator current

[0032] M1: Transconductor

[0033] M2: Transconductor

[0034] OP: Amplifier

[0035] P-: Negative indicator power

[0036] P+: Positive indicator power

[0037] PA: Power amplifier

[0038] Pind: Indicator power

[0039] R1: Resistor

[0040] R2: Resistor

[0041] Sc: Control signal

[0042] Si: Indicator signal

[0043] Sin: Input signal

[0044] Sout: Output signal

[0045] SW1: Switch

[0046] SW2: Switch

[0047] SW3: Switch

[0048] SW4: Switch

[0049] V-: Negative indicator voltage

[0050] V+: Positive indicator voltage

[0051] Vi: Input voltage

[0052] Vin: Negative input voltage

[0053] Vind: Indicator voltage

[0054] Vip: Positive input voltage

[0055] Vout: Buffer stage

[0056] Vvn: Negative output voltage

[0057] Vvp: Positive output voltage Detailed implementation method

[0058] All technical terms used in this document have their ordinary meanings. The definitions of these terms in commonly used dictionaries are only examples of the use of any of the terms discussed herein in the context of this invention application and should not be used to limit the scope and meaning of this invention application. Similarly, this invention application is not limited to the various embodiments shown in this specification.

[0059] Figure 1 In some embodiments of the present invention, it is a schematic diagram of the transmission circuit 10. The transmission circuit 10 includes a processing circuit 11, a power amplifier PA, a signal strength indicator circuit 12, and an output load 13. The transmission circuit 10 is used to transmit an output signal Sout to a receiving end (not shown in the figure). Among them, the processing circuit 11 generates a control signal Sc according to the indicator signal Si to adjust the power gain of the power amplifier PA. The power amplifier PA amplifies the input signal Sin according to the power gain to generate the output signal Sout. The input terminal of the power amplifier PA for receiving the input signal Sin has an input voltage Vi. And due to the output load 13, the output terminal of the power amplifier PA for outputting the output signal Sout has an output voltage Vout. The signal strength indicator circuit 12 is used to detect the power of the output signal Sout and generate the indicator signal Si according to the input signal Sin and the output signal Sout.

[0060] In some embodiments, the transmission circuit 10 is restricted by the specifications of the transmission protocol, such that the power of the output signal Sout output by the transmission circuit 10 must be limited between a preset upper limit and a preset lower limit. Therefore, the signal strength indicator circuit 12 is used to measure the power of the output signal Sout, and it generates the indicator signal Si according to the input signal Sin and the output signal Sout to indicate whether the power of the output signal Sout falls within the specified range. In some embodiments, the indicator signal Si is also referred to as the transmitted signal strength indicator (TSSI). For example, in the 802.11ax standard used by WiFi 6, it is specified that the power of the output signal Sout needs to be between -10 dBm and 25 dBm. Based on the above power range, the signal strength indicator circuit 12 must be able to measure the output signal Sout within this power range. In some prior arts, it is difficult for the power detector to detect all ranges of power between -10 dBm and 25 dBm, resulting in poor measurement accuracy. The signal strength indicator circuit 12 provided in this application can measure different power ranges through different gains to solve the problems encountered in the prior art. The details are described as follows.

[0061] Reference Figure 2 。 Figure 2Schematic diagram of the signal strength indicator circuit 12. The signal strength indicator circuit 12 includes a voltage gain circuit 122, a current gain circuit 123, a multiplier 124, and a buffer stage 125. Figure 1 The power amplifier PA of Figure 1 converts the input voltage Vi (corresponding to the input signal Sin) into the signal Vout according to the power gain. The voltage gain circuit 122 receives the output voltage Vout to generate the indicator voltage Vind. The current gain circuit 123 receives the input voltage Vi to generate the indicator current Iind. The multiplier 124 is used to multiply the indicator voltage Vind and the indicator current Iind to generate the indicator power Pind. The buffer stage 125 converts the indicator power Pind into the indicator signal Si for output.

[0062] In some embodiments, the output voltage Vout is a differential pair, including a positive output voltage Vvp and a negative output voltage Vvn. The voltage gain circuit 122 receives the positive output voltage Vvp and the negative output voltage Vvn, and outputs a positive indicator voltage V+ and a negative indicator voltage V- in the indicator voltage Vind. The input voltage Vi is a differential pair, including a positive input voltage Vip and a negative output voltage Vin. The current gain circuit 123 receives the positive input voltage Vip and the negative input voltage Vin, and outputs a positive indicator current I+ and a negative indicator current I- in the indicator current Iind.

[0063] In some embodiments, the voltage gain circuit 122 includes a set of positive voltage paths formed by a capacitor C1, a capacitor C2, a capacitor C3, a switch SW1, and a switch SW2. As Figure 2 shown, the first ends of the capacitor C1 and the capacitor C2 receive the positive output voltage Vvp in the output voltage Vout. The first ends of the switch SW1 and the switch SW2 are respectively coupled to the second ends of the capacitor C1 and the capacitor C2. The second ends of the switch SW1 and the switch SW2 are coupled to the first end of the capacitor C3. The second end of the capacitor C3 is grounded, and the first end of the capacitor C3 is further coupled to the multiplier 124.

[0064] The voltage gain circuit 122 can switch between a first voltage gain configuration and a second voltage gain configuration by controlling the conduction states of the switch SW1 and the switch SW2, which is used to switch multiple power detection ranges correspondingly. Different voltage gain configurations can generate indicator voltages Vind with different values.

[0065] When the switch SW1 is turned on and the switch SW2 is turned off (the first voltage gain configuration), the positive output voltage Vvp is received at the first end of the capacitor C1, and a positive indicator voltage V+ is generated at the first end of the capacitor C3. Since the second end of the capacitor C3 is grounded, the potential of the positive indicator voltage V+ can be represented by the potential of the positive output voltage Vvp and the voltage division ratio of the capacitors C1 and C3 (V+ = Vvp * C1 / (C1 + C3)).

[0066] When the switch SW1 is turned off and the switch SW2 is turned on (the second voltage gain configuration), the positive output voltage Vvp is received at the first end of the capacitor C2, and a positive indicator voltage V+ is generated at the first end of the capacitor C3. Similarly, the potential of the positive indicator voltage V+ can be represented by the potential of the positive output voltage Vvp and the voltage division ratio of the capacitors C2 and C3 (V+ = Vvp * C2 / (C2 + C3)).

[0067] In some embodiments, the capacitance value of the capacitor C1 is greater than the capacitance value of the capacitor C3, and the capacitance value of the capacitor C3 is greater than the capacitance value of the capacitor C2. Based on the relationship of the above capacitance values, when the switch SW1 is turned on and the switch SW2 is turned off, the voltage gain circuit 122 forms the first voltage gain configuration, and the generated positive indicator voltage V+ is larger. When the switch SW1 is turned off and the switch SW2 is turned on, the voltage gain circuit 122 forms the second voltage gain configuration, and the generated positive indicator voltage V+ is smaller. In other words, the voltage gain circuit 122 can determine the voltage gain from the positive output voltage Vvp to the positive indicator voltage V+ through the conduction states of the switches SW1 and SW2. That is, when the voltage gain circuit 122 forms the first voltage gain configuration (the switch SW1 is turned on and the switch SW2 is turned off), the voltage gain circuit 122 provides a larger voltage gain, and when the voltage gain circuit 122 forms the first voltage gain configuration (when the switch SW1 is turned off and the switch SW2 is turned on), the voltage gain circuit 122 provides a smaller voltage gain.

[0068] When the potential of the positive output voltage Vvp is greater than a threshold value, in order to prevent the potential of the positive indicator voltage V+ from exceeding the upper limit that the multiplier 124 can handle, the voltage gain circuit 122 can make the switch SW1 non-conductive and the switch SW2 conductive (i.e., the second voltage gain configuration) to obtain a smaller voltage gain and amplify the positive output voltage Vvp to the positive indicator voltage V+. In contrast, when the potential of the positive output voltage Vvp is less than the threshold value, in order to prevent the potential of the positive indicator voltage V+ from being lower than the lower limit that the multiplier 124 can handle, the voltage gain circuit 122 can make the switch SW1 conductive and the switch SW2 non-conductive (i.e., the first voltage gain configuration) to obtain a larger voltage gain and amplify the positive output voltage Vvp to the positive indicator voltage V+. In summary, the voltage gain circuit 122 can generate the positive output voltage Vvp within different potential ranges as the positive indicator voltage V+ with different voltage gains, facilitating subsequent power detection operations.

[0069] In some embodiments, at least one of the switches SW1 and SW2 is conductive.

[0070] In some embodiments, the voltage gain circuit 122 further includes a set of negative voltage paths formed by a capacitor C4, a capacitor C5, a capacitor C6, a switch SW3, and a switch SW4. The capacitor C4, the capacitor C5, the capacitor C6, the switch SW3, and the switch SW4 are used to generate a negative indicator voltage V- based on the negative output voltage Vvn. Among them, the capacitor C4, the capacitor C5, the capacitor C6, the switch SW3, and the switch SW4 respectively correspond to the capacitor C1, the capacitor C2, the capacitor C3, the switch SW1, and the switch SW2, and have the same connection relationship and operation (for example: the negative voltage path can have the same first voltage gain configuration and second voltage gain configuration as the positive voltage path, and the two paths can operate in the corresponding gain configurations). Therefore, the details of the capacitor C4, the capacitor C5, the capacitor C6, the switch SW3, and the switch SW4 are not described herein again.

[0071] The current gain circuit 123 includes a transconductor M1, a transconductor M2, a capacitor C7, and a capacitor C8. The receiving ends of the transconductor M1 and the transconductor M2 are respectively used to receive a positive input voltage Vip and a negative input voltage Vin, and generate a negative indicator current I- and a positive indicator current I+ at the output ends of the transconductor M1 and the transconductor M2 respectively. The transconductor M1 and the transconductor M2 have current sources (not shown). In some embodiments, the transconductor M1 and the transconductor M2 share the same current source. The first end of the capacitor C7 is coupled to the receiving end of the transconductor M1, and the second end of the capacitor C7 is coupled to the output end of the transconductor M2. Correspondingly, the first end of the capacitor C8 is coupled to the receiving end of the transconductor M2, and the second end of the capacitor C8 is coupled to the output end of the transconductor M1. In some embodiments, the capacitors C7 and C8 are used to adjust the phases of the positive indicator current I+ and the negative indicator current I- to improve the detection accuracy.

[0072] The transconductor M1 and the transconductor M2 respectively have a plurality of transistors arranged in parallel (for the sake of simplicity of the drawing, Figure 2 only one transistor is shown in the figure and is marked with an arrow as variable). When different numbers of transistors are turned on, the transconductor M1 and the transconductor M2 can provide different current gains to the positive input voltage Vip and the negative input voltage Vin. In other words, the transconductor M1 and the transconductor M2 form different current gain configurations by turning on different transistors, each corresponding to a power detection range. For example, when more or larger transistors are turned on, because the equivalent channel is wider, the transconductor M1 and the transconductor M2 can generate a larger current, so the current gain is larger. In contrast, when fewer or smaller transistors are turned on, because the equivalent channel is narrower, the transconductor M1 and the transconductor M2 can only generate a smaller current, so the current gain is smaller.

[0073] The multiplier 124 is used to receive the positive indicator voltage V+ and the negative indicator voltage V- generated by the voltage gain circuit 122 and the positive indicator current I+ and the negative indicator current I- generated by the current gain circuit 123, and multiply the positive indicator voltage V+ by the positive indicator current I+, and multiply the negative indicator voltage V- by the negative indicator current I- to generate an indicator power Pind. The indicator power Pind includes an indicator power P+ obtained by multiplying the positive indicator voltage V+ by the positive indicator current I+ and an indicator power P- obtained by multiplying the negative indicator voltage V- by the negative indicator current I-.

[0074] The buffer stage 125 includes an amplifier OP, an analog-to-digital converter ADC, a capacitor C9, a capacitor C10, a resistor R1, and a resistor R2. The amplifier OP is coupled to the multiplier 124 to amplify the indicator power Pind. The analog-to-digital converter ADC is coupled to the amplifier OP to convert the amplified indicator power Pind into an indicator signal Si. The capacitor C9, the capacitor C10, the resistor R1, and the resistor R2 are connected across the input and output terminals of the amplifier OP.

[0075] In some embodiments, the buffer stage 125 has a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. The capacitor C9 and the resistor R1 are connected across the positive input terminal and the positive output terminal of the amplifier OP, and the capacitor C10 and the resistor R2 are connected across the negative input terminal and the negative output terminal of the amplifier OP. The positive input terminal and the negative input terminal are respectively used to receive the indicator power P+ and the indicator power P-.

[0076] In some embodiments, the analog-to-digital converter ADC has a low impedance, and the resistors R1, R2, capacitor 9, and capacitor 10 connected before the analog-to-digital converter ADC are implemented as a low-pass filter, which is used to eliminate the noise on the indicator power Pind. In some embodiments, the resistors R1 and R2 are variable resistors. Adjusting the resistance values of the resistors R1 and R2 can adjust the gain of the buffer stage 125 and the passband of the above low-pass filter.

[0077] The features of certain embodiments of the present invention application are briefly described above, so that those of ordinary skill in the art to which the present application pertains can more comprehensively understand the various forms of the present invention. Those of ordinary skill in the art to which the present application pertains should understand that they can easily use the content of the present application as a basis to design or change other processes and structures to achieve the same purposes and / or achieve the same advantages as these embodiments herein. Those of ordinary skill in the art to which the present application pertains should understand that these equivalent embodiments still fall within the inventive concept and protection scope of the present invention, and they can be variously changed, substituted, and modified without departing from the spirit and scope of the content of the present invention application.

Claims

1. A signal strength indicator circuit for detecting the output power of an output signal output by a power amplifier, characterized in that The signal strength indicator circuit includes: A voltage gain circuit for providing a first voltage gain to the output signal to generate a first value of the indicator voltage when the potential of the output signal is not greater than a threshold, and providing a second voltage gain to the output signal to generate a second value of the indicator voltage when the potential of the output signal is greater than the threshold, wherein the first voltage gain is greater than the second voltage gain; A current gain circuit for generating an indicator current based on an input signal corresponding to the output signal; A multiplier for multiplying the indicator voltage by the indicator current to generate an indicator power; And A buffer stage for converting the indicator power into an indicator signal to indicate the output power of the output signal; The voltage gain circuit includes: A first capacitor; A second capacitor, wherein a first end of the first capacitor and a first end of the second capacitor are used to receive the output signal; A first switch, wherein a first end of the first switch is coupled to a second end of the first capacitor, and a second end of the first switch is coupled to the multiplier; A second switch, wherein a first end of the second switch is coupled to a second end of the second capacitor, and a second end of the second switch is coupled to the multiplier, wherein at least one of the first switch and the second switch is turned on during operation of the voltage gain circuit; And A third capacitor coupled between the second end of the first switch and the ground terminal.

2. The signal strength indicator circuit according to claim 1, wherein When the first switch is turned on and the second switch is turned off, the voltage gain circuit utilizes the first voltage gain, and when the second switch is turned on and the first switch is turned off, the voltage gain circuit utilizes the second voltage gain.

3. The signal strength indicator circuit according to claim 1, wherein The current gain circuit provides a first current gain to the input signal to generate a first value of the indicator current or provides a second current gain to the input signal to generate a second value of the indicator current.

4. The signal strength indicator circuit according to claim 3, wherein The current gain circuit includes: A transconductor for generating the indicator current based on the input signal.

5. The signal strength indicator circuit according to claim 4, wherein The transconductor includes a first transistor and a second transistor arranged in parallel, wherein when the first transistor is turned on, the current gain circuit provides the first current gain to the input signal, and when the first transistor is turned off, the current gain circuit provides the second current gain to the input signal.

6. A transmission circuit, characterized in that, The transmission circuit includes: A power amplifier for amplifying an input signal based on the power gain of the power amplifier to generate an output signal; A processing circuit for adjusting the power gain based on the indicator signal; and A signal strength indicator circuit having a plurality of power detection ranges, the signal strength indicator circuit for detecting the power of the output signal using one of the plurality of power detection ranges to generate the indicator signal; The signal strength indicator circuit includes: A voltage gain circuit that can switch between a first voltage gain configuration and a second voltage gain configuration to correspondingly switch between at least two of the multiple power detection ranges, and the voltage gain circuit outputs the output signal as a first value or a second value of an indicator voltage by using the voltage gain corresponding to the first voltage gain configuration or the second voltage gain configuration; A current gain circuit that can switch between a first current gain configuration and a second current gain configuration to correspondingly switch between at least two of the multiple power detection ranges, and the current gain circuit outputs the input signal as a first value or a second value of an indicator current by using the current gain corresponding to the first current gain configuration or the second current gain configuration; A multiplier for multiplying the indicator voltage and the indicator current to generate an indicator power; and A buffer stage for converting the indicator power into the indicator signal.

7. The transmission circuit according to claim 6, wherein When the power of the output signal exceeds a default upper limit value, the signal strength indicator circuit generates the indicator signal to cause the processing circuit to reduce the power gain.

8. The transmission circuit according to claim 6, wherein When the power of the output signal is lower than a preset lower limit value, the signal strength indicator circuit generates the indicator signal to cause the processing circuit to increase the power gain.

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