Circuit substrate

Abstract

The present application has an object to suppress a decrease in impedance in a high frequency region in a circuit substrate having a structure in which a chip-type coil component is surface-mounted on a substrate. A circuit substrate (1) of the present application includes a substrate (10) and a chip-type coil component (20) surface-mounted on the substrate (10). The substrate (10) includes pad patterns (P1, P2) connected to signal lines (S1, S2), respectively, and dummy pad patterns (DP1, DP2) in a floating state. The coil component (20) includes signal terminals (E1, E2) connected to the pad patterns (P1, P2), respectively, and dummy terminals (DE1, DE2) connected to the dummy pad patterns (DP1, DP2), respectively. Thus, since the dummy pad patterns (DP1, DP2) are in a floating state, a decrease in capacitance between the pad patterns (P1, P2) and ground is suppressed, and a decrease in impedance in a high frequency region is suppressed. Furthermore, mounting strength of the coil component (20) with respect to the substrate (10) can also be ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to a circuit substrate, and particularly to a circuit substrate having a structure in which a chip-type coil component is surface-mounted on a substrate. BACKGROUND

[0002] In Patent Literature 1, a structure is disclosed in which one pair of terminal electrodes of a coil component mounted on a substrate is connected to a signal line, and the other pair of terminal electrodes is connected to a ground pattern. According to the above structure, the coil component functions as an LC composite component, and insertion loss is reduced.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Laid-Open No. 2008-140903 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] However, in the mounting structure described in Patent Literature 1, since the capacitance between the signal line and the ground increases, there is a problem that the impedance in a high frequency region decreases.

[0008] Therefore, an object of the present application is to suppress a decrease in impedance in a high frequency region in a circuit substrate having a structure in which a chip-type coil component is surface-mounted on a substrate.

[0009] MEANS FOR SOLVING THE PROBLEMS

[0010] The circuit substrate of the present application is characterized by comprising a substrate and a chip-type coil component surface-mounted on the substrate, the substrate including: first and second signal lines; first and second pad patterns connected to the first and second signal lines, respectively; and first and second dummy pad patterns in a floating state, the coil component including: a drum-type core including a first flange portion, a second flange portion, and a winding core portion between the first and second flange portions; a first signal terminal and a first dummy terminal provided to the first flange portion; a second signal terminal and a second dummy terminal provided to the second flange portion; and a wire wound around the winding core portion, one end of which is connected to the first signal terminal and the other end of which is connected to the second signal terminal, the coil component being mounted on the substrate in such a manner that the first and second signal terminals are connected to the first and second pad patterns, respectively, and the first and second dummy terminals are connected to the first and second dummy pad patterns, respectively.

[0011] According to the present application, since the dummy land pattern is in a floating state, the capacitance between the land pattern and the ground is reduced compared to the case where the land pattern is short-circuited with the dummy land pattern. Thus, the reduction in impedance in the high frequency region can be suppressed. Also, since the dummy land pattern is connected to the dummy terminal, the mounting strength of the coil component with respect to the substrate can also be ensured.

[0012] In the present application, it is also possible that the first and second dummy land patterns are each an independent pattern not connected to other patterns. Thus, the generation of noise due to the dummy land pattern can be prevented.

[0013] In the present application, it is also possible that the effective area of the first and second land patterns is smaller than the effective area of the first and second dummy land patterns. Thus, the capacitance between the land pattern and the ground can be further reduced. In this case, it is also possible that the outer dimensions of the first and second land patterns are the same as the outer dimensions of the first and second dummy land patterns, and the effective area is reduced by a cutout provided in the first and second land patterns. Thus, the connection strength of the land pattern to the signal terminal by solder can be sufficiently ensured.

[0014] Effects of Invention

[0015] As described above, according to the present application, in a circuit substrate having a structure in which a chip-type coil component is surface-mounted on a substrate, the reduction in impedance in the high frequency region can be suppressed. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a general exploded perspective view showing the appearance of a circuit substrate 1 according to a preferred embodiment of the present application.

[0017] Figure 2 is a general perspective view showing the appearance of a coil component 20.

[0018] Figure 3 is a general cross-sectional view of the circuit substrate 1.

[0019] Figure 4 is an equivalent circuit of the coil component 20 in a state of being mounted on the substrate 10.

[0020] Figure 5 is a graph for explaining the effects of the embodiment, the solid line showing the characteristics of the coil component 20 in a state of being mounted on the substrate 10, and the broken line showing the characteristics in the case where a land pattern Pl is integrated with a dummy land pattern DP1 and a land pattern P2 is integrated with a dummy land pattern DP2.

[0021] Figure 6This is a general top view showing the pattern shape on the substrate 10 of the first modified example.

[0022] Figure 7 This is a general top view showing the pattern shape on the substrate 10 of the second modified example.

[0023] Explanation of reference numerals in the attached figures

[0024] 1 Circuit board

[0025] 10 substrate

[0026] 20 Coil Components

[0027] 30 Drum-shaped core

[0028] 31, 32 Flange portion

[0029] 33 Core section

[0030] 40 plate core

[0031] 50 Solder

[0032] Component A mounting area

[0033] DE1, DE2 are dummy terminals

[0034] DP1 and DP2 are dummy pad patterns.

[0035] E1 and E2 signal terminals

[0036] G Grounding pattern

[0037] P1 and P2 pad patterns

[0038] S1 and S2 signal lines

[0039] W winding Detailed Implementation

[0040] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0041] Figure 1 This is a generally exploded perspective view showing the appearance of the circuit board 1 according to a preferred embodiment of the present invention.

[0042] like Figure 1As shown, the circuit substrate 1 of the present embodiment is provided with the substrate 10, and the chip-type coil component 20 surface-mounted to the component mounting region A provided on the substrate 10. On the surface of the substrate 10, there are provided the signal lines S1, S2, the pad patterns P1, P2 connected to the signal lines S1, S2, respectively, and the dummy pad patterns DP1, DP2. The pad patterns P1, P2 and the dummy pad patterns DP1, DP2 are all located in the component mounting region A. The dummy pad patterns DP1, DP2 are all independent patterns not connected to other patterns, and are in an electrically floating state. In Figure 1 In the example shown, the pad pattern P1 and the dummy pad pattern DP2 are arranged at positions opposite to each other, and the pad pattern P2 and the dummy pad pattern DP1 are arranged at positions opposite to each other. In other words, the pad patterns P1, P2 are arranged at diagonal positions to each other, and the dummy pad patterns DP1, DP2 are arranged at diagonal positions to each other.

[0043] Figure 2 is a general perspective view showing the appearance of the coil component 20.

[0044] As shown in Figure 2 , the coil component 20 has a drum-type core 30 having flange portions 31, 32 and a winding core portion 33, a plate-shaped core 40 fixed to the flange portions 31, 32, a signal terminal E1 and a dummy terminal DE1 provided to the flange portion 31, a signal terminal E2 and a dummy terminal DE2 provided to the flange portion 32, and a wire W wound around the winding core portion 33. The wire W is a covered conductor having a good conductor such as copper as a core material.

[0045] The drum-type core 30 is a drum-type block composed of a high-permeability material such as ferrite, and has a structure in which the flange portions 31, 32 and the winding core portion 33 provided therebetween are integrated. The plate-shaped core 40 is also a plate-shaped block composed of a high-permeability material such as ferrite. The drum-type core 30 and the plate-shaped core 40 are fixed to each other via an adhesive or the like. Furthermore, one end of the wire W is connected to the signal terminal E1, and the other end of the wire W is connected to the signal terminal E2. The dummy terminals DE1, DE2 are not connected to any wire. The signal terminals E1, E2 and the dummy terminals DE1, DE2 can be terminals composed of a silver paste or the like attached to the drum-type core 30, or can be terminals composed of terminal metal pieces attached to the drum-type core 30.

[0046] Furthermore, the coil component 20 is mounted to the substrate 10 in such a manner that the signal terminals E1, E2 are connected to the pad patterns P1, P2, respectively, and the dummy terminals DE1, DE2 are connected to the dummy pad patterns DP1, DP2, respectively. The connection of the signal terminals E1, E2 and the dummy terminals DE1, DE2 to the pad patterns P1, P2 and the dummy pad patterns DP1, DP2 is shown in Figure 3is shown, via the solder 50.

[0047] As Figure 3 shown, inside the substrate 10, there is a ground pattern G at positions overlapping the pad patterns P1, P2 and the dummy pad patterns DP1, DP2. Therefore, a stray capacitance is generated between the pad patterns P1, P2 and the ground pattern G, and between the dummy pad patterns DP1, DP2 and the ground pattern G.

[0048] Figure 4 is an equivalent circuit of the coil component 20 in a state where it is mounted on the substrate 10.

[0049] As Figure 4 shown, the coil component 20 can be expressed by an equivalent circuit in which an inductive component Ls, a capacitive component Cp and a resistive component Rp are connected in parallel. In addition to this, in a state where the coil component 20 is mounted on the substrate 10, a stray capacitance component Cpad generated between the pad patterns P1, P2 and the ground pattern G is added. However, since the pad pattern P1 is separated from the dummy pad pattern DP1 and the pad pattern P2 is separated from the dummy pad pattern DP2, the stray capacitance generated by the dummy pad patterns DP1, DP2 is not included in the stray capacitance component Cpad. Due to this, the stray capacitance component Cpad is reduced, and therefore, the reduction of the impedance in the high frequency region is suppressed. On the other hand, the dummy terminals DE1, DE2 are connected to the dummy pad patterns DP1, DP2 via the solder 50, and therefore, the mounting strength of the coil component 20 is also sufficiently ensured.

[0050] Figure 5 is a graph for explaining the effect of the present embodiment, the solid line indicates the characteristics of the coil component 20 in a state where it is mounted on the substrate 10, and the broken line indicates the characteristics in a case where the pad pattern P1 is integrated with the dummy pad pattern DP1 and the pad pattern P2 is integrated with the dummy pad pattern DP2. As Figure 5 shown, it is known that in the low frequency region, there is almost no difference in the impedance between the circuit substrate 1 of the present embodiment and the circuit substrate of the comparative example, but in the high frequency region, the circuit substrate 1 of the present embodiment can obtain a higher impedance.

[0051] Figure 6 is a general plan view showing the pattern shapes on the substrate 10 of the first modified example.

[0052] In Figure 6In the first modification shown, the pad pattern Pl and the pad pattern P2 are arranged at positions opposite to each other, and the dummy pad pattern DPI and the dummy pad pattern DP2 are arranged at positions opposite to each other, unlike the pattern shape in the above-described embodiment. In this case, for the coil component 20 mounted on the substrate 10, the connection position of the wire W also needs to be changed. Specifically, the positions of the signal terminal El and the dummy terminal DEl are arranged to be opposite to each other, and the positions of the signal terminal E2 and the dummy terminal DE2 are arranged to be opposite to each other, unlike the above-described embodiment. Figure 2 The opposite is also possible. As exemplified in the first modification, the layout of the pad patterns Pl, P2 and the dummy pad patterns DPI, DP2 is not particularly limited.

[0053] Figure 7 is a schematic plan view showing the pattern shape on the substrate 10 of the second modification.

[0054] In Figure 7 In the second modification shown, a plurality of slit-like cutouts are provided in the pad patterns Pl, P2. The outer dimensions of the pad patterns Pl, P2 are the same as those of the dummy pad patterns DPI, DP2, but since the slit-like cutouts are provided in the pad patterns Pl, P2, the effective area is reduced compared to the dummy pad patterns DPI, DP2. Here, the effective area refers to the area of the portion where the conductor pattern exists. In this way, by reducing the effective area of the pad patterns Pl, P2, the stray capacitance component Cpad generated between the pad patterns Pl, P2 and the ground pattern G is further reduced, and thus the impedance in the high frequency region is further improved. Moreover, since the outer dimensions are maintained, the connection strength by the solder 50 can be ensured.

[0055] The above describes the preferred embodiment of the present application, but the present application is not limited to the above-described embodiment, and various modifications can be made within the scope of the present application without departing from the spirit of the present application, and these modifications are of course included in the scope of the present application.

Claims

1. A circuit substrate characterized by comprising: a substrate; and a chip-type coil component surface-mounted to the substrate, the substrate including: first and second signal lines; first and second pad patterns connected to the first and second signal lines, respectively; first and second dummy pad patterns in a floating state; and a ground pattern overlapping the first and second pad patterns and the first and second dummy pad patterns, the coil component including: a drum-type core including a first flange portion, a second flange portion, and a winding core portion between the first flange portion and the second flange portion; a first signal terminal and a first dummy terminal provided to the first flange portion; a second signal terminal and a second dummy terminal provided to the second flange portion; and a winding wound around the winding core portion, one end of which is connected to the first signal terminal and the other end of which is connected to the second signal terminal, the coil component mounted to the substrate in a manner that the first and second signal terminals are connected to the first and second pad patterns, respectively, and the first and second dummy terminals are connected to the first and second dummy pad patterns, respectively.

2. The circuit substrate according to claim 1, characterized in that: the first and second dummy pad patterns are each an independent pattern not connected to other patterns.

3. The circuit substrate according to claim 1 or 2, characterized in that: effective areas of the first and second pad patterns are smaller than effective areas of the first and second dummy pad patterns.

4. The circuit substrate according to claim 3, characterized in that: the first and second pad patterns have the same outer dimensions as the first and second dummy pad patterns, and the effective areas are reduced by notches provided to the first and second pad patterns.

5. The circuit substrate according to claim 1, characterized in that: the first pad pattern and the second dummy pad pattern face each other in an axial direction, and the second pad pattern and the first dummy pad pattern face each other in the axial direction.

6. The circuit substrate according to claim 1, characterized in that: the first and second pad patterns each have a notch.

7. The circuit substrate according to claim 6, characterized in that: the first and second dummy pad patterns are each a solid pattern having no notch.

8. The circuit substrate according to claim 1, characterized in that: the first and second pad patterns each have a plurality of notches extending in the axial direction. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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