Integrated circuit and integrated circuit power switch synchronization noise test method

Abstract

The application relates to integrated circuit technology and relates to an integrated circuit and a power switch synchronization noise test method. The application is characterized in that a power switch synchronization noise test circuit is arranged in an integrated circuit chip, the power switch synchronization noise test circuit comprises a clock management and distribution circuit, a measured power supply load circuit, a sampling circuit, and a digitizing circuit; the power switch of the measured power supply load circuit is controlled by a high-frequency clock module; the signal input end of the sampling circuit is connected with the measured power supply load circuit, and the control end of the sampling circuit is connected with a low-frequency clock module; the input end of the digitizing circuit is connected with the signal output end of the sampling circuit, and the output end of the digitizing circuit is the output end of the power switch synchronization noise test circuit. The application can effectively reduce the interference of factors such as chip packaging, a circuit board and peripheral devices on the measured signal.

Description

Technical Field

[0001] This invention relates to integrated circuit technology, and particularly to integrated circuit testing technology. Background Technology

[0002] Example of time-domain voltage waveform of power switching noise: Figure 1 As shown. In large-scale digital circuits, when the system clock edge arrives, a portion of the digital logic triggers a switching action, generating a large transient current. Due to the unavoidable inductance in the power supply network, the network cannot provide sufficient current under transient conditions, causing the supply voltage to drop. Depending on the specific parameters of the power supply network, ringing may also occur.

[0003] As chip operating frequencies continue to increase, the importance of power integrity design is growing. However, the quality of power integrity design is related to the circuit board, chip package, and bare die, making it difficult to detect power quality at the bare die end using probe points on the circuit board. Of course, power quality can be tested from probe points pre-installed on the chip package. However, this method requires specialized chip test probe stations, microwave probes, and various types of benchtop test equipment, resulting in a high hardware investment in the test platform. Furthermore, it necessitates removing some or all of the chip's heatsink cover to conduct the test, which differs somewhat from the actual operating environment of the chip. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for accurately testing the synchronization noise of power switches in actual integrated circuits, and an integrated circuit with on-chip power switch synchronization noise testing function.

[0005] The technical solution adopted by the present invention to solve the aforementioned technical problem is an integrated circuit, characterized in that a power switch synchronization noise test circuit is provided inside the integrated circuit chip, the power switch synchronization noise test circuit comprising:

[0006] The clock management and distribution circuit has a high-frequency clock module and a low-frequency clock module. The high-frequency clock module is connected to the load circuit of the power supply under test. The clock frequency generated by the high-frequency clock module is N times the clock frequency generated by the low-frequency clock module, where N is an integer greater than 3. The low-frequency clock module is connected to the control terminal of the sampling circuit and has a phase control unit.

[0007] The power supply load circuit under test has its power switch controlled by a high-frequency clock module.

[0008] The sampling circuit has its signal input terminal connected to the load circuit of the power supply under test, and its control terminal connected to the low-frequency clock module.

[0009] The digital circuit has its input terminal connected to the signal output terminal of the sampling circuit, and its output terminal is the output terminal of the power switch synchronous noise test circuit.

[0010] Furthermore, the phase control unit is used to generate a low-frequency clock signal with a predetermined phase offset value.

[0011] The sampling circuit includes a switching switch, a resistor, and a capacitor. The resistor is positioned between the signal input terminal and the first selectable terminal of the switching switch. The second selectable terminal of the switching switch is connected to the signal output terminal. The fixed terminal of the switching switch is grounded through the capacitor.

[0012] The capacitor is an adjustable capacitor.

[0013] This invention also provides a method for testing synchronization noise of integrated circuit power switches, characterized by comprising the following steps:

[0014] 1) Divide the source clock signal to obtain a low-frequency clock signal and a high-frequency clock signal, wherein the frequency of the high-frequency clock signal is N times that of the low-frequency clock signal, and N is an integer greater than 3;

[0015] 2) The power switch of the power supply load circuit under test is controlled by a high-frequency clock signal;

[0016] 3) Adjust the phase of the low-frequency clock signal and use the low-frequency clock signal with various phase offset values ​​as the control signal of the sampling circuit to sample the output signal of the power supply load circuit under test.

[0017] 4) The sampling results of low-frequency clock signals with various phase offset values ​​are superimposed as the test output.

[0018] Step 4) involves superimposing the sampling results of low-frequency clock signals with various phase offset values, converting them into digital signals, and using them as the output of the test.

[0019] The sampling time window width of the sampling circuit is adjustable.

[0020] In step 3), the phase of the low-frequency clock signal is adjusted using a preset value x as the step size. The phase offset of the control signal with the sequence number n is n*x, where n is a natural number, relative to the initial control signal with a phase shift value of 0.

[0021] This invention features a simple working principle, low circuit complexity, low design cost, and low power consumption of the built-in test circuit. It has low requirements for the conversion rate design of the analog-to-digital converter, making it easy to implement. Since the analog signal acquisition port is located inside the chip under test (DUT), closer to the test point, it effectively reduces interference from chip packaging, circuit boards, and peripheral components. This invention can be applied to the mid-stage testing, wafer testing, and user product application development testing phases of chips, with low hardware testing requirements and strong adaptability to testing scenarios. Attached Figure Description

[0022] Figure 1 This is a time-domain voltage waveform diagram of power switch noise.

[0023] Figure 2 This is a schematic diagram of the power switch synchronization noise test circuit of the present invention.

[0024] Figure 3 This is a circuit diagram of the sampling circuit of the present invention.

[0025] Figure 4 This is a comparison diagram of the noise waveform and sampling time of the present invention.

[0026] Figure 5 This is a schematic diagram of the present invention. Detailed Implementation

[0027] This invention provides a method for testing synchronization noise of integrated circuit power switches, comprising the following steps:

[0028] 1) Divide the source clock signal to obtain a low-frequency clock signal and a high-frequency clock signal. The frequency of the high-frequency clock signal is N times that of the low-frequency clock signal, where N is an integer greater than 3, and the phase difference between any two adjacent low-frequency clock signals is the same non-zero preset value.

[0029] 2) The power switch of the power supply load circuit under test is controlled by a high-frequency clock signal;

[0030] 3) Use a low-frequency clock signal as the control signal of the sampling circuit to sample the output signal of the power supply load circuit under test, and use the sampling result as the test output.

[0031] Step 3) is as follows: using a low-frequency clock signal as the control signal of the sampling circuit, sampling the output signal of the power supply load circuit under test, and converting the sampling result into a digital signal as the output of the test.

[0032] The sampling time window width of the sampling circuit is adjustable.

[0033] Example

[0034] To meet the noise testing requirements of switching power supplies in certain application scenarios, this invention proposes a solution with an integrated test circuit for chip power switch synchronization noise. This solution integrates the corresponding test circuit functional module within the chip to test power switch synchronization noise and DC voltage drop. It is suitable for power switch synchronization noise testing of digital devices such as FPGAs (FPGA programmable gate arrays).

[0035] See Figure 2 and Figure 3 The present invention includes a power switch synchronization noise test circuit inside an integrated circuit chip, the power switch synchronization noise test circuit comprising:

[0036] The clock management and distribution circuit has a high-frequency clock module and a low-frequency clock module. The high-frequency clock module is connected to the load circuit of the power supply under test. The clock frequency generated by the high-frequency clock module is N times the clock frequency generated by the low-frequency clock module, where N is an integer greater than 3. The low-frequency clock module is connected to the control terminal of the sampling circuit and has a phase control unit.

[0037] The power supply load circuit under test has its power switch controlled by a high-frequency clock module.

[0038] The sampling circuit has its signal input terminal connected to the load circuit of the power supply under test, and its control terminal connected to the low-frequency clock module.

[0039] The digital circuit has its input terminal connected to the signal output terminal of the sampling circuit, and its output terminal is the output terminal of the power switch synchronous noise test circuit.

[0040] The phase control unit is used to generate a low-frequency clock signal with a predetermined phase offset value. For example, the low-frequency clock signal obtained by frequency division is used as the initial control signal, and the phase control unit shifts the phase of the signal to obtain n control signals. The phase offset values ​​of the n control signals are x, 2x, 3x...n*x, respectively.

[0041] The sampling circuit includes a switch, a resistor, and a capacitor. The resistor is positioned between the signal input terminal and the first selectable terminal of the switch. The second selectable terminal of the switch is connected to the signal output terminal. The fixed terminal of the switch is grounded through the capacitor. The capacitor is an adjustable capacitor.

[0042] See Figure 3The sampling circuit controls the charging and discharging of the sampling capacitor via a switch. The switch connects the analog input signal from the power supply load circuit under test to the sampling capacitor, charging it. This switch is controlled by a trigger clock signal (Clk_trig) generated by the clock management and distribution circuit. The Clk_trig signal is an integer multiple of the system clock (Clk_sys) of the power supply load circuit under test. During the charging phase of the sampling capacitor, other circuit units operate in a low-power state, minimizing interference from the built-in test circuit to the circuit under test and improving test accuracy.

[0043] The analog-to-digital converter of the present invention includes a sampling circuit and a digitization circuit. After the sampling capacitor is fully charged and a waiting period is completed, a switch connects the sampling capacitor to the digitization circuit, and the analog-to-digital converter converts the voltage of the analog signal into parallel data.

[0044] The resistor and sampling capacitor constitute an RC filter circuit. The parameter values ​​of the resistor and capacitor can be calculated and selected appropriately based on the frequency corresponding to the switching noise estimated during the design of the circuit under test. Depending on the specific design application, the resistance value in the above diagram can be set to a fixed value, or a parallel resistor and switching circuit can be used to achieve programmable adjustment of the resistance value.

[0045] Clock management and distribution circuitry plays a crucial role in this invention and is its core component. This invention primarily utilizes the clock synchronization relationship between switch synchronization noise and the analog-to-digital converter (ADC). The analog signal acquisition time window of the ADC is roughly aligned with the time of the switch synchronization noise under test. Then, combined with continuous clock phase adjustment, multiple samples are taken under different relative phase conditions to obtain the built-in test voltage waveform of the switch synchronization noise.

[0046] like Figure 4 As shown, the clock management and distribution circuit generates two output clock signals, Clk_sys and Clk_trig, where the frequency of Clk_sys is an integer multiple of Clk_trig. Clk_sys generates power switching synchronization noise by triggering the switching action of the load circuit under test; Clk_trig controls the switching time of the sampling capacitor circuit, thereby controlling the sampling time window of the switching capacitor. When the Clk_sys and Clk_trig clock signals maintain a specific phase relationship, each sampling time window of the sampling capacitor is aligned with the timing of the switching synchronization noise.

[0047] As chip operating frequencies continue to increase, the frequency range affected by power switching synchronization noise also widens, reaching over 5GHz. To measure 5GHz switching synchronization noise, it's necessary to increase the bandwidth of the analog-to-digital converter's switched capacitor circuit and reduce the phase adjustment step size of the clock management and distribution circuits, for example, controlling the phase adjustment step size to within 25 picoseconds. Various methods exist for implementing phase adjustment, which can be flexibly selected based on the specific application. For example, clock management modules with dynamic phase shift control, commonly used in FPGA chip products, can achieve the above specifications. Alternatively, numerically controlled delay circuits can also be considered to implement this function.

[0048] like Figure 5 As shown, by continuously adjusting the relative phase between the Clk_sys and Clk_trig clock signals, and performing one or more analog-to-digital conversions under each relative phase condition, the sampling circuit performs low-pass filtering on the measured power supply signal within the time range corresponding to each sampling time window to obtain an analog input voltage. Then, the analog-to-digital converter performs analog-to-digital conversion on this input voltage. Finally, by fitting the sampling data obtained under continuous phase conditions, the result can be obtained. Figure 5 The waveform of the sampled data output by the analog-to-digital converter is shown.

[0049] The number of tests can be set according to actual measurement needs, and then the average value can be taken to improve the test accuracy.

[0050] For example, a phase shift value x is preset.

[0051] The measurement was performed 50 times under the initial control signal, and the average value was taken.

[0052] Then, the phase shift x of the initial control signal is measured 50 times, and the average value is taken.

[0053] Then, the initial control signal is phase-shifted by 2x, measured 50 times, and the average value is taken.

[0054] This process continues until the phase shift value reaches or exceeds one cycle of the high-frequency clock signal (Clk_sys). The sampling result is obtained by superimposing and fitting the above average values.

[0055] Figure 5 In the middle, the Sth n+1 A sampling window triggered by a low-frequency clock signal samples the noise signal on the left once, and the next sampling is triggered by the Sth clock signal. n+1 Triggered by a low-frequency signal, due to the periodicity of the noise signal, Figure 5 The simplified synthesis and final fitting process is shown.

Claims

1. An integrated circuit, characterized by The power switch synchronous noise test circuit is arranged in an integrated circuit chip, and comprises: a clock management and distribution circuit having a high-frequency clock module and a low-frequency clock module, the high-frequency clock module being connected to a measured power supply load circuit, the clock frequency generated by the high-frequency clock module being N times the clock frequency generated by the low-frequency clock module, N being an integer greater than 3, the low-frequency clock module being connected to a control end of a sampling circuit, the low-frequency clock module having a phase control unit; a measured power supply load circuit, the power switch of which is controlled by the high-frequency clock module, a sampling circuit, a signal input end of which is connected to the measured power supply load circuit, and a control end of which is connected to the low-frequency clock module; a digitizing circuit, an input end of which is connected to a signal output end of the sampling circuit, and an output end of which is an output end of the power switch synchronous noise test circuit.

2. The integrated circuit of claim 1, wherein, The phase control unit is used to generate a low-frequency clock signal with a predetermined phase offset value.

3. The integrated circuit of claim 1, wherein, The sampling circuit comprises a switching switch, a resistor and a capacitor, the resistor being arranged between the signal input end and a first selectable end of the switching switch, a second selectable end of the switching switch being connected to the signal output end, and a fixed end of the switching switch being connected to the ground through the capacitor.

4. The integrated circuit of claim 3, wherein, The capacitor is an adjustable capacitor.

5. A method of integrated circuit power supply switching synchronous noise testing, characterized by, The method comprises the following steps: 1) frequency dividing a source clock signal to obtain a low-frequency clock signal and a high-frequency clock signal, the frequency of the high-frequency clock signal being N times the frequency of the low-frequency clock signal, N being an integer greater than 3; 2) controlling the power switch of the measured power supply load circuit with the high-frequency clock signal; 3) adjusting the phase of the low-frequency clock signal, and sampling the output signal of the measured power supply load circuit with the low-frequency clock signal with various phase offset values as the control signal of the sampling circuit; 4) superimposing the sampling results of the low-frequency clock signals with various phase offset values to obtain the output of the test.

6. The integrated circuit power supply switch synchronization noise test method of claim 5, wherein, In step 4), the sampling results of the low-frequency clock signals with various phase offset values are converted into digital signals and then superimposed to obtain the output of the test.

7. The integrated circuit power supply switch synchronization noise test method of claim 5, wherein, The sampling time window width of the sampling circuit is adjustable.

8. The integrated circuit power supply switch synchronization noise test method of claim 5, wherein, In step 3), the phase of the low-frequency clock signal is adjusted by a preset value x as a step, and the phase offset value of the control signal with a serial number n is n*x relative to the initial control signal with a phase shift value of 0, n being a natural number.

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