A binary field elliptic curve cryptography coprocessor

Abstract

The application discloses a binary field elliptic curve cryptography coprocessor, which comprises a data register module, a first modular multiplier module, a second modular multiplier module, a squarer module, an adder module and a controller module; wherein the first modular multiplier module is designed as a two-stage pipeline structure, and the second modular multiplier module is designed as a four-stage pipeline structure, so that the operation frequency of the system can be effectively improved; thus, the high frequency and small area can be maintained while the high performance is kept, and the optimal tradeoff between the area and the performance is realized. The binary field elliptic curve cryptography coprocessor is suitable for the application of lightweight password encryption and decryption in the Internet of Things and has good practicability. The application can be widely applied in the field of information security technology.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of information security, and in particular to a binary field elliptic curve cryptography coprocessor. BACKGROUND

[0002] Mobile communication is moving from traditional human-to-human connection to human-to-object and object-to-object connection, and interconnection of all things is an inevitable trend. With the deep development of the Internet of Things, the number of Internet of Things intelligent terminal devices is showing explosive growth, thereby bringing more complex security problems such as device authentication, data protection and wireless communication. Therefore, it is very important to design a secure cryptographic coprocessor for the Internet of Things system to ensure the security and privacy of data transmission. And with the large-scale deployment and application of 5G devices, the Internet of Things application requires higher speed for data encryption, and the performance of the existing secure cryptographic coprocessor cannot meet the needs of the 5G era, and there is an urgent need for a high-performance and efficient secure cryptographic coprocessor.

[0003] Elliptic Curve Cryptography (ECC) is an effective solution to achieve this goal. Since 1985, when Koblit and Miller published it, ECC has rapidly become the most popular new generation of public key cryptography system with its short key, low latency, high security and fast operation speed, etc. It has been accepted and standardized by international standard organizations such as ANSI, IEEE, NIST and SCA, and widely applied in the field of Internet of Things and information security. ECC can be implemented on software and hardware platforms, and the ECC scheme based on FPGA hardware has the characteristics of reprogrammability, configurability and high-efficiency cryptographic processing performance, making it very suitable for Internet of Things security applications.

[0004] However, the existing elliptic curve cryptographic coprocessor still has the disadvantages of complex structure and high power consumption. And due to the complexity of ECC cryptographic system theory and large amount of calculation, the existing technology is difficult to meet the demand of computing performance. In the prior art, using a low-bit-width multiplier will result in low performance of the operator; using a large number of multipliers will result in high power consumption; using a high-bit-width multiplier will result in low operation performance because the hardware cannot meet the requirements. SUMMARY

[0005] The present application aims at at least solving one of the problems in the prior art. To this end, the present application proposes a binary field elliptic curve cryptography coprocessor.

[0006] The technical solution adopted by the present application is as follows:

[0007] In one aspect, the embodiments of the present application include a binary field elliptic curve cryptography coprocessor, comprising a data register module, a first modular multiplier module, a second modular multiplier module, a squarer module, an adder module and a controller module;

[0008] The data register module is configured to receive inputted original data and save result data obtained by operation on the original data;

[0009] The first modular multiplier module is designed as a two-stage pipeline structure, comprising a first-stage operation unit and a second-stage operation unit, the first-stage operation unit is configured to perform multiplication operation, and the second-stage operation unit is configured to perform KOM operation and modulo reduction operation;

[0010] The second modular multiplier module is designed as a four-stage pipeline structure, comprising a first-stage calculation unit, a second-stage calculation unit, a third-stage calculation unit and a fourth-stage calculation unit, the first-stage calculation unit, the second-stage calculation unit and the third-stage calculation unit are all configured to perform multiplication calculation, and the fourth-stage calculation unit is configured to perform KOM calculation and modulo reduction calculation;

[0011] The squarer module comprises a first-stage squaring operation unit and a second-stage quartic operation unit, the first-stage squaring operation unit and the second-stage quartic operation unit are both configured to perform fast squaring calculation and modulo reduction calculation;

[0012] The adder module is configured to perform modular addition operation;

[0013] The controller module is configured to control the flow direction of data.

[0014] Further, the first-stage operation unit comprises nine binary field multipliers, and the nine binary field multipliers perform multiplication operation in parallel.

[0015] Further, the first modular multiplier module performs one operation in two clock cycles, and the operation process performed by the first modular multiplier module comprises:

[0016] In the first clock cycle, the first-stage operation unit receives first data and performs multiplication operation to obtain first result data, and saves the first result data to the data register module;

[0017] In the second clock cycle, the second-stage operation unit receives the first result data and performs KOM operation and modulo reduction operation.

[0018] Further, the operation process performed by the first modular multiplier module further comprises:

[0019] In the second clock cycle, the first computing unit receives second data and performs multiplication to obtain second result data, and saves the second result data to the data register module.

[0020] Further, the first computing unit, the second computing unit and the third computing unit perform multiplication by time division multiplexing of three binary field multipliers.

[0021] Further, the second module multiplier module performs one operation in four clock cycles, and the operation performed by the second module multiplier module includes:

[0022] In the first clock cycle, the three binary field multipliers of the first computing unit perform three multiplication operations.

[0023] In the second clock cycle, the three binary field multipliers of the second computing unit perform three multiplication operations.

[0024] In the third clock cycle, the three binary field multipliers of the third computing unit perform three multiplication operations.

[0025] In the fourth clock cycle, the fourth computing unit receives third data and performs KOM operation and modulus reduction operation, and the third data includes the multiplication result data of the first computing unit, the multiplication result data of the second computing unit and the multiplication result data of the third computing unit.

[0026] Further, the output of the first square operation unit is the input of the second quartic operation unit, the squarer module performs one operation in one clock cycle, and the operation performed by the squarer module includes:

[0027] In the first clock cycle, the first square operation unit receives fourth data and performs fast square operation and modulus reduction operation to output first computing result data.

[0028] In the first clock cycle, the second quartic operation unit receives the first computing result data and performs fast square operation and modulus reduction operation to output second computing result data.

[0029] Further, the controller module is also used for detecting whether the input k i and k i-1 are equal, and controlling the flow direction of data according to the detection result, k i is a random positive integer input, k i-1 is a previous random positive integer of the input k i .

[0030] Further, the process of controlling the data flow direction by the controller module comprises:

[0031] detecting whether k i and k i-1 are equal, k i is a random positive integer input, k i-1 is the previous random positive integer input of k i ;

[0032] if it is detected that k i and k i-1 are equal, the data flow direction is controlled to the direction of performing the first operation;

[0033] if it is detected that k i and k i-1 are not equal, the data flow direction is controlled to the direction of performing the first operation.

[0034] The beneficial effects of the present application are:

[0035] The present application provides a binary field elliptic curve cryptography coprocessor, comprising a data register module, a first modular multiplier module, a second modular multiplier module, a squarer module, an adder module and a controller module; wherein the first modular multiplier module is designed as a two-stage pipeline structure, and the second modular multiplier module is designed as a four-stage pipeline structure, which can effectively improve the operating frequency of the system; so as to maintain a high frequency and a small area while maintaining high performance, and achieve the best trade-off between area and performance. The binary field elliptic curve cryptography coprocessor is suitable for lightweight password encryption and decryption in the Internet of Things, and has good practicability.

[0036] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter in the description of the application. BRIEF DESCRIPTION OF DRAWINGS

[0037] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the description of the embodiments, taken in conjunction with the following drawings in which:

[0038] Figure 1 is a schematic diagram of the 5CC Montgomery ladder algorithm described in the embodiments of the present application;

[0039] Figure 2 is a framework diagram of the binary field elliptic curve cryptography coprocessor described in the embodiments of the present application;

[0040] Figure 3 is a hardware circuit diagram of the first modular multiplier module described in the embodiments of the present application;

[0041] Figure 4 is a pipeline schematic diagram of the second modular multiplier module described in the embodiments of the present application;

[0042] Figure 5 A schematic diagram of the fast squaring algorithm described in an embodiment of the present application;

[0043] Figure 6 A schematic diagram of the modular inversion algorithm described in an embodiment of the present application;

[0044] Figure 7 A schematic diagram of the data stream without flipping described in an embodiment of the present application;

[0045] Figure 8 A schematic diagram of the data stream with flipping described in an embodiment of the present application. DETAILED DESCRIPTION

[0046] Embodiments of the present application are described in detail below with reference to several drawings. The embodiments described below are illustrative only, and are not intended to limit the present application, as the present application can be embodied in various forms.

[0047] In the description of the present application, it should be understood that the relative description of position, such as up, down, front, back, left, right, etc., is based on the position or relationship shown in the drawings, and is only for the purpose of facilitating the description of the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular position, be constructed and operated in a particular position, and therefore cannot be understood as a limitation of the present application.

[0048] In the description of the present application, the meaning of several is one or more, and the meaning of multiple is more than two, greater than, less than, more than, etc. are understood as not including the number. If the first, second, third, etc. are described, it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or the sequence of technical features indicated.

[0049] In the description of the present application, unless otherwise explicitly limited, the words such as setting, installing, connecting, etc. should be broadly understood, and the person skilled in the art can reasonably determine the specific meaning of the above words in the present application in combination with the specific content of the technical solution.

[0050] The core operation in Elliptic Curve Cryptography (ECC) is the basic operation on the base field and the point multiplication operation on the elliptic curve. The elliptic curve defined on the binary field (GF(2 m )) satisfies the following equation:

[0051] E:y 2 + xy = x3 +ax 2 +b(1);

[0052] This equation is called the Weierstrass equation, where a,b∈GF(2 m ), and b≠0. The elements of the elliptic curve include the set of all points (x, y) in equation (1) and the point O at infinity. The most important operations of the elliptic curve are point addition (PA) and point doubling (PD). Assume that point P = (x p ,y p ) and point Q=(x Q ,y Q ) are all points on the elliptic curve, and the expression for defining PA is R=(x R ,y R )=P+Q, the expression of PD is R=(x R ,y R )=2P. Since elliptic curve operations are based on finite fields, it is necessary to construct finite field operation units such as modular addition, modular multiplication, modular square and modular inverse to implement PA and PD.

[0053] The most complex operation in the ECC algorithm is point multiplication (PM). Let k be a random positive integer. Since PM can be expressed as kP = (k / 2)P + (k / 2)P, PM can be decomposed into two operations: PA and PD. Figure 1 As shown, the embodiment of the present invention proposes a 5CC Montgomery ladder algorithm. In order to effectively resist side channel attacks, Lopez-Dahab coordinates and the Montgomery ladder algorithm are used to calculate the point multiplication. The algorithm does not require the use of y coordinates during the calculation process, only x coordinates and z coordinates are used. However, coordinate conversion is required before and after the point multiplication operation. Since the binary domain elliptic curve cryptography coprocessor proposed in the embodiment of the present invention includes a first modular multiplier module and a second modular multiplier module, the two modules can calculate the point multiplication operation in parallel. Therefore, the calculation of k i The calculation time of the dot multiplication is only 5 clock cycles for one input bit, which is 5 / 6 of the ordinary 6CC Montgomery ladder algorithm.

[0054] Specifically, refer to Figure 2 The embodiment of the present invention provides a binary domain elliptic curve cryptography coprocessor, comprising a data register module, a first modular multiplier module, a second modular multiplier module, a squarer module, an adder module and a controller module; wherein,

[0055] The data register module is used to receive the input original data and save the result data obtained by performing operations based on the original data;

[0056] The first modular multiplier module is designed as a two-stage pipeline structure, comprising a first-stage operation unit and a second-stage operation unit, the first-stage operation unit is used for performing multiplication operation, and the second-stage operation unit is used for performing KOM operation and modulus reduction operation.

[0057] The second modular multiplier module is designed as a four-stage pipeline structure, comprising a first-stage calculation unit, a second-stage calculation unit, a third-stage calculation unit and a fourth-stage calculation unit, the first-stage calculation unit, the second-stage calculation unit and the third-stage calculation unit are all used for performing multiplication calculation, and the fourth-stage calculation unit is used for performing KOM calculation and modulus reduction calculation.

[0058] The squarer module comprises a first-stage square operation unit and a second-stage fourth power operation unit, and the first-stage square operation unit and the second-stage fourth power operation unit are both used for performing fast square calculation and modulus reduction calculation.

[0059] The adder module is used for performing modulus addition operation.

[0060] The controller module is used for controlling the flow direction of data.

[0061] The first modular multiplier module of the embodiment of the present application is used for performing modulus multiplication operation, is designed as a two-stage pipeline structure, and needs 2 clock periods to perform one modulus multiplication operation, so that the system running frequency can be effectively improved. The second modular multiplier module is used for performing modulus multiplication operation, is designed as a four-stage pipeline structure, needs 4 clock periods to perform one modulus multiplication operation, and the area of the second modular multiplier module is about 1 / 3 of the first modular multiplier module. The squarer module is used for performing modulus square operation and modulus fourth power operation, and can simultaneously output the results of modulus square operation and modulus fourth power operation only by using 1 clock period.

[0062] The embodiment of the present application uses an improved Montgomery ladder algorithm, which needs 5 clock periods to calculate one input bit, maintains high frequency and small area while keeping high performance, and realizes the best trade-off between area and performance. Figure 2 The architecture shown is based on the curve GF(2^163) and achieves 346.4MHz, 14321LUT and 2.68us latency on Virtex-7, and realizes very good area-time performance. The binary field elliptic curve cryptography coprocessor proposed in the embodiment of the present application is very suitable for lightweight encryption and decryption applications in the Internet of Things, and has good practicability.

[0063] The architecture of the binary field elliptic curve cryptography coprocessor proposed in the embodiment of the present application is shown in Figure 2 The most important resource consumption of the architecture is two modular multiplier modules designed using KOM-2 algorithm, which are a first modular multiplier module and a second modular multiplier module. Figure 3In the embodiment of the present invention, the first modular multiplier module is designed as a two-stage pipeline structure, including a first-stage operation unit and a second-stage operation unit, wherein the first-stage operation unit is used to perform multiplication operations, and the second-stage operation unit is used to perform KOM operations and modular reduction operations. The first-stage operation unit includes 9 binary field multipliers, and the 9 binary field multipliers perform multiplication operations in parallel. Taking the curve GF(163) as an example, in the first clock cycle, the multiplier mul1_a and the multiplicand mul1_b pass through the XOR array of the KOM-2 algorithm and enter the 9 41-bit binary field multipliers, and the operation results are stored in the register. In the second clock cycle, the data in the register is sent to the second-stage operation unit to perform KOM calculations and modular reduction calculations, and at the same time, the first-stage operation unit will receive new data for multiplication operations. The second modular multiplier module only performs one modular multiplication operation in each cycle of the 5CC Montgomery ladder algorithm. In order to save area, refer to Figure 4 In an embodiment of the present invention, the second modular multiplier module is designed as a 4-stage pipeline structure, including a first-stage calculation unit, a second-stage calculation unit, a third-stage calculation unit, and a fourth-stage calculation unit, wherein the first-stage calculation unit, the second-stage calculation unit, and the third-stage calculation unit are all used to perform multiplication calculations, and the fourth-stage calculation unit is used to perform KOM calculations and modular reduction calculations. The first-stage calculation unit, the second-stage calculation unit, and the third-stage calculation unit perform multiplication calculations by time-sharing multiplexing of three binary field multipliers. Similarly, taking the curve GF(163) as an example, the second modular multiplier module uses three 41-bit binary field multipliers, and performs a total of 9 multiplication operations in the first three clock cycles by time-sharing multiplexing, and stores the operation results in a register. In the fourth clock cycle, the fourth-stage calculation unit receives third data and performs KOM calculations and modular reduction calculations. The third data includes the multiplication calculation result data of the first-stage calculation unit, the multiplication calculation result data of the second-stage calculation unit, and the multiplication calculation result data of the third-stage calculation unit.

[0064] Among them, the KOM-2 algorithm consists of 4 steps, the specific algorithm is as follows:

[0065] Input: m-bit A and B.

[0066] Output: 2m-bit C, C = A·B.

[0067] Step 1: Let A={A3,A2,A1,A0}, B={B3,B2,B1,B0}, that is, A=A3·2 3m / 4 +A2·2 m / 2 +A1·2 m / 4 +A0,B=B3·2 3m / 4 +B2·2 m / 2 +B1·2 m / 4+ B0, wherein A3, A2, A1, A0, B3, B2, B1, B0 are all m / 4 bits;

[0068] Step 2: calculate S1=A0B0, S2=(A1+A0)(B1+B0), S3=A1B1, S4=(A2+A0)(B2+B0), S5=(A3+A2+A1+A0)(B3+B2+B1+B0), S6=(A3+A1)(B3+B1), S7=A2B2, S8=(A3+A2)(B3+B2), S9=A3B3;

[0069] Step 3: calculate C=S9·2 6m / 4 +(S9+S8+S7)·2 5m / 4 +(S9+S7+S6+S3)·2 4m / 4 +(S9+S8+S7+S6+S5+S4+S3+S2+S1)·2 3m / 4 +(S7+S4+S3+S1)·2 2m / 4 +(S3+S2+S1)·2 m / 4 +S1;

[0070] Step 4: output C.

[0071] In the embodiment of the application, in order to reduce the consumption of hardware resources and reduce the delay, the squaring module is designed as a two-stage circuit, the first stage is a first-stage squaring operation unit, and the second stage is a second-stage quartic operation unit, wherein the input of the second stage is the output of the first stage, and the first-stage squaring operation unit and the second-stage quartic operation unit both comprise a fast squaring component and a modulo reduction component. When data squ_a is input, the squaring operation result squ_c and the quartic operation result qua_c can be obtained simultaneously after one clock cycle. Specifically, as a special multiplication operation, the operation efficiency of the squaring operation implemented using the fast squaring algorithm will be higher. The squaring operation and the multiplication operation are separated for operation, which can accelerate the operation efficiency of the system. Referring to Figure 5 , a(x) 2 The binary representation of a(x) can be obtained by inserting a 0 between adjacent bits in the binary representation of a(x). Similarly, in order to reduce the consumption of hardware resources and reduce the delay, the quartic operation also uses the squaring operation.

[0072] In the embodiment, after the basic operation of the finite field is performed, if the numerical value is greater than the maximum numerical value of the finite field, it is necessary to reduce the numerical value based on the polynomial f(x)=x 163 +x 7 +x 6 +x 3+1 to ensure the result is on the finite field. Therefore, a modulo reduction operation usually needs to be accompanied after other basic operations, and a fast modulo reduction algorithm can obtain the reduction result in one clock cycle. The fast modulo reduction algorithm process is as follows:

[0073] Input: C[324:0] of 325 bits.

[0074] Output: R[162:0] of 163 bits, where R = C mod f(x).

[0075] Step 1: Reduce C[324:323]:

[0076]

[0077]

[0078]

[0079]

[0080] Step 2: Reduce C[322:320]:

[0081]

[0082]

[0083]

[0084]

[0085] Step 3: Reduce C

[319] :

[0086]

[0087]

[0088]

[0089]

[0090] Step 4: Reduce C[318:163]:

[0091]

[0092]

[0093]

[0094]

[0095] Step 5: R = C[257:0], output result.

[0096] In this embodiment, considering the inverse operation as the most complex basic operation in the finite field, the operation unit belongs to the longest operation time in the whole system, and occupies about 10% of the operation time. When performing the inverse operation, the first modulus multiplier module, the second modulus multiplier module and the squarer module need to be called, so that when performing the inverse operation, the problem of being unable to simultaneously perform multiplication operation and squaring operation occurs. Based on this problem, the embodiment of the application proposes an Itoh-Tsujii's algorithm, which is an optimization algorithm based on Fermat's little theorem, converts the inverse operation into a small amount of multiplication operation, squaring operation and fourth power operation, and thus can reduce the calculation complexity and shorten the operation time. Referring to Figure 6 , Figure 6 The inverse operation flow of the elliptic curve GF(2^163) is shown. From Figure 6 It can be seen that the inverse operation is converted into 10 times of multiplication operation and a plurality of times of squaring operation.

[0097] In this embodiment, the controller module controls the flow direction of the data to control the operation sequence and process. Specifically, referring to Figure 1 , a set of coordinate data P=(x P ,y P ) and a random number k are input first, wherein k=(k t-1 ,k t-2 ,…,k1,k0), and k t-1 =1. When the operation starts, the input data is registered in the data register module, and then the flow direction of the data is controlled by the controller module to perform corresponding multiplication, KOM operation, modulus reduction operation, fast squaring operation and other operations. The operation result and intermediate data variable are saved in the data register module. Specifically, the monitoring window can be used to scan the random number k from left to right bit by bit, and referring to Figure 1 , the value of i is assigned from t-2 to 0 to execute the following 5 steps, if k i and k i-1 are equal, Z2 is assigned to A in the first step calculation, and X2 is assigned to A in the second step calculation; if k i and k i-1 are not equal, Z1 is assigned to A in the first step calculation, and X1 is assigned to A in the second step calculation. That is, different values are assigned according to different detected situations to perform corresponding operations. After detecting and performing corresponding assignment, go to the third step, assign Z2A 2 to Z2; then go to the fourth step, assign Z1X1 to X1, and assign (Z1+X1) 2 to Z1; then go to the fifth step, assign xZ1+X1 to X1, and assign R+A 4is assigned to X2.The 5 steps are executed in a loop until i equals 0, and the result Q=kP=(x Q ,y Q ) is outputted. Figure 7 Figure 8 In the 5CC algorithm shown in Figure 1 , the first 5 steps are the calculation process of the current bit, and when the 5th step is executed, the next step is the 1st step of the next bit.The time of each step in the figure is a clock cycle, and the operation is in pipeline. Figure 7 When k i =1, k i-1 =1 or k i =0, k i-1 =0, the data stream does not flip. Figure 8 When k i =1, k i-1 =0 or k i =0, k i-1 =1, the data will flip.

[0098] The binary field elliptic curve cryptography coprocessor proposed in the embodiment of the application is implemented based on the curve GF(163), reaches 346.4MHz, 14321LUT and 2.68us delay on Virtex-7, and the comprehensive performance of area and time is only 38.4, very good area-time performance is achieved, and the binary field elliptic curve cryptography coprocessor is very suitable for encryption and decryption applications in the Internet of Things.

[0099] The embodiment of the application is described in detail above in combination with the drawings, but the application is not limited to the above embodiment, and various changes can be made within the knowledge range of ordinary skilled in the art without departing from the purpose of the application.

Claims

1. A dual-field elliptic curve cryptography coprocessor, comprising: The data register module, the first modular multiplier module, the second modular multiplier module, the squarer module, the adder module and the controller module are included. The data register module is used for receiving input original data and saving result data obtained by operation on the original data. The first modular multiplier module is designed as a two-stage pipeline structure, including a first-stage operation unit and a second-stage operation unit. The second modular multiplier module is designed as a four-stage pipeline structure, including a first-stage calculation unit, a second-stage calculation unit, a third-stage calculation unit and a fourth-stage calculation unit. The squarer module includes a first-stage square operation unit and a second-stage fourth power operation unit. The adder module is used for performing modular addition operation. The controller module is used for controlling the flow direction of data. The first-stage calculation unit, the second-stage calculation unit and the third-stage calculation unit perform multiplication calculation through time-sharing multiplexing of three binary field multipliers. The second modular multiplier module performs one operation in four clock cycles. In the first clock cycle, the three binary field multipliers of the first-stage calculation unit perform three multiplication calculations. In the second clock cycle, the three binary field multipliers of the second-stage calculation unit perform three multiplication calculations. In the third clock cycle, the three binary field multipliers of the third-stage calculation unit perform three multiplication calculations. In the fourth clock cycle, the fourth-stage calculation unit receives third data and performs KOM calculation and modular reduction calculation, the third data including multiplication calculation result data of the first-stage calculation unit, multiplication calculation result data of the second-stage calculation unit and multiplication calculation result data of the third-stage calculation unit. The output of the first-stage square operation unit is the input of the second-stage fourth power operation unit. In the first clock cycle, the first-stage square operation unit receives fourth data and performs fast square calculation and modular reduction calculation to output first-stage calculation result data. In the first clock cycle, the second-stage fourth power operation unit receives the first-stage calculation result data and performs fast square calculation and modular reduction calculation to output second-stage calculation result data. The controller module is also used to detect whether the input and is equal, and controls the flow direction of data according to the detection result, the previous random positive integer for the input the input the previous random positive integer for the input 2. A dual-field elliptic curve cryptography coprocessor according to claim 1, wherein, The first-stage operation unit includes nine binary field multipliers, and the nine binary field multipliers perform multiplication operation in parallel.

3. A dual-field elliptic curve cryptography coprocessor according to claim 1, wherein, The first modular multiplier module performs one operation in two clock cycles. In the first clock cycle, the first-stage operation unit receives first data and performs multiplication calculation to output first-stage calculation result data. In the second clock cycle, the second-stage operation unit receives the first-stage calculation result data and performs KOM calculation and modular reduction calculation to output second-stage calculation result data. In a first clock cycle, the first operation unit receives first data and performs multiplication operation to obtain first result data, and saves the first result data to the data register module; In a second clock cycle, the second operation unit receives the first result data and performs KOM operation and modulus reduction operation.

4. A binary field elliptic curve cryptography coprocessor as claimed in claim 3, wherein, The operation process performed by the first modulus multiplier module further includes: In the second clock cycle, the first operation unit receives second data and performs multiplication operation to obtain second result data, and saves the second result data to the data register module.

5. The binary domain elliptic curve cryptography coprocessor according to claim 1, characterized in that: The process of controlling data flow direction by the controller module includes: detecting and whether equal, a random positive integer input, a random positive integer input, the previous random positive integer; If it is detected that and are equal, then the control data flow is directed to perform the first operation. If it is detected that and are not equal, then the control data flow is directed to the direction of performing the first operation.

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