A Modelica Modeling Method for Time-Sequence Discrete Systems

Abstract

The present invention relates to the field of modeling and simulation technologies, and specifically discloses a Modelica modeling method for a time-sequential discrete system. Based on the Modelica language, this method uses the method of creating discrete source modules and general discrete modules to establish discrete task models, and then constructs a time-sequential discrete system model. By configuring the task period and execution time of the discrete source modules of each task model, multi-rate group task time-sequential design and simulation are realized; by introducing a structured data recording module, the single-step / multi-step delay method of structured data is broken through, and the cyclic dependence problem existing in the modeling and simulation of discrete systems is solved. The Modelica modeling method for a time-sequential discrete system provided by the present invention solves the key problem of modeling time-sequential discrete subsystems in the unified modeling and simulation of large-scale systems across the entire field.

Description

Technical Field

[0001] The present invention relates to the technical field of modeling and simulation, and particularly relates to a Modelica modeling method for a time-sequential discrete system. Background Art

[0002] Modelica is an object-oriented multi-domain physical unified modeling language, which can establish physical object models in different disciplinary fields and realize multi-domain unified modeling and co-simulation of large systems. In engineering, a system generally includes continuous objects and discrete objects, and Modelica can support hybrid modeling of the interaction between continuous and discrete components. Taking the numerical control system of an aero-engine as an example, the hydraulic, electronic, and sensing subsystems are continuous objects, and the control software, as the core component of the numerical control system, is a typical discrete object. The characteristics of object-oriented modeling and non-causal statement modeling in the Modelica specification have great advantages in constructing continuous subsystems. However, when constructing discrete objects such as control software, there are the following two problems:

[0003] On the one hand, the discrete control system has obvious time-sequential characteristics, and time-sequential design and verification are the key objectives for modeling and simulating the control software. Modelica supports discretizing modules by inheriting standard discrete classes, and the execution period and execution time can be configured. A typical control software is generally composed of several tasks. The software realizes multi-rate group time-sequential scheduling of all tasks through the underlying scheduling mechanism. Each task in the software is generally composed of hundreds of basic functions. Correspondingly, in the Modelica model, a top-level task model needs to be built from hundreds of basic modules. When setting or changing the execution period and execution time of a task, it is necessary to set the parameters of each basic module in the task model, and the design and iteration are difficult.

[0004] On the other hand, structured data ports (Connectors) are widely used in the discrete control system model to depict the data flow between one task and another. Taking Figure 1 the shown simple time-sequential discrete system as an example, when the task execution order is A - B - C, in the control software, it is only necessary to execute tasks A, B, and C in sequence and update the output data ports a, b, and c respectively. However, in the model, if the outputs and inputs between tasks are directly connected, there will be circular dependencies, resulting in model compilation failure. According to the execution time sequence, the data c actually used by task A is the data updated in the previous cycle of task C. Therefore, in the models of commercial tools such as Matlab / Simulink, a delay module (Z Figure 1 is generally connected after the data port c. -1) to remove the circular dependency. This process is necessary and widespread in discrete time systems. For the Modelica model, since its delay module is implemented based on the built-in pre() function, this function only supports built-in data types such as Real, Bool, and array, and does not support structured data ports (Connectors), it is necessary to perform Z on each bit of data in the Connector during modeling. -1 When the amount of data in the Connector reaches dozens or hundreds, the workload of modeling and maintenance will increase rapidly.

[0005] The above two problems make it difficult for Modelica-based models to be used in large-scale discrete time systems. As discrete electronic control gradually replaces mechanical hydraulic control in the fields of aviation and aerospace, the application and advancement of multidisciplinary unified modeling and simulation technology based on Modelica in related fields has been greatly restricted. Summary of the invention

[0006] In view of the defects and shortcomings in the prior art, the present invention provides a Modelica modeling method for time-series discrete systems. First, a discrete source module is constructed, and a task is taken as a unit. All general discrete modules inherit the same discrete source module parameters. By setting the discrete source module parameters, the execution cycle and execution time of all basic modules in the task can be modified with one click, and on this basis, multi-rate group timing scheduling modeling and simulation for time-series discrete systems are realized; the present invention solves the circular dependency problem in large-scale time-series discrete system models by introducing a structured data recording and reading mechanism.

[0007] As a first aspect of the present invention, a Modelica modeling method for a time series discrete system is provided, comprising:

[0008] Step S1: constructing a standard module package that inherits the same discrete source module, wherein the standard module package includes a discrete source module and a general discrete module;

[0009] Step S2: constructing a plurality of task packages inheriting the same discrete source module according to the standard module package, wherein each task package includes the standard module package and a task model;

[0010] Step S3: instantiate all task models and establish connection relationships between data ports of each task model to construct a multi-rate group task scheduling discrete control system model;

[0011] Step S4: Based on the multi-rate group task scheduling discrete control system model, a single-step / multi-step delay module of each task model data port is constructed to achieve single-step / multi-step delay of each task model port data.

[0012] Further, construct a standard module package that inherits the same discrete source module. The standard module package includes a discrete source module and a general discrete module, and further includes:

[0013] Step S1-1: Construct the discrete source module through the Discrete Block in the Modelica standard library. The discrete source module includes an execution period and a start execution time, which are two key configurable parameters for multi-rate group timing scheduling, and generate a periodic pulse Trigger according to the execution period and the start execution time;

[0014] Step S1-2: The general discrete module corresponds to the general functions in the software. All general discrete modules first inherit the discrete source module, and all algorithm statements are executed when the periodic pulse Trigger is valid to achieve discrete execution of the functions of the general discrete module according to the execution period and the start execution time. When the execution period and start execution time parameters in the discrete source module change, the default values of the corresponding parameters in the general discrete module change synchronously.

[0015] Further, construct multiple task packages that inherit the same discrete source module according to the standard module package. Each task package includes a standard module package and a task model, and further includes:

[0016] Step S2-1: Create a new Package as the task package and copy a standard module package at its next level;

[0017] Step S2-2: Integrate and construct a task model under the task package. The task model is built using the general discrete module in the standard module package and the continuous general module in the Modelica standard library. The input and output of the task model are structured data ports;

[0018] Step S2-3: Repeat Step S2-1 and Step S2-2 to establish multiple task packages. The execution periods and start execution times of each task model inherit the discrete source modules in their own standard module packages.

[0019] Further, instantiate all task models and establish the connection relationships between the data ports of each task model to construct a multi-rate group task scheduling discrete control system model, including:

[0020] Step S3-1: Establish a data recording module of the record type and instantiate the structured data ports of all task models in the data recording module;

[0021] Step S3-2: The input data port of the task model reads data from the data recording module, and the output data port writes data to the data recording module, establishing the connection relationship between each task model through the reading and writing of port data.

[0022] Further, based on the multi-rate group task scheduling discrete control system model, a single-step / multi-step delay module for the data ports of each task model is constructed to achieve the single-step / multi-step delay of the port data of each task model, including:

[0023] The single-step / multi-step delay module for the data ports of each task model is constructed in two ways: non-causal equation and algorithm equation;

[0024] Among them, the non-causal equation is a typical Modelica equation, starting with the keyword "equation", and all equations are solved simultaneously during simulation without a sequential solution order;

[0025] Among them, the algorithm equation is different from the non-causal equation, starting with the keyword "algorithm", and during the solution, the assignment operation is performed step by step according to the statement order.

[0026] Further, based on the principle that there is a delay in writing to the software buffer, assuming that the output completes reading data from the data recording module at the time (StartTime, PeriodTime), then the input completes writing data to the data recording module at the time (StartTime + dT, PeriodTime), where dT < PeriodTime and dT is time, thus realizing the single-step delay of the output relative to the input;

[0027] Similarly, for the n-step delay, an n-dimensional array of the data port is constructed, denoted as bus[n]. The output completes reading data of bus[n] from the data recording module at the time (StartTime, PeriodTime), the input completes writing data to bus[1] of the data recording module at the time (StartTime + n * dT, PeriodTime), and at the time (StartTime + k * dT, PeriodTime), bus[n - k] completes writing data to bus[n - k + 1], thus realizing the n-step delay of the output relative to the input, where k = 1, 2,... n - 1 and n * dT < PeriodTime.

[0028] Furthermore, the algorithm equation is based on the principle that the software is executed in code order, and the output reads data from the data recording module at the time (StartTime, PeriodTime) and the input writes data to the data recording module at the time (StartTime+dT, PeriodTime), thereby realizing a single-step delay of the output relative to the input;

[0029] Similarly, for an n-step delay, construct an n-dimensional array of data ports, denoted as bus[n]. At (StartTime, PeriodTime), the output reads data from bus[n] of the data recording module, the input writes data to bus[1] of the data recording module at (StartTime+n*dT, PeriodTime), and bus[nk] writes data to bus[n-k+1] at (StartTime+k*dT, PeriodTime). The output is delayed n steps relative to the input.

[0030] Furthermore, the universal discrete module includes a sampler, a counter and an integrator.

[0031] The Modelica modeling method for time-series discrete systems provided by the present invention has the following advantages:

[0032] 1. The present invention constructs discrete source modules and takes a task as a unit. All general discrete modules inherit the same discrete source module parameters. By setting the discrete source module parameters, the execution cycle and execution time of all basic modules in the task can be modified with one click. On this basis, multi-rate group timing scheduling modeling and simulation for sequential discrete systems are realized, filling the gap in the modeling technology of sequential discrete systems based on the Modelica language.

[0033] 2. The present invention introduces a structured data recording and reading mechanism to solve the circular dependency problem in the sequential discrete system model connected by structured data ports, thus breaking the application bottleneck of Modelica in large discrete / hybrid systems;

[0034] 3. The present invention implements a single-step / multi-step delay method for structured data, which cleverly solves the problem of using the structured data of the previous cycle or the previous N cycles of the system in discrete objects in the Modelica language. This problem is common in systems with tasks such as bus communication and redundancy voting. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation of the present invention.

[0036] Figure 1 It is a schematic diagram of a typical circular dependency problem model.

[0037] Figure 2 It is a schematic diagram of the modeling object in a specific embodiment of the present invention.

[0038] Figure 3 It is a schematic diagram of the modeling principle for a time-sequential discrete system in a specific embodiment of the present invention.

[0039] Figure 4 It is a schematic diagram of the simulation results of multi-rate group task scheduling for time-sequential discrete objects in a specific embodiment of the present invention.

[0040] Figure 5 It is a schematic diagram of the simulation results of a hybrid system in a specific embodiment of the present invention.

[0041] Figure 6 It is a schematic diagram of the simulation results of single-step / multi-step delay of structured data in a specific embodiment of the present invention.

[0042] Figure 7 It is a flowchart of the Modelica modeling method for a time-sequential discrete system provided by the present invention. Detailed implementation manners

[0043] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments.

[0044] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0045] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to describe the embodiments of the present invention here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0046] Figure 2 As an example of a hybrid system simplified according to a typical application scenario of an engine control system, the characteristics of each object in the system are shown in Table 1. Among them, Tasks 1 to 3 are discrete tasks, forming a sequential discrete subsystem, and Task 4 is a continuous object.

[0047] Table 1 Object Parameters of the Hybrid System

[0048] Object Execution cycle (s) Start execution time (s) Task 1 0.1 0 Task 2 0.25 0.03 Task 3 0.5 0.05 Task 4 -- --

[0049] In this embodiment, a Modelica modeling method for a sequential discrete system is provided. Figure 7 It is a flowchart of the Modelica modeling method for a sequential discrete system provided by the present invention. As Figure 7 shown, the Modelica modeling method for a sequential discrete system includes:

[0050] Step S1: Construct a standard module package that inherits the same discrete source module. The principle is shown in Figure 3 , and the standard module package refers to the package type in Modelica. Among them, the standard module package includes a discrete source module and a general discrete module;

[0051] Step S2: According to the standard module package, construct multiple task packages that inherit the same discrete source module with one task as a unit. Among them, each task package includes the standard module package and a task model;

[0052] Step S3: Instantiate all task models and establish the connection relationship between the data ports of each task model to construct a multi-rate group task scheduling discrete control system model;

[0053] Step S4: According to the multi-rate group task scheduling discrete control system model, construct single-step / multi-step delay modules for the data ports of each task model to realize the single-step / multi-step delay of the port data of each task model.

[0054] Preferably, for the construction of the standard module package that inherits the same discrete source module, where the standard module package includes a discrete source module and a general discrete module, it further includes:

[0055] Step S1-1: Construct the discrete source module through the Discrete Block in the Modelica standard library. The Modelica standard library refers to the Modelica standard predefined package developed and maintained by the Modelica Association. Among them, the discrete source module includes an execution period PeriodTime and a start execution time StartTime. The execution period and the start execution time are two key configurable parameters for multi-rate group time series scheduling, and a periodic pulse Trigger = sample(StartTime, PeriodTime) is generated based on the execution period PeriodTime and the start execution time StartTime.

[0056] Step S1-2: The general discrete module pairs with the general functions in the software. The general discrete module refers to the module related to the simulation step length in the general module, such as sampling, counter, integrator, etc. All general discrete modules first inherit the discrete source module in Step S1-1, and all algorithm statements are executed when the periodic pulse Trigger is valid to achieve discrete execution of the general discrete module function according to the execution period and the start execution time. Among them, when the execution period and the start execution time parameters in the discrete source module change, the default values of the corresponding parameters in the general discrete module change synchronously.

[0057] Preferably, according to the standard module package, construct multiple task packages that inherit the same discrete source module. The principle is shown in Figure 3 , where each task package includes a standard module package and a task model, and also includes:

[0058] Step S2-1: Create a Package as Task Package 1 and copy a standard module package at its next level.

[0059] Step S2-2: Integrate and construct a Task 1 model under Task Package 1. The Task 1 model is built using the general discrete module in the standard module package and the continuous general module in the Modelica standard library. Among them, the inputs and outputs of the task model are structured data ports (Connectors).

[0060] It should be noted that the continuous general module refers to a module that is only related to real-time input and has nothing to do with the simulation step length, such as a mathematical operation module, a logic module, etc. The structured data port refers to structured data composed of data of one or more different data types or other structured data. In the Modelica language, direct operations such as delay and arithmetic are not allowed.

[0061] Step S2-3: Repeat Step S2-1 and Step S2-2 to establish Task Package 2, Task Package 3, and Task Package 4. Modify the execution period and start execution time of each task model according to the parameters in Table 1. The execution period and start execution time of each task model inherit the discrete source module in its own standard module package.

[0062] Preferably, instantiate all task models and establish the connection relationships between the data ports of each task model to construct a multi-rate group task scheduling discrete control system model. For the cyclic dependency problem that occurs in the connections between task models, solve the cyclic dependency problem that appears in the solution by replacing the direct connection to establish an equation relationship with the operation of reading and writing port data from the data recording module. The specific method is as follows:

[0063] Step S3-1: Establish a data recording module BusRecord of the record type, and instantiate the structured data ports of all task models in the data recording module;

[0064] Step S3-2: The input data port of the task model reads data from the data recording module, and the output data port writes data to the data recording module. Establish the connection relationships between each task model through the reading and writing of port data.

[0065] Discrete Tasks 1 to 3 have built-in counters, and the counter is incremented by 1 for each step of execution. The execution status of each task is shown in Figure 4 , which is consistent with the timing design. The simulation results of the hybrid system model are as shown in Figure 5 . The timing discrete system and the continuous object can be hybrid-simulated, meeting the expectations. Among them, all task object inputs and outputs are structured data ports (Connectors), and only one parameter is plotted in the simulation curve to display the results.

[0066] Preferably, using the principle of Step S3, the construction of single-step / multi-step delay modules for structured data ports (Connectors) can be achieved. The model simulation results are as shown in Figure 6 . Construct the single-step / multi-step delay modules for the data ports of each task model in two ways: non-causal equations and algorithmic equations; among them, the non-causal equation is a typical Modelica equation, starting with the keyword equation, and all equations are solved simultaneously during simulation, without a sequence of solution; among them, the algorithmic equation is distinguished from the non-causal equation, starting with the keyword algorithm, and during solution, assignment operations are performed step by step according to the statement order. The implementation method of the non-causal equation for single-step delay is shown in Table 2, and the implementation method for n-step delay is shown in Table 3. Among them, k = 1, 2,... n - 1, and n*dT < PeriodTime.

[0067] Table 2 Implementation method of single-step delay module

[0068] Non-causal equation execution time Non-causal equation execution content Algorithm equation execution order sample(StartTime,PeriodTime) Out = bus Out := bus sample(StartTime + dT,PeriodTime) bus = In bus := In

[0069] Table 3 Implementation method of n-step delay module

[0070] Non-causal equation execution time Non-causal equation execution content Algorithm equation execution order sample(StartTime,PeriodTime) Out = bus[n] Out := bus[n] sample(StartTime + dT,PeriodTime) bus[n] = bus[n - 1] bus[n] := bus[n - 1] … … … sample(StartTime + k * dT,PeriodTime) bus[n - k + 1] = bus[n - k] bus[n - k + 1] := bus[n - k] … … … sample(StartTime + (n - 1) * dT,PeriodTime) bus[2] = bus[1] bus[2] := bus[1] sample(StartTime + n * dT,PeriodTime) bus[1] = In bus[1] := In

[0071] Preferably, the non-causal equation is based on the principle that the writing of the software buffer has a delay. Assuming that the output completes reading data from the data recording module at the time (StartTime, PeriodTime), the input completes writing data to the data recording module at the time (StartTime + dT, PeriodTime), where dT < PeriodTime and dT is time, then a single-step delay of the output relative to the input is achieved.

[0072] Similarly, for an n-step delay, an n-dimensional array of data ports is constructed, denoted as bus[n]. The output completes reading data from bus[n] of the data recording module at the time (StartTime, PeriodTime), the input completes writing data to bus[1] of the data recording module at the time (StartTime + n * dT, PeriodTime), and bus[n - k] completes writing data to bus[n - k + 1] at the time (StartTime + k * dT, PeriodTime), then an n-step delay of the output relative to the input is achieved, where k = 1, 2,..., n - 1 and n * dT < PeriodTime.

[0073] Preferably, the algorithm equation is based on the principle that the software executes in the order of the code. At the time (StartTime, PeriodTime), the operations of the output reading data from the data recording module and the input writing data to the data recording module at the time (StartTime + dT, PeriodTime) are sequentially executed, then a single-step delay of the output relative to the input is achieved.

[0074] Similarly, for an n-step delay, an n-dimensional array of data ports is constructed, denoted as bus[n]. At the time (StartTime, PeriodTime), the operations of the output reading data from bus[n] of the data recording module and the input completing writing data to bus[1] of the data recording module at the time (StartTime + n * dT, PeriodTime) are sequentially executed, and bus[n - k] completes writing data to bus[n - k + 1] at the time (StartTime + k * dT, PeriodTime), then an n-step delay of the output relative to the input is achieved.

[0075] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present invention. However, the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A Modelica modeling method for time-sequential discrete systems, characterized in that The Modelica modeling method for the time-sequential discrete system includes: Step S1: Construct a standard module package that inherits the same discrete source module, where the standard module package includes a discrete source module and a general discrete module; Step S2: Based on the standard module package, construct multiple task packages that inherit the same discrete source module, where each task package includes the standard module package and a task model; Step S3: Instantiate all task models and establish the connection relationships between the data ports of each task model to construct a multi-rate group task scheduling discrete control system model; Step S4: Based on the multi-rate group task scheduling discrete control system model, construct single-step / multi-step delay modules for the data ports of each task model to achieve single-step / multi-step delay of the port data of each task model; Among them, the instantiating all task models and establishing the connection relationships between the data ports of each task model to construct a multi-rate group task scheduling discrete control system model includes: Step S3-1: Establish a data record module of the record type and instantiate the structured data ports of all task models in the data record module; Step S3-2: The input data port of the task model reads data from the data record module, and the output data port writes data to the data record module, and the connection relationships between each task model are established through the reading and writing of port data; Among them, the constructing single-step / multi-step delay modules for the data ports of each task model based on the multi-rate group task scheduling discrete control system model to achieve single-step / multi-step delay of the port data of each task model includes: Construct single-step / multi-step delay modules for the data ports of each task model in two ways: non-causal equations and algorithmic equations; Among them, the non-causal equation is a typical Modelica equation, starting with the keyword equation, and all equations are solved simultaneously during simulation without a sequence of solution; Among them, the algorithmic equation is different from the non-causal equation, starting with the keyword algorithm, and during solution, assignment operations are performed step by step according to the statement sequence.

2. The Modelica modeling method for a time-sequential discrete system according to claim 1, wherein The constructing a standard module package that inherits the same discrete source module, where the standard module package includes a discrete source module and a general discrete module, further includes: Step S1-1: Construct the discrete source module through the Discrete Block of the Modelica standard library; where the discrete source module includes an execution period and a start execution time, and the execution period and the start execution time are two key configurable parameters for multi-rate group time-sequential scheduling, and a periodic pulse Trigger is generated according to the execution period and the start execution time; Step S1-2: The general discrete module targets the general functions in the software. All general discrete modules first inherit the discrete source module, and all algorithm statements are executed when the periodic pulse Trigger is valid, so as to realize the discrete execution of the general discrete module function according to the execution period and the start execution time. Among them, when the execution period and the start execution time parameters in the discrete source module change, the default values of the corresponding parameters in the general discrete module change synchronously.

3. The Modelica modeling method for a time-sequential discrete system according to claim 2, characterized in that, Based on the standard module package, multiple task packages that inherit the same discrete source module are constructed. Each task package includes a standard module package and a task model, and further includes: Step S2-1: Create a new Package as a task package, and copy a standard module package at its next level. Step S2-2: Integrate and construct a task model under the task package. The task model is built using the general discrete module in the standard module package and the continuous general module in the Modelica standard library. The input and output of the task model are structured data ports. Step S2-3: Repeat Step S2-1 and Step S2-2 to establish multiple task packages. The execution periods and start execution times of each task model inherit the discrete source module in its own standard module package.

4. The Modelica modeling method for a time-sequential discrete system according to claim 1, characterized in that The non-causal equation is based on the principle that there is a delay in writing to the software buffer. Assuming that the output completes reading data from the data recording module at (StartTime, PeriodTime), then the input completes writing data to the data recording module at (StartTime + dT, PeriodTime), where dT < PeriodTime and dT is time, so as to realize a single-step delay of the output relative to the input. Similarly, for an n-step delay, construct an n-dimensional array of data ports, denoted as bus[n]. The output completes reading data from bus[n] of the data recording module at (StartTime, PeriodTime), the input completes writing data to bus[1] of the data recording module at (StartTime + n * dT, PeriodTime), and at (StartTime + k * dT, PeriodTime), bus[n - k] completes writing data to bus[n - k + 1], then the output has an n-step delay relative to the input, where k = 1, 2, … n - 1 and n * dT < PeriodTime.

5. The Modelica modeling method for a time-sequential discrete system according to claim 1, characterized in that The algorithm equation is based on the principle that the software executes according to the code order. At (StartTime, PeriodTime), the operations of the output reading data from the data recording module and the input writing data to the data recording module at (StartTime + dT, PeriodTime) are executed in sequence, so as to realize a single-step delay of the output relative to the input. Similarly, for an n-step delay, an n-dimensional array of data ports is constructed, denoted as bus[n]. At the time (StartTime, PeriodTime), the operations are sequentially performed as follows: output reads data from bus[n] of the data recording module, input writes data to bus[1] of the data recording module at the time (StartTime + n*dT, PeriodTime), and at the time (StartTime + k*dT, PeriodTime), bus[n - k] writes data to bus[n - k + 1]. Then, the output is delayed by n steps relative to the input.

6. The Modelica modeling method for a time-sequential discrete system according to claim 1, wherein The general discrete module includes a sampler, a counter, and an integrator.

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