A low-cost inter-chip reliable communication method

Abstract

The application provides a low-cost inter-chip reliable communication method, comprising: taking two GPIOs on two chips to simulate a two-wire bus, the two-wire bus comprising a DATA line and a SYNC line; defining a byte comprising nine bits, the first bit being a start bit and the last eight bits being data bits, and the start bit being low; setting two clock periods for each data bit, comprising a sending clock period and a response clock period; when sending data, the sending end outputs the sending clock period, waits for the response clock period, and after detecting the rising edge of the response to interrupt, continues to send the next bit of data, and the data is sent in a loop; when receiving data, it is judged whether the first bit of the byte is low, if yes, the level of the DATA line is read after the rising edge of the SYNC is received to obtain the data bit data, the response clock is output, and the process is repeated until the reception of all data bits is completed; otherwise, it is directly exited. The method realizes reliable communication between two low-cost chips.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, and a low-cost inter-chip reliable communication method. BACKGROUND

[0002] More and more Internet of Things products (such as door locks) use WIFI SOC, Bluetooth SOC chips as master control chips. Compared with the traditional master control chip + WIFI / Bluetooth chip architecture, using WIFI / Bluetooth SOC chips can effectively reduce the complexity of software and hardware design and reduce the overall cost. However, WIFI / Bluetooth SOC also brings certain limitations in software and hardware design:

[0003] First, WIFI / Bluetooth SOC resources are preferentially used to ensure the implementation of WIFI protocol stack and Bluetooth protocol stack, and the remaining resources can be used for the development of related application software. Meanwhile, the peripheral resources of WIFI / Bluetooth SOC chips are much less than general-purpose processors, such as the number of GPIOs, the number of UARTs, the number of SPIs, and the number of I2Cs. Therefore, we often need to use GPIO simulation to realize communication between two WIFI / Bluetooth SOC chips. The traditional method is to use GPIO simulation UART, GPIO simulation SPI, or GPIO simulation I2C to communicate between two WIFI / Bluetooth SOCs. However, this operation cannot guarantee reliability and may lose data with a high probability. Because the resources of SOC chips are preferentially used to ensure the implementation of WIFI / Bluetooth protocol stack, the real-time performance of GPIO simulation interrupt cannot be guaranteed, and the interrupt delay is random and uncontrollable. Therefore, the traditional GPIO simulation UART, SPI, I2C, etc. is not suitable for the implementation of GPIO simulation communication between WIFI / Bluetooth SOC chips. Therefore, a reliable communication method suitable for WIFI / Bluetooth SOC chips needs to be studied. SUMMARY

[0004] The technical problem to be solved by the present application is to provide a low-cost inter-chip reliable communication method that can be used for reliable communication between two SOCs and can guarantee the reliability of data communication without being affected by WIFI protocol stack, Bluetooth protocol stack, etc.

[0005] The present application is implemented as follows: a low-cost inter-chip reliable communication method, comprising the following steps:

[0006] Step S1: Take two GPIOs on two chips to simulate a two-wire bus, the two-wire bus includes a DATA line and a SYNC line, the DATA line is used for data transmission, and the SYNC line is used for triggering data transmission and responding to data reception;

[0007] Step S2, defining a byte including 9 bits, the first bit is a start bit, and the last eight bits are data bits, and the start bit must be low;

[0008] Step S3, setting two clock cycles for each data bit, including a sending clock cycle and a response clock cycle, the sending clock cycle is output by the sending end, the response clock cycle is output by the receiving end, and both use rising edge triggering mechanism;

[0009] Step S4, when sending data, the sending end outputs the sending clock cycle, waits for the response clock cycle, and after detecting the rising edge interruption of the response, it is considered that the receiving end has read the data, and the next bit of data is sent, and the data is sent in a loop;

[0010] Step S5, when receiving data, it is judged whether the first bit of the byte is low, if yes, the DATA line level is read after receiving the rising edge interruption of SYNC, the data bit data is obtained, the response clock is output, and the process is repeated until all data bits are received; otherwise, directly exit, and do not output the response clock.

[0011] Further, on the DATA line, 1 is defined as high level and 0 is defined as low level, and on the SYNC line, 1 is defined as high level and 0 is defined as low level.

[0012] Further, the DATA line and the SYNC line are respectively provided with an upper pull resistor, so that in the idle state, the external resistance is pulled up, the DATA line and the SYNC line are both in high level, and the two ends of the chip GPIO are in input state.

[0013] Further, the step S4 specifically includes:

[0014] Step S41, before sending data, first detect whether the bus is in idle state and whether the SYNC line is in high level, if one of the two conditions is not met, it means that the opposite end has initiated data communication, and data cannot be sent, and the process is ended; if both conditions are met, it means that the bus is in idle state, and data sending is started;

[0015] Step S42, when sending data, the interruption function of the SYNC line is closed, and the low level is output, and the DATA line is also switched to the output state;

[0016] Step S43, sending the start bit, the SYNC line outputs low level, the DATA outputs low level, and delays for a specific time;

[0017] Step S44, prepare to output a sending clock cycle, close the CPU interrupt, the SYNC line is configured as input, at this time the SYNC line will gradually become high level, delay for a specific time, so as to wait for the SYNC line to become high level completely, at this time enable the rising edge interrupt of the SYNC line, open the CPU interrupt, wait for the trigger of the rising edge interrupt of the SYNC line, after detecting the rising edge interrupt of the SYNC line, it is explained that the other party has received the bit data, at the same time, close the SYNC line interrupt, delay for a specific time, then loop the process of sending data bit data, until all data bits are sent.

[0018] Further, the step S5 specifically comprises:

[0019] Step S51, when receiving data, the bus is in idle state, and the SYNC line is in the state of enabling the rising edge interrupt, after detecting the rising edge interrupt of the SYNC line, if the bus is in idle state before, then enter the receiving state;

[0020] Step S52, if the first bit of a byte is received, then judge whether it is low level, if yes, then enter step S53, otherwise directly exit, end the flow;

[0021] Step S53, after receiving the rising edge interrupt, read the DATA level, obtain the data bit data, prepare to output a response clock, first close the SYNC interrupt, the SYNC is configured as output low, delay for a specific time, keep the SYNC as low, then lock the CPU interrupt, the SYNC is configured as input, delay for a specific time, so as to make the SYNC rise to a high enough level, enable the rising edge interrupt of the SYNC, at the same time, open the CPU interrupt, thus a complete acceptance of a data bit is completed, repeat the process until the reception of all data bits is completed, after the reception timeout, switch the bus state to the idle state again.

[0022] Further, the DATA line is unidirectional control, the sending end is push-pull output, and the receiving end is input, the SYNC line is bidirectional control, and the sending end and the receiving end need to be switched between sending and receiving.

[0023] Further, the two chips are two SOCs, and the two SOCs adopt any one combination mode of WIFI SOC and WIFI SOC, and Bluetooth SOC and Bluetooth SOC.

[0024] The application has the following advantages: the application simulates two GPIOs on two low-cost chips into a two-wire bus, defines corresponding bus communication rules, adopts a data bit double clock cycle mechanism, guarantees the reliability of data communication, makes it not affected by any interrupt delay, and effectively improves the communication reliability between the two low-cost chips. BRIEF DESCRIPTION OF DRAWINGS

[0025] The application will be further described below with reference to the drawings and embodiments.

[0026] Fig. 1 The flow chart of the low-cost inter-chip reliable communication method of the application.

[0027] Fig. 2 The analog communication timing diagram in a specific embodiment of the application. DETAILED DESCRIPTION

[0028] As Figs. 1-2 shown, the low-cost inter-chip reliable communication method provided by the application comprises the following steps:

[0029] Step S1, two GPIOs are taken on two chips to simulate a two-wire bus, the two-wire bus comprises a DATA line (data line) and a SYNC line (synchronization line), the DATA line is used for data transmission, and the SYNC line is used for triggering data sending and responding to data receiving; wherein the two chips are two SOCs, such as two SOCs arranged in a door lock device, and the two SOCs adopt any one combination mode of WIFI SOC and WIFI SOC, and Bluetooth SOC and Bluetooth SOC.

[0030] Step S2, define a byte comprising 9 bits, the first bit is a start bit, and the last eight bits are data bits, and the start bit must be low; see Fig. 2 ;

[0031] Step S3, set two clock periods for each data bit, including a sending clock period and a response clock period, the sending clock period is output by the sending end, the response clock period is output by the receiving end, and both adopt the mechanism of rising edge triggering;

[0032] Step S4, when sending data, the sending end outputs the sending clock period, waits for the response clock period, after detecting the rising edge interruption of the response, it is considered that the receiving end has read the data, and the next bit of data is continuously sent, and the data is sent in this way;

[0033] Step S5, when receiving data, it is judged whether the first bit of the byte is low, if yes, the DATA line level is read after receiving the rising edge interruption of SYNC, the data bit data is obtained, the response clock is output, and the process is repeated until the reception of all data bits is completed; otherwise, directly exit without outputting the response clock.

[0034] As Fig. 2As shown, one data bit has two clock periods, the first is the data sending clock period, controlled by the sending end, and the second is the response clock period, controlled by the data receiving end. The sending clock period of the data bit is output by the sending end, and uses a rising edge triggering mechanism. The receiving end detects the rising edge interrupt, and can collect the data on the data line. The response period of the data bit is output by the receiving end, and also uses a rising edge triggering mechanism. After the sending end outputs the sending clock period, it starts to wait for the response clock period. After detecting the rising edge interrupt of the response, it can be considered that the receiving end has read the data, and the next data bit can be continuously sent, to thereby cyclically send data.

[0035] In a preferred embodiment, on the DATA line, 1 is defined as a high level and 0 is defined as a low level, and on the SYNC line, 1 is defined as a high level and 0 is defined as a low level.

[0036] In a preferred embodiment, an upper pull resistor is additionally arranged outside the DATA line and the SYNC line, so that in the idle state, the external resistor is pulled high, the DATA line and the SYNC line are both at a high level, and the two GPIOs of the chip are both in an input state.

[0037] In a preferred embodiment, the step S4 specifically comprises:

[0038] Step S41, before sending data, first detect whether the bus is in an idle state and whether the SYNC line is at a high level. If one of the two conditions is not satisfied, it indicates that the opposite end has initiated data communication, and data cannot be sent (otherwise, bus conflict will be caused), and the process is ended. If both conditions are satisfied, it indicates that the bus is in an idle state, and data sending is started.

[0039] Step S42, when sending data, the interrupt function of the SYNC line is closed, and the SYNC line is output at a low level. The DATA line is also switched to an output state.

[0040] Step S43, a start bit is sent. The SYNC line is output at a low level, the DATA line is output at a low level, and a specific time (which can be adjusted according to specific conditions, such as 20 microseconds, 50 microseconds, 100 microseconds, etc.) is delayed.

[0041] Step S44, prepare to output the sending clock period, close the CPU interrupt, the SYNC line is configured as input, at this time the SYNC line will gradually become high, delay for a specific time, such as 2 microseconds, in order to wait for the SYNC line to become high completely, enable the rising edge interrupt of the SYNC line (in order to wait for the accepting party to output the response clock period), open the CPU interrupt, wait for the trigger of the rising edge interrupt of the SYNC line, after detecting the rising edge interrupt of the SYNC line, it is indicated that the other party has received the bit data, at the same time, close the SYNC line interrupt, delay for a specific time, and then loop the process to send the data of the data bit, until all the data bits are sent.

[0042] In a preferred embodiment, the step S5 specifically comprises:

[0043] Step S51, when receiving data, the bus is normally in an idle state (both high), and the SYNC line is in an enabled rising edge interrupt state, after detecting the rising edge interrupt of the SYNC line, if the bus is previously in an idle state, enter the receiving state;

[0044] Step S52, if the first bit of a byte is received, judge whether it is low, if yes, enter step S53, otherwise, directly exit and end the flow;

[0045] Step S53, after receiving the rising edge interrupt, read the DATA level, obtain the data bit data, prepare to output the response clock, first close the SYNC interrupt, the SYNC is configured as output low, delay for a specific time, such as 5 microseconds, keep the SYNC low, then lock the CPU interrupt, the SYNC is configured as input, delay for a specific time, in order to make the SYNC rise to a high enough level, enable the rising edge interrupt of the SYNC (for waiting for the sending clock period of the next data bit), at the same time, open the CPU interrupt, thus a complete acceptance of a data bit is completed, repeat the process until the reception of all data bits is completed, after the reception timeout, switch the bus state to the idle state again.

[0046] In a preferred embodiment, the resistance value of the pull-up resistor is 4.7K ohms, and the specific resistance value can be adjusted according to the actual situation.

[0047] In a preferred embodiment, the DATA line is unidirectional control, the sending end is push-pull output, and the receiving end is input, the SYNC line is bidirectional control, and the sending end and the receiving end need to be switched between sending and receiving.

[0048] The application simulates the GPIO on two low-cost chips into two-wire bus, defines corresponding bus communication rules, adopts data bit double clock cycle mechanism, guarantees data communication reliability, and makes it not affected by any interruption delay, so as to realize reliable communication between the two low-cost chips.

[0049] Although the specific embodiments of the present application are described above, those skilled in the art should understand that the specific embodiments described are only illustrative, and are not intended to limit the scope of the present application, and equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present application should be covered within the scope of the claims of the present application.

Claims

1. A low-cost, reliable inter-chip communication method, characterized in that: Includes the following steps: Step S1: Take two GPIOs from each of the two chips to simulate a two-wire bus. The two-wire bus includes a DATA line and a SYNC line. The DATA line is used for data transmission, and the SYNC line is used for triggering data transmission and acknowledging data reception. Step S2: Define a byte consisting of 9 bits, with the first bit being the start bit and the last eight bits being the data bits, and the start bit must be low. Step S3: Set two clock cycles for each data bit, including a transmit clock cycle and an acknowledge clock cycle. The transmit clock cycle is output by the transmitting end, and the acknowledge clock cycle is output by the receiving end, and both adopt a rising edge triggering mechanism. Step S4: When sending data, the sending end outputs a transmission clock cycle and waits for an acknowledgment clock cycle. After detecting the rising edge interrupt of the acknowledgment, it is considered that the receiving end has read the data and continues to send the next bit of data, thus sending data in a loop. Step S5: When receiving data, determine whether the first bit of the byte is low. If so, read the DATA line level after receiving the rising edge interrupt of SYNC, obtain the data bit data, output the acknowledgment clock, and repeat this process until all data bits are received. Otherwise, exit directly without outputting an acknowledgment clock; Step S4 specifically includes: Step S41: Before sending data, first check whether the bus is idle and whether the SYNC line is high. If either condition is not met, it means that the other end has initiated data communication and data cannot be sent, so the process ends. If both conditions are met, it means that the bus is idle and data transmission begins. Step S42: When sending data, disable the interrupt function of the SYNC line, output a low level, and switch the DATA line to the output state. Step S43: Send the start bit, the SYNC line outputs a low level, the DATA line outputs a low level, and delays for a specific time; Step S44: Prepare the output transmission clock cycle, disable CPU interrupts, configure the SYNC line as an input, and the SYNC line will gradually become high. Delay for a specific time to wait for the SYNC line to become high completely. At this time, enable the rising edge interrupt of the SYNC line, enable CPU interrupts, and wait for the rising edge interrupt of the SYNC line to be triggered. After the rising edge interrupt of the SYNC line is detected, it means that the other party has received this bit of data. At the same time, disable the SYNC line interrupt, delay for a specific time, and then repeat this process to send data bits until all data bits have been sent. Step S5 specifically includes: Step S51: When receiving data, the bus is usually in an idle state, and the SYNC line is in the enabled rising edge interrupt state. After detecting the rising edge interrupt of the SYNC line, if the bus was previously in an idle state, it will enter the receiving state. Step S52: If the first bit of a byte is received, determine whether it is low level. If it is, proceed to step S53; otherwise, exit directly and end the process. Step S53: After receiving the rising edge interrupt, read the DATA level, obtain the data bit, and prepare to output the acknowledge clock. First, disable the SYNC interrupt, configure SYNC to output low, delay for a specific time, keep SYNC low, then lock the CPU interrupt, configure SYNC to input, delay for a specific time so that SYNC rises to a sufficiently high level to enable the rising edge interrupt of SYNC, and at the same time enable the CPU interrupt. This completes the reception of one data bit. Repeat this process until all data bits are received. After the reception timeout, switch the bus state back to the idle state.

2. The method according to claim 1, characterized in that: On the DATA line, 1 is defined as high level and 0 as low level. On the SYNC line, 1 is defined as high level and 0 as low level.

3. The method according to claim 1, characterized in that: The DATA line and SYNC line are each externally equipped with a pull-up resistor, so that when the idle state is reached, the external resistor is pulled high, the DATA line and SYNC line are both at a high level, and the GPIO at both ends of the chip are in the input state.

4. The method according to claim 1, characterized in that: The DATA line is unidirectional, with the transmitting end providing push-pull output and the receiving end providing input. The SYNC line is bidirectional, requiring the transmitting and receiving ends to continuously switch between transmitting and receiving.

5. The method according to claim 1, characterized in that: The two chips are two SoCs, and the two SoCs adopt any combination of WIFI SoC and Bluetooth SoC, WIFI SoC and WIFI SoC, and Bluetooth SoC and Bluetooth SoC.

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