A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors.The semiconductor device comprises a substrate, an epitaxial layer on the surface of the substrate, a gate oxide layer on the side of the epitaxial layer away from the substrate, a first doped polysilicon layer on the side of the gate oxide layer away from the substrate, a second doped polysilicon layer on the side of the first doped polysilicon layer away from the substrate, a third doped polysilicon layer on the side of the second doped polysilicon layer away from the substrate, and the doping elements in the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer comprise phosphorus, the gate oxide layer comprises doping elements, and the doping elements comprise phosphorus; wherein the doping concentration of phosphorus elements in the second doped polysilicon layer is greater than the doping concentration of phosphorus elements in the third doped polysilicon layer.The semiconductor device and the manufacturing method thereof provided by the application have the effect of growing the polysilicon layer at a faster rate.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Silicon carbide, as an important third-generation semiconductor material, has advantages such as high bandgap, high critical breakdown electric field, and high thermal conductivity. Therefore, silicon carbide power devices have advantages such as higher breakdown voltage, faster switching speed, and higher operating temperature compared with traditional silicon-based power devices, and have very broad application prospects in new energy vehicles, photovoltaic power generation, electric vehicle traction and other fields.

[0003] The polysilicon layer is an important component of SiC MOSFET devices, mainly serving to connect the gate oxide layer and the gate metal. Growing a high-quality doped polysilicon layer is the foundation for fabricating high-performance power devices.

[0004] However, existing technologies suffer from the problem of slow growth rate of polysilicon layers in SiC MOSFET devices. Summary of the Invention

[0005] The purpose of this application is to provide a semiconductor device and a method for fabricating the same, in order to solve the problem of slow growth rate of polysilicon layer in SiC MOSFET devices in the prior art.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0007] In a first aspect, embodiments of this application provide a semiconductor device, the semiconductor device comprising:

[0008] Substrate;

[0009] The epitaxial layer located on the surface of the substrate;

[0010] The gate oxide layer located on the side of the epitaxial layer away from the substrate;

[0011] A first doped polysilicon layer located on the side of the gate oxide layer away from the substrate;

[0012] A second doped polysilicon layer located on the side of the first doped polysilicon layer away from the substrate; a third doped polysilicon layer located on the side of the second doped polysilicon layer away from the substrate;

[0013] The doping element in the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer includes phosphorus, and the gate oxide layer includes a doping element, which includes phosphorus.

[0014] The phosphorus doping concentration in the second doped polycrystalline silicon layer is greater than that in the third doped polycrystalline silicon layer.

[0015] Optionally, the thickness of the third doped polysilicon layer is greater than the thickness of the second doped polysilicon layer.

[0016] Optionally, the thickness of the first doped polysilicon layer is 10~30 nm; and / or,

[0017] The thickness of the second doped polysilicon layer is 10~30 nm; and / or,

[0018] The thickness of the third doped polycrystalline silicon layer is 350nm-750nm.

[0019] Optionally, the phosphorus doping concentration in the second doped polysilicon layer is greater than the phosphorus doping concentration in the first doped polysilicon layer.

[0020] Optionally, along the direction from the third doped polysilicon layer to the gate oxide layer, the concentration of phosphorus doping in the first doped polysilicon layer gradually decreases.

[0021] Optionally, the gate oxide layer contains phosphorus at the interface between the gate oxide layer and the epitaxial layer, and the epitaxial layer is a silicon carbide epitaxial layer.

[0022] Optionally, the thickness of the gate oxide layer is 40nm-60nm.

[0023] Optionally, the phosphorus doping concentration in the gate oxide layer is 5E15 / cm³. 2 ~1E17 / cm 2 ; and / or, the phosphorus doping concentration in the first doped polycrystalline silicon layer is 1E17 / cm³. 2 ~1E18 / cm 2 ; and / or,

[0024] The phosphorus doping concentration in the second doped polycrystalline silicon layer is 1E20 / cm³. 2 ~1E21 / cm 2 ; and / or,

[0025] The phosphorus doping concentration in the third doped polycrystalline silicon layer is 1E18 / cm³. 2 ~1E20 / cm 2 .

[0026] Optionally, the doping elements in the gate oxide layer, the first doped polysilicon layer, the second doped polysilicon layer, and the third doped polysilicon layer include phosphorus and nitrogen.

[0027] Optionally, the doping elements in the gate oxide layer, the first doped polysilicon layer, the second doped polysilicon layer, and the third doped polysilicon layer are phosphorus and nitrogen.

[0028] Secondly, embodiments of this application also provide a semiconductor device, the semiconductor device comprising:

[0029] Substrate;

[0030] The epitaxial layer located on the surface of the substrate;

[0031] A gate oxide layer located on the side of the epitaxial layer away from the substrate, the gate oxide layer comprising a doping element, the doping element being phosphorus;

[0032] A polycrystalline silicon layer located on the side of the gate oxide layer away from the substrate;

[0033] A first sub-polycrystalline silicon layer located on the side of the polycrystalline silicon layer away from the substrate and a second sub-polycrystalline silicon layer located on the side of the first sub-polycrystalline silicon layer away from the substrate, wherein the first sub-polycrystalline silicon layer and the second sub-polycrystalline silicon layer include doping elements, wherein the doping elements include phosphorus;

[0034] The doping concentration of the first sub-polysilicon layer is greater than that of the second sub-polysilicon layer.

[0035] Optionally, the thickness of the second sub-polysilicon layer is greater than the thickness of the first sub-polysilicon layer.

[0036] Optionally, the gate oxide layer contains phosphorus at the interface between the gate oxide layer and the epitaxial layer, and the epitaxial layer is silicon carbide.

[0037] Optionally, the thickness of the gate oxide layer is 40nm-60nm. Thirdly, embodiments of this application also provide a semiconductor device, the semiconductor device comprising:

[0038] Substrate;

[0039] The epitaxial layer located on the surface of the substrate;

[0040] The gate oxide layer located on the side of the epitaxial layer away from the substrate;

[0041] The first doped polysilicon layer is located on the side of the oxide gate oxide layer away from the substrate;

[0042] A second doped polysilicon layer located on the side of the first doped polysilicon layer away from the substrate;

[0043] A third doped polysilicon layer located on the side of the second doped polysilicon layer away from the substrate;

[0044] The doping element in the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer includes phosphorus, and the gate oxide layer includes a doping element, which includes phosphorus.

[0045] The thickness of the third doped polysilicon layer is greater than the thickness of the second doped polysilicon layer.

[0046] Optionally, the second doped polycrystalline silicon layer is fabricated using an in-situ doping process.

[0047] Optionally, the phosphorus doping concentration in the second doped polycrystalline silicon layer is greater than the phosphorus doping concentration in the third doped polycrystalline silicon layer.

[0048] Optionally, the thickness of the first doped polysilicon layer is 10~30 nm; and / or,

[0049] The thickness of the second doped polysilicon layer is 10~30 nm; and / or,

[0050] The thickness of the third doped polycrystalline silicon layer is 350nm-750nm.

[0051] Optionally, the phosphorus doping concentration in the second doped polysilicon layer is greater than the phosphorus doping concentration in the first doped polysilicon layer.

[0052] Optionally, along the direction from the third doped polysilicon layer to the gate oxide layer, the concentration of phosphorus doping in the first doped polysilicon layer gradually decreases.

[0053] Optionally, the gate oxide layer contains phosphorus at the interface between the gate oxide layer and the epitaxial layer, and the epitaxial layer is silicon carbide.

[0054] Optionally, the thickness of the gate oxide layer is 40nm-60nm.

[0055] Fourthly, embodiments of this application also provide a method for fabricating a semiconductor device, the method comprising the following steps:

[0056] Provide a substrate;

[0057] An epitaxial layer is formed on the substrate;

[0058] A gate oxide layer is formed on the epitaxial layer;

[0059] An intrinsic polysilicon gate layer is formed on the gate oxide layer;

[0060] A second doped polysilicon layer is formed on the intrinsic polysilicon gate layer;

[0061] A third doped polysilicon layer is formed on the second polysilicon layer; wherein the doping element in the second doped polysilicon layer and the third doped polysilicon layer includes phosphorus, and the doping concentration of phosphorus in the second doped polysilicon layer is greater than the doping concentration of phosphorus in the third doped polysilicon layer.

[0062] Optionally, the second doped polysilicon layer is formed on the intrinsic polysilicon gate layer using an in-situ doping process; and / or,

[0063] A third doped polysilicon layer is formed on the second doped polysilicon layer using an in-situ doping process.

[0064] Optionally, after the step of forming a third doped polysilicon layer on the second doped polysilicon layer, the method further includes:

[0065] The phosphorus element in the second doped polysilicon layer is diffused into the intrinsic polysilicon gate layer and the gate oxide layer using an annealing process.

[0066] Optionally, the gate oxide layer is formed on the epitaxial layer using a wet oxidation process.

[0067] Compared with the prior art, the embodiments of this application have the following beneficial effects:

[0068] This application provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; an epitaxial layer on the surface of the substrate; a gate oxide layer on the side of the epitaxial layer away from the substrate; a first doped polysilicon layer on the side of the gate oxide layer away from the substrate; a second doped polysilicon layer on the side of the first doped polysilicon layer away from the substrate; and a third doped polysilicon layer on the side of the second doped polysilicon layer away from the substrate. The doping element in the first, second, and third doped polysilicon layers includes phosphorus, and the gate oxide layer also includes a doping element, which includes phosphorus. The phosphorus doping concentration in the second doped polysilicon layer is greater than that in the third doped polysilicon layer. Because the semiconductor device provided in this application includes multiple doped polysilicon layers, and the phosphorus doping concentration in the second doped polysilicon layer is greater than that in the third doped polysilicon layer, the growth rate of the polysilicon can be significantly increased when doping the third doped polysilicon layer, while ensuring that the doping concentration meets the requirements. Attached Figure Description

[0069] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0070] Figure 1 This is a schematic diagram of the hierarchical structure of semiconductor devices in the prior art.

[0071] Figure 2 This is a first exemplary flowchart of a semiconductor device fabrication method provided in an embodiment of this application.

[0072] Figure 3 The hierarchical structure diagram corresponding to S104 provided in the embodiments of this application.

[0073] Figure 4 The hierarchical structure diagram corresponding to S106 provided in the embodiments of this application.

[0074] Figure 5 The hierarchical structure diagram corresponding to S108 provided in the embodiments of this application.

[0075] Figure 6 The hierarchical structure diagram corresponding to S112 provided in the embodiments of this application.

[0076] Figure 7 This is a second exemplary flowchart of a semiconductor device fabrication method provided in an embodiment of this application.

[0077] Figure 8 This is a hierarchical structure diagram after annealing provided in an embodiment of this application.

[0078] In the picture:

[0079] 110 - Substrate; 120 - Epitaxial layer; 130 - Gate oxide layer; 140 - Intrinsic polysilicon gate layer; 151 - First doped polysilicon layer; 152 - Second doped polysilicon layer; 153 - Third doped polysilicon layer. Detailed Implementation

[0080] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0081] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0082] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0083] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0084] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0085] As described in the background section, the polysilicon layer is a crucial component of SiC MOSFET devices, primarily serving to connect the gate oxide layer and the gate metal. However, the sheet resistance of the polysilicon layer severely limits the switching speed of the power device, thus preventing the full utilization of the high-frequency characteristics of silicon carbide devices.

[0086] Figure 1 The diagram shows a schematic of the layer structure of an existing MOSFET device, in which the substrate, epitaxial layer, gate oxide layer and polysilicon layer are connected layer by layer. Of course, other layer structures, such as the gate metal layer, are also connected on the polysilicon layer, which will not be described in detail here.

[0087] based on Figure 1 Given the hierarchical structure, existing technologies mainly employ the following two methods to reduce the sheet resistance of polysilicon:

[0088] The first method involves growing intrinsic polysilicon on the surface of the gate oxide layer, and then doping it with impurity elements, such as P or B, through ion implantation or furnace tube annealing. However, this process can cause uneven sheet resistance of the polysilicon and also increases production costs.

[0089] The second method involves growing polycrystalline silicon on the surface of the gate oxide layer through in-situ doping. In-situ doped polycrystalline silicon refers to introducing a gas containing impurities, such as PH3 or B2H6, during polycrystalline silicon deposition to ensure uniform doping. This process results in more uniform polycrystalline silicon doping, is simpler, and has lower costs. However, because PH3 or B2H6 has a stronger adsorption effect on the surface than SiH4, the growth rate is slower, and the uniformity of the film thickness is worse than that of intrinsic polycrystalline silicon.

[0090] In summary, the existing technology suffers from the problem of slow growth rate of polysilicon layers in SiC MOSFET devices.

[0091] In view of this, in order to solve the above problems, this application provides a method for manufacturing a semiconductor device, which first grows a thin layer of intrinsic polycrystalline silicon to change the surface properties, and then grows polycrystalline silicon through an in-situ doping process to improve the overall growth rate of polycrystalline silicon.

[0092] The semiconductor device fabrication method provided in this application is illustrated below:

[0093] As an optional implementation, please refer to Figure 2 The semiconductor device fabrication method provided in this application includes:

[0094] S102 provides a substrate;

[0095] S104 forms an epitaxial layer on the substrate.

[0096] S106 forms a gate oxide layer on the epitaxial layer.

[0097] S108 forms an intrinsic polysilicon gate layer on the gate oxide layer.

[0098] S110, a second doped polysilicon layer is formed on the intrinsic polysilicon gate layer.

[0099] S112, a third doped polysilicon layer is formed on the second polysilicon layer; wherein the doping elements in the second and third doped polysilicon layers include phosphorus, and the doping concentration of phosphorus in the second doped polysilicon layer is greater than the doping concentration of phosphorus in the third doped polysilicon layer.

[0100] The term "forming layer B on layer A" means that layer A includes two sides, namely the front side and the back side, with the back side facing the substrate and the front side facing the opposite direction of the substrate, and layer B is connected to the front side of layer A.

[0101] For example, combining Figure 1For an oxide layer, with its back side facing the substrate and connected to the epitaxial layer, and its front side facing the opposite direction of the substrate and connected to the polysilicon layer, it can be described by the term "growing polysilicon based on the side of the gate oxide layer away from the substrate".

[0102] This approach achieves several advantages. First, by first growing a thin intrinsic polysilicon layer during the growth of the doped polysilicon layer, the surface properties are altered, thus increasing the growth rate of the in-situ doped polysilicon. Furthermore, since the first polysilicon layer is thinner than the doped polysilicon layer, the growth rate of the polysilicon layer is strongly correlated with the growth rate of the doped polysilicon layer; therefore, increasing the growth rate of the doped polysilicon layer improves the overall growth rate of the polysilicon layer. Second, this application still employs an in-situ doping process to grow the doped polysilicon layer, resulting in better uniformity of polysilicon doping and lower costs.

[0103] This application does not limit the materials of the substrate 110 and the epitaxial layer 120. For example, the substrate 110 can be a SiC substrate 110, a Si substrate 110, a sapphire substrate 110, etc., and the epitaxial layer 120 can be homoepitaxial or heteroepitaxial. For example, the epitaxial layer 120 can be SiC epitaxial. The structure after growing the epitaxial layer 120 is as follows. Figure 3 As shown. Since epitaxial growth technology is relatively mature, the epitaxial growth process will not be described in detail. For example, vapor phase epitaxy can be used to grow epitaxial layer 120.

[0104] After growing the epitaxial layer 120 to the target thickness, please refer to... Figure 4 A gate oxide layer 130 needs to be grown on the surface of the epitaxial layer 120. Optionally, in order to remove impurities on the surface of the epitaxial layer 120, a standard RCA cleaning process needs to be performed on the epitaxial layer 120 after its growth. Furthermore, the gate oxide layer 130 provided in this application is a gate oxide, which can be a SiO2 gate oxide layer.

[0105] Based on this, as one implementation method, when growing the gate oxide layer 130, it can be thermally oxidized at a high temperature of 1300℃, then annealed at 1250℃ in a nitrogen-doped atmosphere for 30 min, and then annealed in an argon or other inert gas atmosphere for 90 min to form the SiO2 gate oxide layer 130. The nitrogen-doped atmosphere includes, but is not limited to, nitrogen, nitric oxide, or nitrous oxide, and the thickness of the gate oxide layer 130 ranges from 40 nm to 60 nm.

[0106] As another method, SiO2 gate oxide layer 130 can be formed by oxidizing with moist oxygen (e.g., water vapor) at a high temperature of 950℃-1100℃ for 90 minutes, followed by annealing at 1250℃ in a nitrogen-doped atmosphere for 30 minutes, and then annealing in an inert gas atmosphere such as argon for 90 minutes. Of course, the nitrogen-doped atmosphere includes, but is not limited to, nitrogen, nitric oxide, or nitrous oxide, with a thickness ranging from 40nm to 60nm. The SiO2 dielectric film formed by moist oxygen oxidation is relatively loose compared to that formed by high-temperature hot oxygen oxidation, which is more conducive to the diffusion of nitrogen or phosphorus elements.

[0107] Please see Figure 5 After growing the gate oxide layer 130, intrinsic polysilicon is grown on the surface of the gate oxide layer 130 to form an intrinsic polysilicon gate layer 140. This application does not limit the growth process of the intrinsic polysilicon gate layer 140. For example, an undoped and relatively thin intrinsic polysilicon layer can be grown at a high temperature of 620°C using LPCVD (Low Pressure Chemical Vapor Deposition). Of course, other processes can also be used to grow the intrinsic polysilicon gate layer 140, such as CVD or molecular beam epitaxy, and are not limited here.

[0108] By growing an intrinsic polysilicon gate layer on a silicon oxide layer, the surface properties can be changed through the intrinsic polysilicon gate layer. This can then increase the growth rate of in-situ doped polysilicon during the growth of the doped polysilicon layer, thus significantly improving the growth rate of the doped polysilicon layer.

[0109] To ensure that the intrinsic polysilicon gate layer 140 does not affect the growth rate and the performance of the device, the thickness of the intrinsic polysilicon gate layer 140 needs to be relatively thin. Optionally, the thickness of the intrinsic polysilicon gate layer 140 is in the range of 10~30nm.

[0110] Of course, in an alternative implementation, after the intrinsic polysilicon gate layer 140 is grown, impurity elements can be implanted through an ion implantation process to form doped polysilicon, for example, implanting P or B elements, and then growing the doped polysilicon layer.

[0111] For further information on improving the growth rate of doped polysilicon layers, please refer to [link / reference needed]. Figure 6 The doped polysilicon layer includes a second doped polysilicon layer 152 and a third doped polysilicon layer 153, and the doping concentration of the second doped polysilicon layer 152 is greater than the doping concentration of the third doped polysilicon layer 153.

[0112] The impurity source for doping can be a P-source or a B-source, or other impurity sources, which are not limited here. Taking the P-source as an example, PH3 can be used as the P-source. Based on this, a second doped polycrystalline silicon layer 152 can be deposited in situ at 620℃ by LPCVD with PH3 doping. The gas atmosphere is a mixture of SiH4, PH3 and N2, with a flow ratio of SiH4 to PH3 of 2:1, so that the phosphorus doping concentration reaches 3E20cm-1 to 1E21cm-1 and the resistivity reaches 5E-4Ω·cm to 1E-3Ω·cm.

[0113] Of course, the process can also employ CVD, molecular beam epitaxy, or other techniques; there are no limitations on this. Similarly, other gases can be used, such as inert gases; there are no restrictions on this either.

[0114] It should be noted that, in order to meet the requirements of the diffusion process and further improve the growth rate of the polysilicon layer, the thickness of the second doped polysilicon layer 152 is relatively thin. Optionally, the thickness of the second doped polysilicon layer is in the range of 10~30nm.

[0115] After growing the second doped polysilicon layer 152, the flow rate of PH3 can be reduced, and the third doped polysilicon layer 153 can be deposited by in-situ PH3 doping at 620℃ using LPCVD. By reducing the PH3 flow rate, the competition between surface PH3 and SiH4 can be reduced, thereby further improving the growth rate.

[0116] In this application, the specific value of reducing the flow rate of PH3 is not limited. For example, when growing the second doped polysilicon layer 152, the flow rate ratio of SiH4 to PH3 is 2:1, while when growing the third doped polysilicon layer 153, the flow rate ratio of SiH4 to PH3 is 4:1, thereby reducing the flow rate of PH3.

[0117] Optionally, the sum of the thicknesses of the intrinsic polysilicon gate layer 140 and the doped polysilicon layer (i.e., 1 including the first doped polysilicon layer and the second doped polysilicon layer) is 400~800nm. Based on this, since the thicknesses of the intrinsic polysilicon gate layer 140 and the second doped polysilicon layer 152 are relatively thin, the thickness of the third doped polysilicon layer 153 is relatively large. By increasing the growth rate of the third doped polysilicon layer 153, the growth rate of the entire polysilicon layer can be significantly increased.

[0118] For example, consider a polysilicon layer with a total thickness of 400 nm, an intrinsic polysilicon gate layer 140 with a thickness of 30 nm, a second doped polysilicon layer 152 with a thickness of 30 nm, and a third doped polysilicon layer 153 with a thickness of 340 nm. Since the intrinsic polysilicon gate layer 140 is fabricated using conventional processes, its growth rate is relatively low, consistent with the growth rate of polysilicon layers in existing technologies. However, during the growth of the second doped polysilicon layer 152, the surface properties are altered by the intrinsic polysilicon gate layer 140, thus improving the growth efficiency of the second doped polysilicon layer 152. During the growth of the third doped polysilicon layer 153, the growth rate is maximized by altering the surface properties and reducing the pH3 flow rate. Therefore, the thickest third doped polysilicon layer 153 is grown at the fastest growth rate, minimizing the growth time for all three layers and improving the overall growth rate of the polysilicon layer.

[0119] Following S112, to improve the performance of semiconductor devices, please refer to [link / reference needed]. Figure 7 The manufacturing method also includes:

[0120] S112 is used to anneal the semiconductor device to allow impurity elements to diffuse into the gate oxide layer.

[0121] In this process, high-temperature annealing can push the dopant elements in the second doped polysilicon layer 152 to the interface between the gate oxide layer 130 and the epitaxial layer 120. For example, when the dopant element is P, the annealing process pushes the P element into the gate oxide layer 130 and accumulates at the interface between the gate oxide layer 130 and the epitaxial layer 120, thereby improving the channel mobility and performance of the semiconductor device. The structure after annealing is as follows: Figure 8 As shown.

[0122] One implementation method is to anneal the semiconductor device at a high temperature of 1000℃ for 90 minutes. It should be noted that when the gate oxide layer 130 is fabricated using wet oxidation, wet oxidation is more conducive to the diffusion of nitrogen or phosphorus elements. Furthermore, the high-temperature annealing process can further reduce defects in the wet oxidation process, thereby improving the gate oxide quality.

[0123] Furthermore, it should be noted that since the intrinsic polysilicon gate layer 140 is made of intrinsic polysilicon, and the doping concentration of the second doped polysilicon layer 152 is greater than that of the third doped polysilicon layer 153, the barrier distribution of the entire polysilicon layer is first raised and then lowered. This barrier distribution is more conducive to the diffusion of impurity elements, and can push more impurity elements to the interface between the gate oxide layer 130 and the epitaxial layer 120, thereby improving the channel mobility of the device.

[0124] Based on the above implementation method, please refer to Figure 6 This application also provides a semiconductor device, characterized in that the semiconductor device includes a substrate; an epitaxial layer located on the surface of the substrate; a gate oxide layer located on the side of the epitaxial layer away from the substrate, the gate oxide layer including a doping element, the doping element including phosphorus; a polysilicon layer located on the side of the gate oxide layer away from the substrate; a first sub-polysilicon layer located on the side of the polysilicon layer away from the substrate and a second sub-polysilicon layer located on the side of the first sub-polysilicon layer away from the substrate, the first sub-polysilicon layer and the second sub-polysilicon layer including a doping element, the doping element including phosphorus; wherein the doping concentration of the first sub-polysilicon layer is greater than the doping concentration of the second sub-polysilicon layer.

[0125] Optionally, the thickness of the second sub-polysilicon layer is greater than the thickness of the first sub-polysilicon layer.

[0126] Optionally, the gate oxide layer contains phosphorus at the interface between the gate oxide layer and the epitaxial layer, and the epitaxial layer is silicon carbide.

[0127] Optionally, the thickness of the gate oxide layer is 40nm-60nm.

[0128] As another implementation, embodiments of this application also provide another semiconductor device, which includes: a substrate; an epitaxial layer located on the surface of the substrate; a gate oxide layer located on the side of the epitaxial layer away from the substrate; a first doped polysilicon layer located on the side of the gate oxide layer away from the substrate; a second doped polysilicon layer located on the side of the first doped polysilicon layer away from the substrate; and a third doped polysilicon layer located on the side of the second doped polysilicon layer away from the substrate. The doping element in the first doped polysilicon layer, the second doped polysilicon layer, and the third doped polysilicon layer includes phosphorus, and the gate oxide layer includes a doping element, which includes phosphorus. The phosphorus doping concentration in the second doped polysilicon layer is greater than the phosphorus doping concentration in the third doped polysilicon layer.

[0129] Optionally, the thickness of the third doped polysilicon layer is greater than the thickness of the second doped polysilicon layer.

[0130] Optionally, the thickness of the first doped polysilicon layer is 10~30nm; and / or, the thickness of the second doped polysilicon layer is 10~30nm; and / or, the thickness of the third doped polysilicon layer is 350nm-750nm.

[0131] Optionally, the phosphorus doping concentration in the second doped polycrystalline silicon layer is greater than the phosphorus doping concentration in the first doped polycrystalline silicon layer.

[0132] Furthermore, along the direction from the third doped polysilicon layer to the gate oxide layer, the phosphorus doping concentration gradually decreases in the first doped polysilicon layer. Phosphorus is present at the interface between the gate oxide layer and the epitaxial layer, which is a silicon carbide epitaxial layer. The gate oxide layer has a thickness of 40nm-60nm. The phosphorus doping concentration in the gate oxide layer is 5E15 / cm³. 2 ~1E17 / cm 2 ; and / or, the phosphorus doping concentration in the first doped polycrystalline silicon layer is 1E17 / cm³. 2 ~1E18 / cm 2 ; and / or, the phosphorus doping concentration in the second doped polysilicon layer is 1E20 / cm³. 2 ~1E21 / cm 2 ; and / or, the phosphorus doping concentration in the third doped polysilicon layer is 1E18 / cm³. 2 ~1E20 / cm 2 Since the intrinsic polysilicon gate layer 140 is intrinsic polysilicon, its surface properties can be altered to increase the growth rate of in-situ doped polysilicon. Naturally, an in-situ doping process is also used to form the third doped polysilicon layer on the second doped polysilicon layer.

[0133] Optionally, the doped polysilicon layer includes a second doped polysilicon layer 152 located on the side of the intrinsic polysilicon gate layer 140 away from the substrate 110; and a third doped polysilicon layer 153 located on the side of the second doped polysilicon layer 152 away from the substrate 110; wherein the doping concentration of the second doped polysilicon layer 152 is greater than the doping concentration of the third doped polysilicon layer 153.

[0134] By setting a second doped polysilicon layer 152 and a third doped polysilicon layer 153, the flow rate of the impurity source in the third doped polysilicon layer 153 can be reduced during the fabrication process, thereby increasing the growth rate.

[0135] Optionally, the thickness of the second doped polysilicon layer 152 is 10~30nm, the thickness of the intrinsic polysilicon gate layer 140 is 10~30nm, and the sum of the thicknesses of the intrinsic polysilicon gate layer 140 and the doped polysilicon layer is 400~800nm.

[0136] By setting the thickness as described above, the intrinsic polysilicon gate layer 140 and the second doped polysilicon layer 152 are relatively thin, while the third doped polysilicon layer 153 is thicker, and the growth rate of the third doped polysilicon layer 153 is the fastest, thus improving the overall growth rate of the polysilicon layer.

[0137] In summary, this application provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; an epitaxial layer on the surface of the substrate; a gate oxide layer on the side of the epitaxial layer away from the substrate; a first doped polysilicon layer on the side of the gate oxide layer away from the substrate; a second doped polysilicon layer on the side of the first doped polysilicon layer away from the substrate; and a third doped polysilicon layer on the side of the second doped polysilicon layer away from the substrate. The doping element in the first, second, and third doped polysilicon layers includes phosphorus, and the gate oxide layer also includes a doping element, which includes phosphorus. The phosphorus doping concentration in the second doped polysilicon layer is greater than that in the third doped polysilicon layer. Because the semiconductor device provided in this application includes multiple doped polysilicon layers, and the phosphorus doping concentration in the second doped polysilicon layer is greater than that in the third doped polysilicon layer, the growth rate of the polysilicon can be significantly increased when doping the third doped polysilicon layer, while ensuring that the doping concentration meets the requirements.

[0138] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0139] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate; an epitaxial layer on a surface of the substrate; a gate oxide layer on a side of the epitaxial layer away from the substrate; a first doped polysilicon layer on a side of the gate oxide layer away from the substrate; a second doped polysilicon layer on a side of the first doped polysilicon layer away from the substrate; and a third doped polysilicon layer on a side of the second doped polysilicon layer away from the substrate; the doping elements in the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer comprise phosphorus, and the gate oxide layer comprises doping elements, which comprise phosphorus; the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer are formed by annealing a three-layer polysilicon layer, a first layer of the three-layer polysilicon layer is a doped polysilicon layer formed on the gate oxide layer and formed by ion implantation doping of an intrinsic polysilicon layer, a second layer of the three-layer polysilicon layer is an in-situ doped polysilicon layer formed on the first layer of the three-layer polysilicon layer, and a third layer of the three-layer polysilicon layer is an in-situ doped polysilicon layer formed on the second layer of the three-layer polysilicon layer; 2. The semiconductor device of claim 1, wherein, wherein the doping concentration of phosphorus in the second doped polysilicon layer is greater than the doping concentration of phosphorus in the third doped polysilicon layer.

3. The semiconductor device of claim 2, wherein, The thickness of the third doped polysilicon layer is greater than the thickness of the second doped polysilicon layer. The thickness of the first doped polysilicon layer is 10-30 nm; and / or The thickness of the second doped polysilicon layer is 10-30 nm; and / or 4. The semiconductor device according to claim 1 or 2, wherein The thickness of the third doped polysilicon layer is 350-750 nm.

5. The semiconductor device of claim 4, wherein, The doping concentration of phosphorus in the second doped polysilicon layer is greater than the doping concentration of phosphorus in the first doped polysilicon layer.

6. The semiconductor device of claim 4, wherein, In the direction from the third doped polysilicon layer to the gate oxide layer, the doping concentration of phosphorus in the first doped polysilicon layer gradually decreases.

7. The semiconductor device of claim 6, wherein, The gate oxide layer contains phosphorus at the interface between the gate oxide layer and the epitaxial layer, and the material of the epitaxial layer is silicon carbide.

8. The semiconductor device according to claim 1 or 2, wherein The doping concentration of phosphorus element in the gate oxide layer is 5E15 / cm 2 1E17 / cm 2 ; and / or, a doping concentration of phosphorus elements in the first doped polysilicon layer is 1E17 / cm 2 1E18 / cm 2 ; and / or, The doping concentration of phosphorus element in the second doped polysilicon layer is 1E20 / cm 2 1E21 / cm 2 ; and / or, The doping concentration of phosphorus element in the third doped polysilicon layer is 1E18 / cm 2 1E20 / cm 2 .

9. The semiconductor device of claim 1, wherein, The thickness of the gate oxide layer is 40-60 nm.

10. The semiconductor device of claim 9, wherein, The doping elements in the gate oxide layer, the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer comprise phosphorus and nitrogen.

11. A semiconductor device, characterized by comprising: The doping elements in the gate oxide layer, the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer are phosphorus and nitrogen. The semiconductor device comprises: a substrate; an epitaxial layer on a surface of the substrate; a gate oxide layer on a side of the epitaxial layer away from the substrate, the gate oxide layer comprising doping elements, which comprise phosphorus; a polysilicon layer on a side of the gate oxide layer away from the substrate; a first sub-polysilicon layer on a side of the polysilicon layer away from the substrate and a second sub-polysilicon layer on a side of the first sub-polysilicon layer away from the substrate, the first sub-polysilicon layer and the second sub-polysilicon layer comprising doping elements, which comprise phosphorus; wherein the doping concentration of the first sub-polysilicon layer is greater than the doping concentration of the second sub-polysilicon layer. The polycrystalline silicon layer, the first sub-polycrystalline silicon layer and the second sub-polycrystalline silicon layer are formed by annealing a three-layer polycrystalline silicon layer, a first layer of the three-layer polycrystalline silicon layer is an intrinsic polycrystalline silicon layer formed on the gate oxide layer, a second layer of the three-layer polycrystalline silicon layer is an in-situ doped polycrystalline silicon layer formed on the first layer of the three-layer polycrystalline silicon layer, and a third layer of the three-layer polycrystalline silicon layer is an in-situ doped polycrystalline silicon layer formed on the second layer of the three-layer polycrystalline silicon layer.

12. The semiconductor device of claim 11, wherein, The thickness of the second sub-polycrystalline silicon layer is greater than the thickness of the first sub-polycrystalline silicon layer.

13. The semiconductor device according to claim 11 or 12, wherein The gate oxide layer contains phosphorus at an interface between the gate oxide layer and an epitaxial layer, and the epitaxial layer is silicon carbide.

14. The semiconductor device of claim 11, wherein, The thickness of the gate oxide layer is 40-60 nm.

15. A semiconductor device, characterized by comprising: The semiconductor device comprises: a substrate; an epitaxial layer on a surface of the substrate; a gate oxide layer on a side of the epitaxial layer away from the substrate; a first doped polycrystalline silicon layer on a side of the gate oxide layer away from the substrate; a second doped polycrystalline silicon layer on a side of the first doped polycrystalline silicon layer away from the substrate; a third doped polycrystalline silicon layer on a side of the second doped polycrystalline silicon layer away from the substrate; the doping elements in the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer and the third doped polycrystalline silicon layer include phosphorus, and the gate oxide layer contains the doping elements including phosphorus; the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer and the third doped polycrystalline silicon layer are formed by annealing a three-layer polycrystalline silicon layer, a first layer of the three-layer polycrystalline silicon layer is an intrinsic polycrystalline silicon layer formed on the gate oxide layer or a doped polycrystalline silicon layer formed on the gate oxide layer and formed by ion implantation doping of the intrinsic polycrystalline silicon layer, a second layer of the three-layer polycrystalline silicon layer is an in-situ doped polycrystalline silicon layer formed on the first layer of the three-layer polycrystalline silicon layer, and a third layer of the three-layer polycrystalline silicon layer is an in-situ doped polycrystalline silicon layer formed on the second layer of the three-layer polycrystalline silicon layer; wherein the thickness of the third doped polycrystalline silicon layer is greater than the thickness of the second doped polycrystalline silicon layer.

16. The semiconductor device of claim 15, wherein, The doping concentration of phosphorus in the second doped polycrystalline silicon layer is greater than the doping concentration of phosphorus in the third doped polycrystalline silicon layer.

17. The semiconductor device of claim 15, wherein, The thickness of the first doped polycrystalline silicon layer is 10-30 nm; and / or The thickness of the second doped polycrystalline silicon layer is 10-30 nm; and / or The thickness of the third doped polycrystalline silicon layer is 350-750 nm.

18. The semiconductor device of claim 15 or 16, wherein, The doping concentration of phosphorus in the second doped polycrystalline silicon layer is greater than the doping concentration of phosphorus in the first doped polycrystalline silicon layer.

19. The semiconductor device of claim 18, wherein, In the direction from the third doped polycrystalline silicon layer to the gate oxide layer, the concentration of phosphorus doping in the first doped polycrystalline silicon layer gradually decreases.

20. The semiconductor device of claim 15, wherein, The gate oxide layer contains phosphorus at an interface between the gate oxide layer and an epitaxial layer, and the epitaxial layer is silicon carbide.

21. The semiconductor device of claim 20, wherein, The thickness of the gate oxide layer is 40-60 nm.

22. A method of fabricating a semiconductor device, the method comprising: The method comprises the following steps: providing a substrate; forming an epitaxial layer on the substrate; forming a gate oxide layer on the epitaxial layer; forming an intrinsic polycrystalline silicon gate layer on the gate oxide layer; forming a second doped polysilicon layer on the intrinsic polysilicon gate layer by using an in-situ doping process; forming a third doped polysilicon layer on the second doped polysilicon layer by using an in-situ doping process; wherein the doping elements in the second doped polysilicon layer and the third doped polysilicon layer include phosphorus, and the doping concentration of phosphorus in the second doped polysilicon layer is greater than that in the third doped polysilicon layer; after the step of forming the third doped polysilicon layer on the second doped polysilicon layer, the method further comprises: diffusing the phosphorus in the second doped polysilicon layer into the intrinsic polysilicon gate layer and the gate oxide layer by using an annealing process.

23. The method for making a semiconductor device of claim 22, wherein, forming the gate oxide layer on the epitaxial layer by using a wet oxygen oxidation process.

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