A trench gate DMOS device with improved temperature characteristics

Abstract

The present application belongs to the technical field of power semiconductor, and relates to a trench gate MOSFET structure, which comprises a metallized drain, a heavily doped first-conductivity-type semiconductor substrate, a lightly doped first-conductivity-type semiconductor lightly doped epitaxial layer, a first-conductivity-type semiconductor heavily doped source region I, a first-conductivity-type semiconductor heavily doped source region II, an interlayer dielectric, a trench polysilicon gate electrode, a planar polysilicon gate electrode, a metal via, a gate oxide layer, a second-conductivity-type semiconductor heavily doped contact region, a longitudinal channel region, a lateral channel region and a second-conductivity-type semiconductor body region. The present application designs a lateral MOSFET inside the device without additional layout area and without deeper trench depth, which is connected in series with the longitudinal channel to extend the channel length, so that the influence of the mobility on the drain current will be significantly increased, and the device can enter the current negative temperature characteristic region earlier, thereby improving the reliability of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor devices, in particular to a trench gate DMOS device. BACKGROUND

[0002] Power semiconductor devices are semiconductor devices for power processing, which combine microelectronic technology and power electronic technology to form the basis and core of power electronic technology. Power DMOS plays an important role in the field of power conversion due to its fast switching speed, high input impedance, small loss, simple driving, good frequency characteristics and other advantages. Its development process is to continuously improve the withstand voltage and reduce the loss while maintaining its own advantages. The traditional DMOS device is a planar structure using double diffusion process, which is the first successful commercial application of power DMOS and plays a key role in promoting the development of power DMOS. However, the existence of the internal JFET region makes the on-resistance of the device larger, which is not desirable for the development of power devices, providing an opportunity for the development of trench gate power devices. Trench gate DMOS adopts U-shaped trench structure, the conductive channel is a longitudinal channel, the cell density is high, and the current handling capacity is large. Because the JFET region is eliminated in its structure, the device has low on-state loss and is widely used in low-voltage fields.

[0003] In the direction of low-voltage and ultra-low-voltage applications, with the continuous development and optimization of the process in recent years, the problem of small current temperature instability of power DMOS has gradually emerged. The working current of DMOS device under large current condition presents a negative temperature characteristic, while under small current condition it presents a positive temperature characteristic. This is because the temperature characteristic of mobility dominates under large current, while the temperature characteristic of threshold voltage dominates under small current. When the temperature characteristics of mobility and threshold voltage have opposite effects on current, the current point at which their effects cancel each other out is the zero temperature point of the device. When the drain current of DMOS is less than the zero temperature point, it presents a positive temperature characteristic, and when it is greater than the zero temperature point, it presents a negative temperature characteristic. Since the positive temperature characteristic of the drain current may cause the failure or even burning of the device, in order to make the thermal stability of the device better, it is desirable to make the zero temperature point of the device as small as possible. SUMMARY

[0004] The present application provides a trench gate DMOS device with improved temperature characteristics to significantly increase the influence of mobility on the drain current, improve the realization of a lower zero temperature point, make the device enter the current negative temperature characteristic region earlier, and improve the stability of low-voltage DMOS under small current.

[0005] To achieve the above-mentioned application purposes, the technical solutions of the present application are as follows:

[0006] A trench gate DMOS device with improved temperature characteristics, the device top is provided with a metal via 9, the longitudinal section through the device cell metal via 9 and parallel to the length of the metal via 9 is a BB1 section, the longitudinal section through the metal via 9 and perpendicular to the length of the metal via 9 and from one side of the cell to the other side is an AA1 section;

[0007] On the AA1 section, the device structure includes a metalized drain 1, a heavily doped first conductivity type semiconductor substrate 2 on the metalized drain 1, a lightly doped first conductivity type semiconductor lightly doped epitaxial layer 3 on the heavily doped first conductivity type semiconductor substrate 2, a second conductivity type semiconductor body region 14 on the top of the lightly doped first conductivity type semiconductor lightly doped epitaxial layer 3; the top of the lightly doped first conductivity type semiconductor lightly doped epitaxial layer 3 also has a trench, the trench is filled with a polysilicon gate electrode 7; the side of the trench is in contact with the second conductivity type semiconductor body region 14, the lower surface of the trench is lower than the lower surface of the second conductivity type semiconductor body region 14; the trench polysilicon gate electrode 7 is electrically isolated from the second conductivity type semiconductor body region 14 by a gate oxide layer 10; a first conductivity type semiconductor heavily doped source region I 4 on one side of the top of the second conductivity type semiconductor body region 14 and a first conductivity type semiconductor heavily doped source region II 5 on the other side of the top of the second conductivity type semiconductor body region 14; a second conductivity type semiconductor heavily doped contact region 11 on part of the top of the second conductivity type semiconductor body region 14; a longitudinal channel region 12 inside the side surface of the second conductivity type semiconductor body region 14 and parallel to the trench polysilicon gate electrode 7; the second conductivity type semiconductor heavily doped contact region 11 and part of the first conductivity type semiconductor heavily doped source region II 5 are electrically connected to the top layer source metal through the metal via 9 on their top; the trench polysilicon gate electrode 7 is electrically isolated from the lightly doped first conductivity type semiconductor lightly doped epitaxial layer 3, the first conductivity type semiconductor heavily doped source region I 4, the first conductivity type semiconductor heavily doped source region II 5, the second conductivity type semiconductor heavily doped contact region 11, the metal via 9 and the top layer metal by the interlayer dielectric 6;

[0008] On the BB1 profile, the device structure includes a metalized drain 1, a heavily doped first-conductivity-type semiconductor substrate 2 on the metalized drain 1, a lightly doped first-conductivity-type semiconductor lightly doped epitaxial layer 3 on the first-conductivity-type semiconductor substrate 2, a second-conductivity-type semiconductor body region 14 on the top of the lightly doped first-conductivity-type semiconductor lightly doped epitaxial layer 3, a planar polysilicon gate electrode 8 on the partial top of the second-conductivity-type semiconductor body region 14, a trench polysilicon gate electrode 7 directly connected with the planar polysilicon gate electrode 8, a lateral channel region 13 on the top of the second-conductivity-type semiconductor body region 14 and parallel to the planar polysilicon gate electrode 8, a second-conductivity-type semiconductor heavily doped contact region 11 on the partial top of the second-conductivity-type semiconductor body region 14, the second-conductivity-type semiconductor heavily doped contact region 11 being electrically connected with the top layer source metal through a metal via hole 9, and the planar polysilicon gate electrode 8 being electrically isolated from the lightly doped first-conductivity-type semiconductor lightly doped epitaxial layer 3, the first-conductivity-type semiconductor heavily doped source region I 4, the first-conductivity-type semiconductor heavily doped source region II 5, the second-conductivity-type semiconductor heavily doped contact region 11 and the top layer metal through an interlayer dielectric 6.

[0009] The first-conductivity-type semiconductor heavily doped source region I 4 is not directly connected with the source, and the first-conductivity-type semiconductor heavily doped source region I 4, the first-conductivity-type semiconductor heavily doped source region II 5, the planar polysilicon gate electrode 8 and the lateral channel region 13 form a lateral MOSFET structure.

[0010] As a preferred mode, the doping concentration of the heavily doped region is 1E18cm -3 -1E19cm -3 , and the doping concentration of the lightly doped region is 1E15cm -3 -1E16cm -3 .

[0011] As a preferred mode, the silicon material in the device is replaced by silicon carbide, gallium arsenide, indium phosphide or germanium silicon semiconductor material.

[0012] The beneficial effects of the present application are that, on the basis of the longitudinal channel of the conventional trench gate DMOS, a lateral MOSFET is further formed, the channel length is increased without increasing the layout area and the trench depth, the influence of the mobility on the drain current is significantly increased, the device can enter the current negative temperature characteristic region earlier, and the reliability of the device is improved, as shown in Figs. Figure 4 and Figure 5 . BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a three-dimensional structure schematic diagram of the embodiment 1 of the present application;

[0014] Figure 2 This is the present invention. Figure 1 A schematic diagram after longitudinal sectioning along line AA1;

[0015] Figure 3 This is the present invention. Figure 1 A schematic diagram showing the result after longitudinal sectioning along line BB1.

[0016] Figure 4 The transfer characteristic curves of this invention at different temperatures and the drain current I corresponding to the zero temperature point are... D * Indication;

[0017] Figure 5 The channel length of this invention is 1 / I D * The relationship.

[0018] 1 is a metallized drain; 2 is a heavily doped first conductivity type semiconductor substrate; 3 is a lightly doped first conductivity type semiconductor lightly doped epitaxial layer; 4 is a heavily doped first conductivity type semiconductor source region I; 5 is a heavily doped first conductivity type semiconductor source region II; 6 is an interlayer dielectric; 7 is a trench polysilicon gate electrode; 8 is a planar polysilicon gate electrode; 9 is a metal via; 10 is a gate oxide layer; 11 is a heavily doped second conductivity type semiconductor contact region; 12 is a longitudinal channel region; 13 is a lateral channel region; 14 is a second conductivity type semiconductor bulk region. Detailed Implementation

[0019] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0020] Example 1

[0021] like Figure 1 As shown, this embodiment provides a trench gate DMOS device with improved temperature characteristics. The top of the device is provided with a metal via 9. The longitudinal section passing through the metal via 9 of the device cell and parallel to the length of the metal via 9 is the BB1 ​​section. The longitudinal section passing through the metal via 9 and perpendicular to the length direction of the metal via 9, from one side of the cell to the other side, is the AA1 section.

[0022] like Figure 2As shown, on the AA1 cross section, the device structure includes a metalized drain 1, a heavily doped first-conductivity-type semiconductor substrate 2 on the metalized drain 1, a lightly doped first-conductivity-type semiconductor lightly doped epitaxial layer 3 on the heavily doped first-conductivity-type semiconductor substrate 2, a second-conductivity-type semiconductor body region 14 on top of the lightly doped first-conductivity-type semiconductor lightly doped epitaxial layer 3; the top of the lightly doped first-conductivity-type semiconductor lightly doped epitaxial layer 3 also has a trench, the trench is filled with a polysilicon gate electrode 7; the side of the trench is in contact with the second-conductivity-type semiconductor body region 14, the lower surface of the trench is lower than the lower surface of the second-conductivity-type semiconductor body region 14; the trench polysilicon gate electrode 7 is electrically isolated from the second-conductivity-type semiconductor body region 14 by a gate oxide layer 10; a first-conductivity-type semiconductor heavily doped source region I 4 on one side of the top of the second-conductivity-type semiconductor body region 14 and a first-conductivity-type semiconductor heavily doped source region II 5 on the other side of the top of the second-conductivity-type semiconductor body region 14; a second-conductivity-type semiconductor heavily doped contact region 11 on part of the top of the second-conductivity-type semiconductor body region 14; a longitudinal channel region 12 on the inside of the second-conductivity-type semiconductor body region 14 and parallel to the trench polysilicon gate electrode 7; the second-conductivity-type semiconductor heavily doped contact region 11 and part of the first-conductivity-type semiconductor heavily doped source region II 5 are electrically connected to the top layer source metal through a metal via hole 9 on the top thereof; the trench polysilicon gate electrode 7 is electrically isolated from the lightly doped first-conductivity-type semiconductor lightly doped epitaxial layer 3, the first-conductivity-type semiconductor heavily doped source region I 4, the first-conductivity-type semiconductor heavily doped source region II 5, the second-conductivity-type semiconductor heavily doped contact region 11, the metal via hole 9 and the top layer metal through an interlayer dielectric 6;

[0023] As Figure 3As shown, on the BB1 profile, the device structure includes a metalized drain 1, a heavily doped first-conductivity-type semiconductor substrate 2 on the metalized drain 1, a lightly doped first-conductivity-type semiconductor lightly doped epitaxial layer 3 on the first-conductivity-type semiconductor substrate 2, a second-conductivity-type semiconductor body region 14 on the top of the lightly doped first-conductivity-type semiconductor lightly doped epitaxial layer 3, a planar polysilicon gate electrode 8 on the top of the second-conductivity-type semiconductor body region 14, a trench polysilicon gate electrode 7 directly connected with the planar polysilicon gate electrode 8, a lateral channel region 13 on the top of the second-conductivity-type semiconductor body region 14 and parallel to the planar polysilicon gate electrode 8, a second-conductivity-type semiconductor heavily doped contact region 11 on the top of the second-conductivity-type semiconductor body region 14, the second-conductivity-type semiconductor heavily doped contact region 11 being electrically connected with the top layer source metal through a metal via hole 9, and the planar polysilicon gate electrode 8 being electrically isolated from the lightly doped first-conductivity-type semiconductor lightly doped epitaxial layer 3, the first-conductivity-type semiconductor heavily doped source region I 4, the first-conductivity-type semiconductor heavily doped source region II 5, the second-conductivity-type semiconductor heavily doped contact region 11 and the top layer metal through an interlayer dielectric 6.

[0024] The first-conductivity-type semiconductor heavily doped source region I 4 is not directly connected with the source electrode, and the first-conductivity-type semiconductor heavily doped source region I 4, the first-conductivity-type semiconductor heavily doped source region II 5, the planar polysilicon gate electrode 8 and the lateral channel region 13 form a lateral MOSFET structure.

[0025] The heavily doped region has a doping concentration of 1E18 cm -3 -1E19 cm -3 The lightly doped region has a doping concentration of 1E15 cm -3 -1E16 cm -3 .

[0026] The silicon material in the device is replaced by silicon carbide, gallium arsenide, indium phosphide or germanium silicon semiconductor material.

[0027] The working principle of the present application is illustrated by taking Example 1 as an example.

[0028] The working current of DMOS device shows negative temperature characteristic under large current condition, and shows positive temperature characteristic under small current condition. This is because the temperature characteristic of mobility is dominant under large current condition, and the temperature characteristic of threshold voltage is dominant under small current condition. When the temperature characteristic of mobility and the temperature characteristic of threshold voltage have opposite effects on current, the current point at which the effects of the two characteristics are counteracted is the zero temperature point of the device. When the drain current of DMOS is less than the zero temperature point, the device shows positive temperature characteristic, and when the drain current is greater than the zero temperature point, the device shows negative temperature characteristic. Since the positive temperature characteristic of drain current can cause failure or even burning of the device, in order to make the thermal stability of the device better, it is desirable that the zero temperature point of the device is as small as possible.

[0029] Taking the first conductive type semiconductor as an N-type semiconductor as an example. In the present application, when the trench polysilicon gate 7 and the planar polysilicon gate electrode 8 are at a high potential, the longitudinal channel region 12 of the trench gate DMOS and the longitudinal channel region 12 of the lateral MOSFET are formed, and the carriers start to flow. The carriers reaching the first conductive type semiconductor heavily doped source region II 5 pass through two parallel flow paths, one of which is through the lateral channel region 13, the first conductive type semiconductor heavily doped source region I 4, and the longitudinal channel region 12, and the other of which is directly through the longitudinal channel region 12. The presence of the lateral channel region 13 can increase the channel length without increasing the layout area and the trench depth, so that the influence of mobility on the drain current will be significantly increased, and the device can enter the current negative temperature characteristic region earlier, thereby improving the reliability of the device, as shown in Figure 4 and Figure 5 The parallel connection of the long channel path and the short channel path can not only improve the temperature characteristic of the device, but also take into account the low on-resistance of the device, and achieve a compromise in the performance of the device.

[0030] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A trench-gate DMOS device with improved temperature characteristics, characterized in that: The device has a metal through hole (9) on the top. The longitudinal section that passes through the metal through hole (9) of the device cell and is parallel to the length of the metal through hole (9) is the BB1 ​​section. The longitudinal section that passes through the metal through hole (9) and is perpendicular to the length direction of the metal through hole (9) from one side of the cell to the other is the AA1 section. In the AA1 cross section, the device structure includes a metallized drain (1), a heavily doped first conductivity type semiconductor substrate (2) above the metallized drain (1), and a lightly doped first conductivity type semiconductor epitaxial layer (3) above the heavily doped first conductivity type semiconductor substrate (2); a second conductivity type semiconductor body region (14) located on top of the lightly doped first conductivity type semiconductor epitaxial layer (3); the top of the lightly doped first conductivity type semiconductor epitaxial layer (3) also has a trench, and the trench is filled with a polysilicon gate electrode (7); the side of the trench is in contact with the second conductivity type semiconductor body region (14), and the lower surface of the trench is lower than the lower surface of the second conductivity type semiconductor body region (14); the trench polysilicon gate electrode (7) is electrically isolated from the second conductivity type semiconductor body region (14) through a gate oxide layer (10); and a first conductivity type semiconductor heavily doped source region located on one side of the top of the second conductivity type semiconductor body region (14). I(4) and the first conductive type semiconductor heavily doped source region II(5) located on the other side of the top of the second conductive type semiconductor body region (14); the second conductive type semiconductor heavily doped contact region (11) located on part of the top of the second conductive type semiconductor body region (14); the longitudinal channel region (12) is located on the inner side of the second conductive type semiconductor body region (14) and is parallel to the trench polysilicon gate electrode (7); the second conductive type semiconductor heavily doped contact region (11) and part of the first conductive type semiconductor heavily doped source region II(5) are electrically connected to the top source metal through the metal via (9) at their top; the trench polysilicon gate electrode (7) is electrically isolated from the lightly doped first conductive type semiconductor lightly doped epitaxial layer (3), the first conductive type semiconductor heavily doped source region I(4), the first conductive type semiconductor heavily doped source region II(5), the second conductive type semiconductor heavily doped contact region (11), the metal via (9) and the top metal through the interlayer dielectric (6); In the BB1 ​​cross section, the device structure includes a metallized drain (1), a heavily doped first conductivity type semiconductor substrate (2) above the metallized drain (1), a lightly doped first conductivity type semiconductor lightly doped epitaxial layer (3) above the first conductivity type semiconductor substrate (2); a second conductivity type semiconductor body region (14) located on top of the lightly doped first conductivity type semiconductor lightly doped epitaxial layer (3); a planar polysilicon gate electrode (8) on top of a portion of the second conductivity type semiconductor body region (14); a trench polysilicon gate electrode (7) and a planar polysilicon gate electrode (8) are directly connected, and a lateral channel region (13) is located at the top of the second conductivity type semiconductor body region (14). And parallel to the planar polysilicon gate electrode (8); the second conductivity type semiconductor heavily doped contact region (11) located on the top of part of the second conductivity type semiconductor body region (14); the second conductivity type semiconductor heavily doped contact region (11) is electrically connected to the top source metal through the metal via (9) at its top; the planar polysilicon gate electrode (8) is electrically isolated from the lightly doped first conductivity type semiconductor lightly doped epitaxial layer (3), the first conductivity type semiconductor heavily doped source region I (4), the first conductivity type semiconductor heavily doped source region II (5), the second conductivity type semiconductor heavily doped contact region (11), the metal via (9) and the top metal through the interlayer dielectric (6); The first type of semiconductor heavily doped source region I (4) is not directly connected to the source electrode; the first type of semiconductor heavily doped source region I (4), the first type of semiconductor heavily doped source region II (5), the planar polysilicon gate electrode (8), and the lateral channel region (13) form a lateral MOSFET structure.

2. The trench-gate DMOS device with improved temperature characteristics according to claim 1, characterized in that: The heavy doping concentration is 1E18cm. -3 -1E19cm -3 The lightly doped concentration is 1E15cm. -3 -1E16cm -3 .

3. The trench-gate DMOS device with improved temperature characteristics according to claim 1, characterized in that: The silicon material in the device is replaced with silicon carbide, gallium arsenide, indium phosphide, or germanium silicon semiconductor materials.

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