A cyclotron optimization starting device

Abstract

The invention discloses a cyclotron optimization start-up device, which comprises a tuning module for finding a tuning point based on a continuous closed-loop or pulse closed-loop mode, a low-level modulation output module based on a continuous closed-loop or pulse closed-loop mode, an amplitude demodulation module based on a continuous closed-loop or pulse closed-loop mode, a CPU based on a continuous closed-loop or pulse closed-loop mode, and a digital controller based on a continuous closed-loop or pulse closed-loop mode. The device is characterized in that the tuning module for finding a tuning point based on a continuous closed-loop or pulse closed-loop mode finds the tuning point in a low-power tuning stage and a pulse search stage, so that the cavity frequency and the high-frequency signal frequency are consistent, so as to improve the Q value of the cavity and meet the conditions for accelerating particles. The invention adopts a pre-tuning point + pulse closed-loop mode, which not only improves the quality factor in the cavity startup process, but also avoids the safety hazards caused by excessive power.

Description

Technical Field

[0001] The invention relates to a cyclotron high-frequency low-level system design technology, and in particular to a cyclotron optimization starting device. Background Art

[0002] There are three difficulties in the startup process of the cyclotron high-frequency cavity: the first difficulty is to avoid the secondary electron multiplication effect area, because the secondary electron multiplication effect will limit the power increase of the high-frequency system; the second difficulty is to find the tuning point, because if the tuning point cannot be found, even if the secondary electron multiplication effect area is crossed, it will still limit the power increase of the high-frequency system. The difficulty in finding the tuning point lies in: the compact cyclotron designed by the China Institute of Atomic Energy has a lower starting point power in the secondary electron multiplication area, nearly tens of milliwatts, which is nearly 100 times the minimum starting point of the existing technical-level electron multiplication area of ​​1 watt. It is more difficult to find the tuning point at ultra-low power; the third difficulty is: even if the tuning point is found and the secondary electron multiplication effect area is crossed, new problems will be encountered in the high-level continuous signal stage after the power is increased: on the one hand, the signal is required to be a high-power signal, and on the other hand, when the signal power is too high, if the quality factor Q of the cavity is not high enough, it will cause the reflected power to be too large, thereby burning the transmitter and the coupling window. For example, after finding the tuning point, pulse stretching is used to cross the electron multiplication region. After the pulse is stretched to 50%, it becomes a continuous signal and enters the power boost and normal operation stages under the continuous signal. The latter two stages require the power to remain high, but because it is a continuous high-power signal, when it accumulates to a certain level, it is very likely to burn out the transmitter and coupling window. Summary of the invention

[0003] In view of the problems existing in the prior art, the present invention proposes a cyclotron optimization starting device, the first purpose of which is to solve the problem of finding the tuning point under ultra-low power, and the second purpose of which is to solve the problem of easy breakdown and burning of the cavity under high-power continuous signals.

[0004] The present invention proposes the following technical solutions to solve the technical problems:

[0005] A cyclotron optimization startup device, the device comprises a tuning module for finding tuning points based on a continuous closed loop or a pulse closed loop mode, a low level modulation output module based on a continuous closed loop or a pulse closed loop mode, an amplitude demodulation module based on a continuous closed loop or a pulse closed loop mode, a CPU based on a continuous closed loop or a pulse closed loop mode, and a digital controller based on a continuous closed loop or a pulse closed loop mode; the CPU based on a continuous closed loop or a pulse closed loop mode is provided with a state machine for controlling a high frequency cavity startup process, the state machine comprises a shutdown state s0, a low power tuning state s1, a pulse search state s2, a power boost state s3, and a normal operation state s4 during the high frequency cavity startup process; the digital controller based on a continuous closed loop or a pulse closed loop mode is provided with a PID tuning algorithm unit, a DSP balancing algorithm unit, and a signal received from an analog circuit and realizing communication with the CPU; the PID tuning algorithm unit avoids cavity detuning by accelerating the PID operation rate; the DSP balancing algorithm unit ensures cavity pressure balance of two groups of cavities by adjusting a capacitor motor;

[0006] Its characteristics are: the tuning module for finding tuning points based on the continuous closed-loop or pulse closed-loop mode makes the cavity frequency and the high-frequency signal frequency consistent by finding the tuning points in the low-power tuning stage and the pulse search stage, so as to improve the Q value of the cavity and meet the conditions for accelerating particles; the continuous closed-loop mode means that the closed-loop modes of the low-power tuning state, the pulse search state and the power boost state are all continuous closed-loop modes; the pulse closed-loop mode means that the closed-loop mode of the low-power tuning state is the continuous closed-loop mode, and the closed-loop modes of the pulse search state and the power boost state are the pulse closed-loop mode.

[0007] Furthermore, in the continuous closed-loop mode, the low-power tuning state, the power boost state, and the normal operating state are set as the continuous signal operating mode, and the pulse search state is set as the pulse signal operating mode, and the tuning closed loop in the low-power tuning state, the tuning closed loop in the power search state, and the amplitude modulation closed loop in the power boost state are all closed loops under continuous signals; in the pulse closed-loop mode, only the low-power tuning state is set as the continuous signal operating mode, and the power search state, the power boost state, and the normal operating state are all pulse signal operating modes, and only the tuning closed loop in the low-power tuning state is a closed loop in the continuous signal operating mode, and the tuning closed loop in the power search state and the amplitude modulation closed loop in the power boost are all closed loops under pulse signals, and the closed loop under the pulse signal is determined to be closed when the pulse is at a high level.

[0008] Furthermore, the tuning module for finding the tuning point based on the continuous closed-loop or pulse closed-loop mode is provided with a cavity forward signal Forward, a cavity sampling signal Pickup1, a high-frequency switch 1 and a high-frequency switch 2, an amplifier and an attenuator, a phase detector, a tuning parameter setting module and a tuning comparator in sequence between the accelerator cavity and the CPU; the ADC analog signal derived from the phase detector is subtracted from the tuning parameter setting value, and the operation result is sent to the digital controller through the ADC in one way and to the tuning comparator in the other way; in the low-power tuning and pulse search states, the tuning comparator uses a continuous signal to judge the tuning closed loop, and when the tuning comparator judges that the cavity frequency and the high-frequency signal frequency are consistent, the tuning closed loop signal PhaseOK is output respectively, and the signal is sent to the CPU through the digital controller; the cavity forward signal Forward and the cavity sampling signal Pickup1 are obtained by sampling the sampling cable after the low-level modulation output module in the continuous closed-loop or pulse closed-loop mode drives the accelerator cavity.

[0009] Furthermore, in the low-power tuning state of the continuous closed-loop mode, the pulse-to-continuous circuit of the amplitude demodulation module outputs a pulse signal with a duty cycle of 10%, and the CPU controls the ForceCW signal to output a low-level signal, and performs an AND operation with the output of the pulse-to-continuous circuit. The result is still a low-level signal. The AND operation output result is given to the high-frequency switch 1 and the high-frequency switch 2 of the tuning module, and the high-voltage switch 3 of the low-level modulation output module as a low-level signal. The forward signal Forward of the cavity and the cavity sampling signal Pickup1 are selected to connect to their respective 25db amplifiers through the high-frequency switch 1 and the high-frequency switch 2, and the high-voltage switch 3 selects a 14db attenuator. In the power search state of the continuous closed-loop mode, the pulse-to-continuous circuit of the amplitude demodulation module outputs a pulse signal with a duty cycle that is continuously widened from 10% to 50%. The CPU controls the ForceCW signal to output a high-level signal, and performs an AND operation with the pulse signal output by the pulse-to-continuous circuit. The result is still a pulse with a duty cycle that is continuously widened. Signal, high frequency switches 1 and 2 select between the amplifier and the attenuator according to the pulse signal, and high frequency switch 3 also selects between 3db attenuation and 14db attenuation, that is, when the pulse is high level, switch 1 and switch 2 select 23db attenuator, switch 3 selects 3db attenuation, when the pulse is low level, switch 1 and switch 2 select 25db amplifier, switch 3 selects 14db attenuation; in the power boost state and normal operation state of the continuous closed-loop mode, the pulse-to-continuous circuit output of the amplitude demodulation module is a high-level continuous signal, the CPU controls the ForceCW signal to output a high-level signal, and performs an AND operation with the output result of the pulse-to-continuous circuit, the result is a high-level signal, and the AND operation output result gives a high level to high frequency switch 1 and high frequency switch 2, as well as high frequency switch 3 of the low-level modulation output module, the forward signal Forward of the cavity and the cavity sampling signal Pickup1 are selected to connect to their respective attenuators through high frequency switch 1 and high frequency switch 2, and high frequency switch 3 is connected to a 3db attenuator.

[0010] Furthermore, in the low-power tuning state of the pulse closed-loop mode, the CPU state machine turns from the off state s0 to the low-power tuning state s1, and sends s1 to the digital controller, and the digital controller gives a low-level signal to the high-frequency switch 1 and the high-frequency switch 2 of the tuning module, and the high-voltage switch 3 of the low-level modulation output module, and the forward signal Forward of the cavity and the cavity sampling signal Pickup1 are selected to connect to their respective amplifiers through the high-frequency switch 1 and the high-frequency switch 2, and the high-voltage switch 3 selects a 14db attenuator; in the power search state, the power boost state, and the normal operation state of the pulse closed-loop mode, the CPU state machine changes according to the low-power tuning state. The continuous tuning closed-loop signal PhaseOK in the tuning state, the pulse amplitude closed-loop signal PhaseOK in the pulse search state, and the pulse amplitude closed-loop signal VDeeOK in the power boost state respectively send s2, s3, and s4 signals to the digital controller in the pulse closed-loop mode. The digital controller in the pulse closed-loop mode gives a high level to the high-frequency switch 1 and high-frequency switch 2 of the tuning module and the high-voltage switch 3 of the low-level modulation output module. The forward signal Forward of the cavity and the cavity sampling signal Pickup1 are selected to connect to their respective attenuators through the high-frequency switch 1 and the high-frequency switch 2, and the high-voltage switch 3 is connected to the 3db attenuator.

[0011] Furthermore, the amplitude demodulation module based on the continuous closed-loop or pulse closed-loop mode is provided with a cavity sampling signal Pickup2, a detector, a pulse-to-continuous circuit, an amplitude modulation parameter setting module and an amplitude comparator in sequence between the accelerator cavity and the CPU; in the continuous closed-loop mode, after the cavity sampling signal Pickup2 is three centimeters, one path passes through a differential circuit for ignition detection judgment, and the other two paths, one path passes through detector 1 and the pulse-to-continuous circuit, and the pulse signal or continuous signal is input into the AND gate and the CPU for AND operation; one path is used for amplitude closed-loop judgment after being detected by detector 2; in the power boost state When the voltage value of the detection result of detector 1 is subtracted from the amplitude modulation parameter setting and it is judged that it is within the allowable range, it is judged as an amplitude closed loop, and a continuous amplitude closed loop signal VDee_OK is output to the CPU; in the pulse closed loop mode, after the cavity samples the signal Pickup2 for two centimeters, one path passes through the differential circuit for ignition detection judgment, and the other path passes through the detector for amplitude closed loop judgment; in the power boost state, when the voltage value of the detection result of the detector is subtracted from the amplitude modulation parameter setting and it is judged that it is within the allowable range, it is judged as an amplitude closed loop, and a pulse amplitude closed loop signal VDee_OK is output to the CPU.

[0012] Furthermore, in the pulse-to-continuous circuit of the continuous closed-loop mode, in the low-power tuning stage, the pulse-to-continuous circuit inputs a low-power signal and outputs a signal with a 10% duty cycle, which is given to the AND gate and performs an AND operation with the ForceCW controlled by the CPU, and the result of the AND operation is a low level; in the pulse search stage, the pulse-to-continuous circuit determines that the current power has reached the power of the low-power tuning closed loop, then outputs a pulse with a gradually widened duty cycle to the AND gate and performs an AND operation with the ForceCW controlled by the CPU, and the AND gate gives the pulse with a gradually widened duty cycle to the high-frequency switch 3, and selects to connect a 14db attenuator when the pulse is at a low level, and selects a 3db attenuator when it is at a high level, thereby achieving pulse widening; in the power boost stage, the pulse-to-continuous circuit determines that the current power has reached the power of the pulse search state amplitude closed loop, then outputs a continuous signal to the AND gate and performs an AND operation with the CPU, and the output of the AND gate is a continuous high level and is given to the high-frequency switch 3, and the high-frequency switch 3 is connected to the 3db attenuator according to the continuous high level signal.

[0013] Furthermore, the low-level modulation output module based on the continuous closed-loop or pulse closed-loop mode is sequentially provided with a high-frequency signal digital-to-analog module, an amplitude-phase modulation module, a 3db attenuator and a 14db attenuator, a high-frequency switch 3, a digitally controlled attenuator, and a low-level output signal along the direction from the digital controller to the accelerator cavity; in the low-power tuning state, the low-level output signal drives the accelerator cavity, thereby obtaining the cavity forward signal Forward and the cavity sampling signal Pickup1 of the tuning module through the sampling cable.

[0014] Furthermore, in the power search state of the continuous closed-loop mode, after the CPU receives the continuous tuning closed-loop PhaseOK signal in the low-power tuning state, it controls the high-frequency switch 3 to connect to the 3db attenuator and the 14db attenuator at different times through the AND gate operation result to achieve pulse width widening. At this time, the digitally controlled attenuator is a constant value and remains unchanged; in the power boost state of the continuous closed-loop mode, after the CPU receives the continuous tuning closed-loop signal PhaseOK in the pulse search phase, it controls the high-frequency switch 3 to connect to the 3db attenuator through the AND gate operation result, and instructs the digital controller to control the digitally controlled attenuator to continuously reduce attenuation, thereby continuously increasing power, until the amplitude modulation comparator of the amplitude demodulation module outputs a continuous amplitude closed-loop VDeeOK signal to the CPU. At this time, the power boost stage is completed and the normal operation state is entered.

[0015] Further, in the power search state of the pulse closed-loop mode, after the CPU receives the continuous tuning closed-loop PhaseOK signal of the low-power tuning state, the CPU state machine sends an s2 signal to the digital controller, and the digital controller sends a pulse with a certain duty cycle to the high-frequency switch 3. The high-frequency switch 3 is connected to a 3db attenuator when the pulse is high and a 14db attenuator when the pulse is low according to the fixed duty cycle pulse. At this time, the digitally controlled attenuator is a fixed value and remains unchanged; in the power boost state, after the CPU receives the pulse tuning closed-loop signal PhaseOK of the pulse search state, its state machine sends an s3 signal to the digital controller, and the digital controller sends a pulse with a certain duty cycle to the high-frequency switch 3. The high-frequency switch 3 is connected to a 3db attenuator when the pulse is high and a 14db attenuator when the pulse is low according to the fixed duty cycle pulse. At the same time, the digital controller controls the digitally controlled attenuator to continuously reduce the attenuation, thereby continuously increasing the power until the amplitude modulation comparator of the amplitude demodulation module outputs a pulse amplitude closed-loop signal VDeeOK to the CPU. At this time, the power boost stage is completed and the normal operation stage is entered.

[0016] Further, when the CPU based on the continuous closed-loop or pulse closed-loop mode receives the amplitude closed-loop signal VDeeOK of the amplitude demodulation module and enters the normal operation state, the digital controller starts the DSP balancing algorithm unit to balance the cavity pressure between the two cavities.

[0017] Furthermore, the PID tuning algorithm unit of the digital controller based on the continuous closed-loop or pulse closed-loop mode is arranged in the digital controller, using a PID operation module, a data arithmetic logic module, and a multi-bus architecture; the data arithmetic logic module is used to implement the addition and multiplication functions in the PID operation module, and the PID tuning algorithm unit describes the PID digital operation algorithm in the assembly language of DSP and uses parallel processing instructions under the multi-bus architecture to realize the synchronous execution of multiple operation instructions, thereby speeding up the PID operation rate and avoiding cavity detuning.

[0018] Furthermore, the PID operation module is provided with a PID operation output y(n) submodule for driving the accelerator cavity motor, a PID operation output y(n-1) submodule at the previous moment, a PID adjustment coefficient K0, K1, K2 submodule, and a PID input submodule of x(n), x(n-1) and x(n-2) at the current moment, the previous moment and the previous two moments; the data arithmetic logic module includes a DSP5600 series digital signal processor, which stores the PID input x(n), x(n-1) and x(n-2) at the current moment, the previous moment and the previous two moments in register R0, stores the PID adjustment coefficients k0, k1, k2 in register R3, uses the global bus to read and write these two registers, and uses the accumulator and multiplication functions in the DSP to implement assembly instructions.

[0019] y(n)=y(n-1)+k0*x(n)+k1*x(n-1)+k2*x(n-2).

[0020] Furthermore, the DSP balancing algorithm unit is provided with a voltage balancing ratio calculating unit and a voltage balancing adjusting unit; the voltage balancing ratio calculating unit is used for the ratio relationship: Among them, C12 is the coupling capacitance value between the two groups of cavities, which is divided into two parts C12" and C12', wherein C12" is the capacitance of the D1 cavity, and C12' is the capacitance of the D2 cavity; the voltage balancing unit can adjust the cavity D plate voltage by changing the ratio of C12" and C12'.

[0021] Furthermore, for the CPU based on the continuous closed-loop mode, when in the low-power tuning state, the forced conversion signal ForceCW of the CPU is 0, and when in the power search, power boost, and normal operation states, the forced conversion signal ForceCW of the CPU is 1.

[0022] Advantages and effects of the present invention

[0023] 1. The present invention adopts the pre-tuning point + pulse closed-loop mode, which not only improves the quality factor during the cavity startup process, but also avoids the safety hazards caused by excessive power. The pre-tuning point is found before the power is increased in the two stages. The first pre-tuning point is found before the low-power tuning state enters the pulse search state, so that when entering the pulse search state to increase the power, the input power to the cavity can be maximized, and the power reflected back by the cavity can be minimized, that is, the quality factor Q value of the cavity is the highest. The second pre-tuning point is found before entering the power boosting state from the pulse search state, that is, the tuning point is found for the second time in the pulse search stage, so that when entering the power boosting state, the input power to the cavity can be maximized and the power reflected back by the cavity can be minimized; the pulse closed-loop mode uses a pulse with a fixed duty cycle to replace the high-level continuous mode under the pulse search, power boost, and normal operating conditions, thereby solving the problem of excessive power burning the transmitter and the coupling window during the debugging process. At the same time, since the tuning point is judged when the pulse is at a high level, it does not affect the judgment of the tuning closed loop and also takes into account the problem of avoiding excessive power burning the transmitter and the coupling window.

[0024] 2. The present invention solves the long-standing problem of finding the tuning point at ultra-low power during the start-up of the accelerator cavity by organically combining the tuning module, the low-level modulation output module, the amplitude demodulation module, the PID tuning algorithm unit of the digital controller, the DSP balancing algorithm unit, and the CPU state machine. It also solves the problem of needing to find the tuning point twice due to power changes during the cavity start-up process: by setting the high-frequency switch 1 and the high-frequency switch 2, the amplifier, the attenuator, and the phase detector of the tuning module, the problem that the low-power signal cannot be recognized by the phase detector at ultra-low power and the high-power signal exceeds the maximum input voltage range of the phase detector is solved; by organically combining the PID tuning algorithm unit, the tuning parameter setting module, and the tuning comparator of the tuning module, the problem that the PID operation rate cannot keep up with the state change when finding the tuning point is solved; The low-level output signal of the low-level modulation output module, the organic combination of 3, 3db attenuation and 14db attenuation of the high-frequency switch and the tuning module not only realizes the tuning closed loop in the low-power tuning state, but also realizes the tuning closed loop in the high-power pulse search state; through the tuning closed loop of the tuning module, the amplitude demodulation module, the amplitude closed loop signal and the CPU state machine, and the digital controller, the control problem of the high-frequency signals 1, 2, and 3 in the two stages of the tuning closed loop is solved, so that the three high-frequency switches select one amplifier and one 14db attenuator at ultra-low power, so that the low-power signal can enter the phase detection range of the phase detector; at high power, the high-frequency signals 1, 2, and 3 select one attenuator and one 3db attenuator, so that the high-power cavity sampling signal will not exceed the maximum input voltage range of the phase detector. In short, through the organic combination of various modules, mutual support and mutual dependence, new effects are produced. Substantial progress has been achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1-1 It is a schematic diagram of the cyclotron optimization starting device based on the continuous closed-loop mode of the present invention;

[0026] Figure 1-2 It is a schematic diagram of the cyclotron optimization starting device based on the pulse closed-loop mode of the present invention;

[0027] Figure 2 Schematic diagram of the PID tuning algorithm for the invented optimized starting device.

[0028] Figure 3-1 This is a flow chart of the cyclotron optimization startup method based on the continuous closed-loop mode of the present invention.

[0029] Figure 3-2 This is a flow chart of the cyclotron optimization startup method based on the pulse closed-loop mode of the present invention. DETAILED DESCRIPTION

[0030] Design principle of the present invention

[0031] 1. The innovation of the present invention lies in: pre-tuning point + pulse closed-loop mode. The pre-tuning point is the pre-tuning point found before the power is increased in the two stages. The first pre-tuning point is the tuning point found before the low-power tuning state enters the pulse search state, so that when entering the pulse search state to increase the power, the input power to the cavity can be maximized and the power reflected back by the cavity can be minimized, that is, the Q value of the cavity is the highest. The second pre-tuning point is the tuning point found before entering the power increase state from the pulse search state, that is, the tuning point is found for the second time in the pulse search stage, so that when entering the power increase state, the input power to the cavity can be maximized and the power reflected back by the cavity can be minimized; the pulse closed-loop mode is to use a pulse with a fixed duty cycle to replace the high-level continuous mode under the pulse search, power increase, and normal operation state, thereby solving the problem of excessive power burning the transmitter and the coupling window during the debugging process. At the same time, since the tuning point is judged at the high level of the pulse, it does not affect the judgment of the tuning closed loop and also takes into account the problem of avoiding excessive power burning the transmitter and the coupling window.

[0032] 2. Difficulties in the design of the present invention: One of the difficulties is to achieve tuning under ultra-low power. 1) Compared with the lowest power of 1 watt in the prior art, the low power of the present invention is only tens of milliwatts, which is more than 100 times different. Because the cavity signal is weak under the ultra-low power signal, it cannot enter the phase detection range of the phase detector; 2) When tuning from low power to pulse search state, the tuning point will also change if the power changes, and it is necessary to find the tuning point again. When the tuning point is found again, the sampled cavity signal is a high-power signal, and the high-power signal will burn the phase detector when entering the phase detector; 3) The PID algorithm is required to adapt to the rate of state change and the requirements of the data processing speed of the previous state and the next state. The PID output result is used to control the motor of the cavity so that the cavity signal and the high-frequency signal are consistent, thereby realizing the tuning closed loop. Before the next state is reached, the PID is required to complete the processing of the data of the previous state, so as not to mix the data of the next state and the previous state together because the data of the previous state has not been processed, resulting in output errors. The second difficulty is that under high power conditions, it is necessary to meet high power requirements while preventing the cavity from being punctured and destroyed.

[0033] 3. Solution of the present invention: The solution to the first difficulty is: 1) Set up three high-frequency switches, set up high-frequency switch 1 and high-frequency switch 2 in the tuning module, and set up amplifiers and attenuators corresponding to high-frequency switches 1 and 2. Set up high-frequency switch 3 in the low-level modulation output module, and set up 3db and 14db attenuators. When in the low-power tuning state, the amplifier is selected through the high-frequency switches 1 and 2. The amplifier is 25db, so that the signal is amplified and enters the phase detector range, thereby solving the problem that the signal power is too low and it is not easy to enter the phase detector range. In order to ensure that the ultra-low power signal is input to the cavity in the low-power tuning state, the high-frequency switch 3 is also required to select a 14db attenuator to ensure that the signal output to the cavity is an ultra-low power signal of tens of millivolts; 2) When switching to the power search state, in order to prevent the cavity sampling signal from burning the phase detector, the high-frequency switches 1 and 2 select the attenuator. This attenuation is based on the standard of not burning the phase detector. Therefore, the attenuator should be designed moderately (23db attenuation); in order to ensure that the high-power signal is input to the cavity in the power search state, the high-frequency switch 3 is also required to select a 3db attenuator. Different attenuators are selected by the high-frequency switch 3 to increase or decrease the power. 3) Speed ​​up PID processing: Method 1 is to execute several instructions together, including addition instructions, multiplication instructions, input instructions, output instructions, and shift instructions, which speeds up the serial execution of instructions compared to conventional methods; Method 2 is to use assembly language, which is more basic than other languages, so it has a fast operation speed; Method 3 is to use a multi-bus architecture, which further highlights the effect of parallel processing compared to an architecture with only one bus. The above three methods support and depend on each other, and none of them can be missing. Only the combination of the three can achieve the best effect.

[0034] The solution to the second problem is: in the power search state, power boost state, and formal operation state, replace the high-power continuous signal with a pulse signal with a fixed duty cycle; in the power search state, use the high level of the pulse to judge the tuning closed loop; in the power boost state, use the high level of the pulse to judge the amplitude closed loop; in the formal operation state, change the high-power continuous signal into a pulse signal with a fixed duty cycle. In this way, a discrete high-power pulse signal is used to replace the high-power continuous signal, reducing the cumulative effect of the high-power signal. Since the power of the discrete pulse signal has not been reduced, it also meets the high power requirements of the power search state, power boost state, and formal operation state. Among them, the power of the power boost state and the formal operation state is higher than the power of the pulse search state, because this power is the power after the power boost after the pulse search state.

[0035] The present invention will be further explained below in conjunction with the accompanying drawings:

[0036] A cyclotron optimization startup device Figure 1-1 ,1-2 As shown, the device includes a tuning module for finding tuning points based on a continuous closed loop or pulse closed loop mode, a low-level modulation output module based on a continuous closed loop or pulse closed loop mode, an amplitude demodulation module based on a continuous closed loop or pulse closed loop mode, a CPU based on a continuous closed loop or pulse closed loop mode, and a digital controller based on a continuous closed loop or pulse closed loop mode; the CPU based on a continuous closed loop or pulse closed loop mode is provided with a state machine for controlling the high-frequency cavity startup process, and the state machine includes a closed state s0, a low-power tuning state s1, a pulse search state s2, a power boost state s3, and a normal operation state s4 during the high-frequency cavity startup process; the digital controller based on a continuous closed loop or pulse closed loop mode is provided with a PID tuning algorithm unit, a DSP balancing algorithm unit, and a signal received from an analog circuit and communicated with the CPU; the PID tuning algorithm unit avoids cavity detuning by accelerating the PID operation rate; the DSP balancing algorithm unit ensures the cavity pressure balance of the two groups of cavities by adjusting the capacitor motor;

[0037] Its characteristics are: the tuning module for finding tuning points based on the continuous closed-loop or pulse closed-loop mode makes the cavity frequency and the high-frequency signal frequency consistent by finding the tuning points in the low-power tuning stage and the pulse search stage, so as to improve the Q value of the cavity and meet the conditions for accelerating particles; the continuous closed-loop mode means that the closed-loop modes of the low-power tuning state, the pulse search state and the power boost state are all continuous closed-loop modes; the pulse closed-loop mode means that the closed-loop mode of the low-power tuning state is the continuous closed-loop mode, and the closed-loop modes of the pulse search state and the power boost state are the pulse closed-loop mode.

[0038] Supplementary Note 1:

[0039] 1. The cyclotron optimization starting device of the present invention includes five main parts: a tuning module, a low-level modulation output module, an amplitude demodulation module, a CPU, and a digital controller. The five main parts can be used in both continuous closed-loop mode and pulse closed-loop mode. The difference is that when used in the continuous closed-loop mode, the high-frequency switches 1 and 2 of the tuning module and the high-frequency switch 3 of the low-level modulation output module are controlled by the AND gate of the amplitude demodulation module; when used in the pulse closed-loop mode, the high-frequency switches 1 and 2 of the tuning module and the high-frequency switch 3 of the low-level modulation output module are controlled by the CPU state machine and the digital controller. The CPU state machine sends a signal to the digital controller, and then the digital controller controls the high-frequency switches 1, 2, and 3. The continuous closed loop is to realize the tuning closed loop and amplitude closed loop under continuous signal, and the pulse closed loop is to realize the tuning closed loop and amplitude closed loop under the high level of pulse signal. However, the tuning closed loop of the pulse closed loop is only applicable to the tuning closed loop of the pulse search state, and is not applicable to the tuning closed loop of the low power tuning state. The tuning closed loop of the low power tuning state is always the tuning closed loop under continuous signal.

[0040] 2. Figure 1-1 , 1-2 It is divided into three parts: upper, middle and lower. The top layer is the tuning module, the bottom layer is the amplitude demodulation module, and the middle layer is the low-level output module. The top and bottom layers are sampling from the cavity, and the middle layer is inputting high-frequency signals to the cavity. The purpose of sampling from the cavity is to perform tuning closed loop and amplitude closed loop; the purpose of inputting high-frequency signals to the cavity is to increase the power of the cavity to the voltage that can accelerate particles, and to ensure that the cavity frequency is stable at the high-frequency signal frequency, so as to achieve the purpose of accelerating particles.

[0041] 3. The power increase must meet two conditions. The first is to find the tuning point, that is, the tuning closed loop. At this time, the signal output to the cavity can increase the power; the second is the amplitude closed loop. Although the tuning closed loop finds the tuning point, the power may still not reach the set height, so it is necessary to realize the amplitude closed loop, that is, the amplitude reaches the set height. Therefore, the low-level output signal of the middle layer is a process of power from low to high.

[0042] 4. The pulse search state is used to cross the multi-electron multiplication region. The method is that in the pulse search state, the first pulse crosses the voltage region that produces multi-electron multiplication. Assuming that the multi-electron multiplication region is from 10 millivolts to 100 millivolts, the voltage region of the first pulse hitting the high-frequency cavity is 101 millivolts, which is across the electron multiplication region, to achieve the effect of avoiding the multi-electron multiplication region. In the continuous closed-loop mode, the pulse in the pulse search state quickly widens to 0.5% duty cycle, and then becomes a high-level continuous signal. In the pulse closed-loop mode, the pulse in the pulse search state is a pulse with a fixed duty cycle. Since the tuning point is found in advance in the low-power tuning state, the power added to the high-frequency cavity in the pulse search stage is high enough, and the reflected power of the high-frequency cavity is as small as possible. Therefore, whether it is a continuous closed loop or a pulse closed loop, in the power search state, the power added to the high-frequency cavity meets the requirements due to the high cavity Q value.

[0043] Furthermore, in the continuous closed-loop mode, the low-power tuning state, the power boost state, and the normal operating state are set as the continuous signal operating mode, and the pulse search state is set as the pulse signal operating mode, and the tuning closed loop in the low-power tuning state, the tuning closed loop in the power search state, and the amplitude modulation closed loop in the power boost state are all closed loops under continuous signals; in the pulse closed-loop mode, only the low-power tuning state is set as the continuous signal operating mode, and the power search state, the power boost state, and the normal operating state are all pulse signal operating modes, and only the tuning closed loop in the low-power tuning state is a closed loop in the continuous signal operating mode, and the tuning closed loop in the power search state and the amplitude modulation closed loop in the power boost are all closed loops under pulse signals, and the closed loop under the pulse signal is determined to be closed when the pulse is at a high level.

[0044] Supplementary Note 2

[0045] The continuous closed-loop mode means that two stages of tuning closed-loop (low-power tuning state, power search state) and one stage of amplitude closed-loop (power boost state) are both closed-loop under the condition of continuous signals.

[0046] The pulse closed-loop mode means that the low-power tuning state is tuned and closed under a continuous signal, while the power search state and the power boost state are closed under the condition of a pulse signal.

[0047] Furthermore, the tuning module for finding the tuning point based on the continuous closed-loop or pulse closed-loop mode is provided with a cavity forward signal Forward, a cavity sampling signal Pickup1, a high-frequency switch 1 and a high-frequency switch 2, an amplifier and an attenuator, a phase detector, a tuning parameter setting module and a tuning comparator in sequence between the accelerator cavity and the CPU; the ADC analog signal derived from the phase detector is subtracted from the tuning parameter setting value, and the operation result is sent to the digital controller through the ADC in one way and to the tuning comparator in the other way; in the low-power tuning and pulse search states, the tuning comparator uses a continuous signal to judge the tuning closed loop, and when the tuning comparator judges that the cavity frequency and the high-frequency signal frequency are consistent, the tuning closed loop signal PhaseOK is output respectively, and the signal is sent to the CPU through the digital controller; the cavity forward signal Forward and the cavity sampling signal Pickup1 are obtained by sampling the sampling cable after the low-level modulation output module in the continuous closed-loop or pulse closed-loop mode drives the accelerator cavity.

[0048] Supplementary Note 3

[0049] The relationship between the tuning module and the other two modules. Although it is an independent module, the tuning module is inseparable from the low-level output signal of the low-level output module: the low-level output signal drives the accelerator cavity to generate the cavity forward signal Forward and the cavity sampling signal Pickup1; the tuning module is also inseparable from the AND gate operation result of the amplitude demodulation module, because it is the AND gate operation result that controls the high-frequency switches 1 and 2 of the tuning module, and controls the high-frequency switch 3 at the same time. Although the high-frequency switch 3 belongs to the low-level output module, it will also affect the tuning closed loop of the second stage of the tuning module, that is, the power search stage: specifically, in the power search stage, the cavity signal power entering the high-frequency switches 1 and 2 is enhanced. At this time, it is not necessary to select an amplifier but an attenuator, because the signal is too strong, so it needs to be attenuated to facilitate the phase detector phase detection. Only when it enters the phase detector phase detection range can the tuning closed loop judgment under the subsequent power search state be performed. The cavity signal power entering the high-frequency switches 1 and 2 is enhanced because the high-frequency switch selects a 3db attenuator to enhance the signal power entering the cavity. In short, the tuning module is inseparable from the other two modules because the tuning module serves two stages. Only when the tuning module is organically combined with the other two modules can the tuning closed-loop judgment of the two stages be realized.

[0050] Furthermore, in the low-power tuning state of the continuous closed-loop mode, the pulse-to-continuous circuit of the amplitude demodulation module outputs a pulse signal with a duty cycle of 10%, and the CPU controls the ForceCW signal to output a low-level signal, and performs an AND operation with the output of the pulse-to-continuous circuit. The result is still a low-level signal. The AND operation output result is given to the high-frequency switch 1 and the high-frequency switch 2 of the tuning module, and the high-voltage switch 3 of the low-level modulation output module as a low-level signal. The forward signal Forward of the cavity and the cavity sampling signal Pickup1 are selected to connect to their respective 25db amplifiers through the high-frequency switch 1 and the high-frequency switch 2, and the high-voltage switch 3 selects a 14db attenuator. In the power search state of the continuous closed-loop mode, the pulse-to-continuous circuit of the amplitude demodulation module outputs a pulse signal with a duty cycle that is continuously widened from 10% to 50%. The CPU controls the ForceCW signal to output a high-level signal, and performs an AND operation with the pulse signal output by the pulse-to-continuous circuit. The result is still a pulse with a duty cycle that is continuously widened. Signal, high frequency switches 1 and 2 select between the amplifier and the attenuator according to the pulse signal, and high frequency switch 3 also selects between 3db attenuation and 14db attenuation, that is, when the pulse is high level, switch 1 and switch 2 select 23db attenuator, switch 3 selects 3db attenuation, when the pulse is low level, switch 1 and switch 2 select 25db amplifier, switch 3 selects 14db attenuation; in the power boost state and normal operation state of the continuous closed-loop mode, the pulse-to-continuous circuit output of the amplitude demodulation module is a high-level continuous signal, the CPU controls the ForceCW signal to output a high-level signal, and performs an AND operation with the output result of the pulse-to-continuous circuit, the result is a high-level signal, and the AND operation output result gives a high level to high frequency switch 1 and high frequency switch 2, as well as high frequency switch 3 of the low-level modulation output module, the forward signal Forward of the cavity and the cavity sampling signal Pickup1 are selected to connect to their respective attenuators through high frequency switch 1 and high frequency switch 2, and high frequency switch 3 is connected to a 3db attenuator.

[0051] Furthermore, in the low-power tuning state of the pulse closed-loop mode, the CPU state machine turns from the off state s0 to the low-power tuning state s1, and sends s1 to the digital controller, and the digital controller gives a low-level signal to the high-frequency switch 1 and the high-frequency switch 2 of the tuning module, and the high-voltage switch 3 of the low-level modulation output module, and the forward signal Forward of the cavity and the cavity sampling signal Pickup1 are selected to connect to their respective amplifiers through the high-frequency switch 1 and the high-frequency switch 2, and the high-voltage switch 3 selects a 14db attenuator; in the power search state, the power boost state, and the normal operation state of the pulse closed-loop mode, the CPU state machine changes according to the low-power tuning state. The continuous tuning closed-loop signal PhaseOK in the tuning state, the pulse amplitude closed-loop signal PhaseOK in the pulse search state, and the pulse amplitude closed-loop signal VDeeOK in the power boost state respectively send s2, s3, and s4 signals to the digital controller in the pulse closed-loop mode. The digital controller in the pulse closed-loop mode gives a high level to the high-frequency switch 1 and high-frequency switch 2 of the tuning module and the high-voltage switch 3 of the low-level modulation output module. The forward signal Forward of the cavity and the cavity sampling signal Pickup1 are selected to connect to their respective attenuators through the high-frequency switch 1 and the high-frequency switch 2, and the high-voltage switch 3 is connected to the 3db attenuator.

[0052] Furthermore, the amplitude demodulation module based on the continuous closed-loop or pulse closed-loop mode is provided with a cavity sampling signal Pickup2, a detector, a pulse-to-continuous circuit, an amplitude modulation parameter setting module and an amplitude comparator in sequence between the accelerator cavity and the CPU; in the continuous closed-loop mode, after the cavity sampling signal Pickup2 is three centimeters, one path passes through a differential circuit for ignition detection judgment, and the other two paths, one path passes through detector 1 and the pulse-to-continuous circuit, and the pulse signal or continuous signal is input into the AND gate and the CPU for AND operation; one path is used for amplitude closed-loop judgment after being detected by detector 2; in the power boost state When the voltage value of the detection result of detector 1 is subtracted from the amplitude modulation parameter setting and it is judged that it is within the allowable range, it is judged as an amplitude closed loop, and a continuous amplitude closed loop signal VDee_OK is output to the CPU; in the pulse closed loop mode, after the cavity samples the signal Pickup2 for two centimeters, one path passes through the differential circuit for ignition detection judgment, and the other path passes through the detector for amplitude closed loop judgment; in the power boost state, when the voltage value of the detection result of the detector is subtracted from the amplitude modulation parameter setting and it is judged that it is within the allowable range, it is judged as an amplitude closed loop, and a pulse amplitude closed loop signal VDee_OK is output to the CPU.

[0053] Supplementary Note 4

[0054] In continuous closed loop mode, if Figure 1-1As shown, the pulse-to-continuous circuit of the amplitude demodulation module cooperates with the CPU to jointly output a signal to the AND gate, and the operation result of the AND gate is used to control three high-frequency switches.

[0055] In pulse closed loop mode, if Figure 1-2 As shown, the amplitude demodulation module does not have an AND gate, and the control of the high-frequency switches 1, 2, and 3 is controlled by the CPU state machine.

[0056] Furthermore, in the pulse-to-continuous circuit of the continuous closed-loop mode, in the low-power tuning stage, the pulse-to-continuous circuit inputs a low-power signal and outputs a signal with a 10% duty cycle, which is given to the AND gate and performs an AND operation with the ForceCW controlled by the CPU, and the result of the AND operation is a low level; in the pulse search stage, the pulse-to-continuous circuit determines that the current power has reached the power of the low-power tuning closed loop, then outputs a pulse with a gradually widened duty cycle to the AND gate and performs an AND operation with the ForceCW controlled by the CPU, and the AND gate gives the pulse with a gradually widened duty cycle to the high-frequency switch 3, and selects to connect a 14db attenuator when the pulse is at a low level, and selects a 3db attenuator when it is at a high level, thereby achieving pulse widening; in the power boost stage, the pulse-to-continuous circuit determines that the current power has reached the power of the pulse search state amplitude closed loop, then outputs a continuous signal to the AND gate and performs an AND operation with the CPU, and the output of the AND gate is a continuous high level and is given to the high-frequency switch 3, and the high-frequency switch 3 is connected to the 3db attenuator according to the continuous high level signal.

[0057] Furthermore, the low-level modulation output module based on the continuous closed-loop or pulse closed-loop mode is sequentially provided with a high-frequency signal digital-to-analog module, an amplitude-phase modulation module, a 3db attenuator and a 14db attenuator, a high-frequency switch 3, a digitally controlled attenuator, and a low-level output signal along the direction from the digital controller to the accelerator cavity; in the low-power tuning state, the low-level output signal drives the accelerator cavity, thereby obtaining the cavity forward signal Forward and the cavity sampling signal Pickup1 of the tuning module through the sampling cable.

[0058] Supplementary Note 5

[0059] 1. The relationship between the low-level modulation output module and the other two types of modules: The purpose of setting up the low-level modulation output module is to input signals of different powers to the cavity under different states. At the same time, the low-level modulation output module also requires the cooperation of the other two modules: in the low-power tuning state, since the signal power output to the cavity is very low, the high-frequency switches 1 and 2 of the tuning module are required to amplify the signal through the amplifier, and the high-frequency switch 3 of the low-power output module is required to select 14db attenuation; in the power search stage, power boost state, and normal operation state, since the signal power output to the cavity is enhanced, all three high-frequency switches are required to select the filter or 3db attenuator; at the same time, the low-level modulation output module also requires the cooperation of the amplitude modulation module, and the cavity sampling signal of the amplitude modulation module is sampled and given to the AND gate, and the three high-frequency signal switches are controlled by the AND operation results.

[0060] 2. The low-level modulation output module also controls the signal power output to the cavity in four states through the combination of high-frequency switch 3 and digitally controlled attenuator. When in the low-power tuning state, high-frequency switch 3 selects 14db attenuator and the digitally controlled attenuator remains constant; in the pulse search state, high-frequency switch 3 selects 3db attenuator and the digitally controlled attenuator remains constant; in the power boost state, the digital controller controls the digitally controlled attenuator to continuously reduce the attenuation and high-frequency switch 3 selects 3db attenuator; in the normal operating stage, high-frequency switch 3 selects 3db attenuator and the digitally controlled attenuator remains constant.

[0061] 3. In the continuous closed-loop mode, the high-frequency switch 3 of the low-level modulation output module is controlled by the AND gate operation result of the amplitude modulation module. In the pulse closed-loop mode, the high-frequency switch 3 of the low-level modulation output module is controlled by the CPU state machine.

[0062] Furthermore, in the power search state of the continuous closed-loop mode, after the CPU receives the continuous tuning closed-loop PhaseOK signal in the low-power tuning state, it controls the high-frequency switch 3 to connect to the 3db attenuator and the 14db attenuator at different times through the AND gate operation result to achieve pulse width widening. At this time, the digitally controlled attenuator is a constant value and remains unchanged; in the power boost state of the continuous closed-loop mode, after the CPU receives the continuous tuning closed-loop signal PhaseOK in the pulse search phase, it controls the high-frequency switch 3 to connect to the 3db attenuator through the AND gate operation result, and instructs the digital controller to control the digitally controlled attenuator to continuously reduce attenuation, thereby continuously increasing power, until the amplitude modulation comparator of the amplitude demodulation module outputs a continuous amplitude closed-loop VDeeOK signal to the CPU. At this time, the power boost stage is completed and the normal operation state is entered.

[0063] Further, in the power search state of the pulse closed-loop mode, after the CPU receives the continuous tuning closed-loop PhaseOK signal of the low-power tuning state, the CPU state machine sends an s2 signal to the digital controller, and the digital controller sends a pulse with a certain duty cycle to the high-frequency switch 3. The high-frequency switch 3 is connected to a 3db attenuator when the pulse is high and a 14db attenuator when the pulse is low according to the fixed duty cycle pulse. At this time, the digitally controlled attenuator is a fixed value and remains unchanged; in the power boost state, after the CPU receives the pulse tuning closed-loop signal PhaseOK of the pulse search state, its state machine sends an s3 signal to the digital controller, and the digital controller sends a pulse with a certain duty cycle to the high-frequency switch 3. The high-frequency switch 3 is connected to a 3db attenuator when the pulse is high and a 14db attenuator when the pulse is low according to the fixed duty cycle pulse. At the same time, the digital controller controls the digitally controlled attenuator to continuously reduce the attenuation, thereby continuously increasing the power until the amplitude modulation comparator of the amplitude demodulation module outputs a pulse amplitude closed-loop signal VDeeOK to the CPU. At this time, the power boost stage is completed and the normal operation stage is entered.

[0064] Further, when the CPU based on the continuous closed-loop or pulse closed-loop mode receives the amplitude closed-loop signal VDeeOK of the amplitude demodulation module and enters the normal operation state, the digital controller starts the DSP balancing algorithm unit to balance the cavity pressure between the two cavities.

[0065] Furthermore, the PID tuning algorithm unit of the digital controller based on the continuous closed-loop or pulse closed-loop mode is arranged in the digital controller, using a PID operation module, a data arithmetic logic module, and a multi-bus architecture; the data arithmetic logic module is used to implement the addition and multiplication functions in the PID operation module, and the PID tuning algorithm unit describes the PID digital operation algorithm in the assembly language of DSP and uses parallel processing instructions under the multi-bus architecture to realize the synchronous execution of multiple operation instructions, thereby speeding up the PID operation rate and avoiding cavity detuning.

[0066] Furthermore, the PID operation module is as follows: Figure 2As shown, there are provided a PID operation output y(n) submodule for driving the accelerator cavity motor, a PID operation output y(n-1) submodule at the previous moment, a PID adjustment coefficient K0, K1, K2 submodule, and a PID input submodule of x(n), x(n-1) and x(n-2) at the current moment, the previous moment and the previous two moments; the data arithmetic logic module includes a DSP5600 series digital signal processor, which stores the PID input x(n), x(n-1) and x(n-2) at the current moment, the previous moment and the previous two moments in register R0, stores the PID adjustment coefficients k0, k1, k2 in register R3, uses the global bus to read and write these two registers, and uses the DSP

[0067] The accumulator and multiplication functions in the , using assembly instructions to implement

[0068] y(n)=y(n-1)+k0*x(n)+k1*x(n-1)+k2*x(n-2).

[0069] Supplementary Note 6

[0070] This parallel assembly instruction effectively improves the operation rate of the PID algorithm. The output result of the y(n) submodule is used to tune the movement of the motor to change the resonant frequency of the cavity, thereby affecting the phase difference between the cavity sampling signal and the forward signal, so that the output voltage of the phase detector approaches the set voltage of the parameter setting module. The set voltage of the parameter setting module is the voltage of the phase difference between the cavity sampling signal and the cavity forward signal when the preset cavity frequency and the high-frequency signal frequency are consistent. The output voltage of the phase detector is the voltage of the actual phase difference between the cavity sampling signal and the cavity forward signal.

[0071] Furthermore, the DSP balancing algorithm unit is provided with a voltage balancing ratio calculating unit and a voltage balancing adjusting unit; the voltage balancing ratio calculating unit is used for the ratio relationship: Among them, C12 is the coupling capacitance value between the two groups of cavities, which is divided into two parts C12" and C12', wherein C12" is the capacitance of the D1 cavity, and C12' is the capacitance of the D2 cavity; the voltage balancing unit can adjust the cavity D plate voltage by changing the ratio of C12" and C12'.

[0072] Furthermore, for the CPU based on the continuous closed-loop mode, when in the low-power tuning state, the forced conversion signal ForceCW of the CPU is 0, and when in the power search, power boost, and normal operation states, the forced conversion signal ForceCW of the CPU is 1.

[0073] Embodiment 1

[0074] Based on the above-mentioned cyclotron optimization startup device, the present invention also designs a cyclotron optimization startup method based on a continuous closed-loop mode. Figure 3-1 As shown, its characteristic is that it includes the following steps:

[0075] A cyclotron optimization startup method based on a continuous closed-loop mode comprises the following steps:

[0076] Step 1: Initialization preparation

[0077] 1) Establish a one-button start-up process for the cyclotron low-level system;

[0078] 2) Establish a CPU state machine, the state of the state machine is S0~S4;

[0079] Step 2: Enter the low power tuning state in the continuous closed loop mode and realize the tuning closed loop in the low power state;

[0080] Step 3: Enter the pulse search state in the continuous closed-loop mode and implement the tuning closed-loop in the pulse search state;

[0081] Step 4: Enter the power boost state in the continuous closed-loop mode and realize the amplitude closed-loop in the power boost state;

[0082] Step 5: Enter the normal operating state under the continuous closed-loop mode and achieve cavity pressure balance under the normal operating state.

[0083] Furthermore, the step 2 of entering the low-power tuning state in the continuous closed-loop mode and realizing the tuning closed loop in the low-power state is specifically performed as follows:

[0084] 1) The low-level modulation output module inputs a low-level continuous signal to the accelerator cavity, and the low-level continuous signal drives the accelerator cavity, and obtains the cavity forward signal Forward, cavity sampling signal Pickup1, and cavity sampling signal Pickup2 of the tuning module from the accelerator through the sampling cable;

[0085] 2) After the cavity sampling signal Pickup2 is three centimeters, one path passes through the differential circuit for ignition detection and judgment, and the other two paths, one path is detected by the detector and used for amplitude closed-loop judgment, and the other path of the signal passes through the detector 1 and the pulse-to-continuous circuit to output a continuous signal, and the continuous signal is input to the AND gate and CPU for AND operation, and the AND operation result outputs a low level;

[0086] 3) A low level signal is given to high frequency switch 1, high frequency switch 2, and high frequency switch 3;

[0087] 4) High-frequency switch 1 and high-frequency switch 2 are connected to the amplifier to ensure that the signal can enter the phase detection range of the phase detector; high-frequency switch 3 is connected to a 14db attenuator to ensure that the voltage of the low-level continuous signal output has not reached the secondary electron multiplication effect area of ​​the cavity;

[0088] 5) performing a subtraction operation on the ADC analog signal derived from the phase detector and the tuning parameter setting value, and sending the operation result to the digital controller through the ADC in one way and to the tuning comparator in the other way;

[0089] 6) When the tuning comparator determines that the cavity frequency and the high-frequency signal frequency are consistent, it outputs a tuning closed-loop signal PhaseOK to the CPU, realizing the tuning closed-loop in the low-power tuning state and entering the pulse search phase.

[0090] Furthermore, the step 3 of entering the pulse search state in the continuous closed-loop mode and realizing the tuning closed-loop in the pulse search state is specifically performed as follows:

[0091] 1) After the CPU receives the tuning closed-loop signal PhaseOK in the low-power tuning state, its forced conversion signal ForceCW output is 1;

[0092] 2) After the cavity sampling signal Pickup2 is three centimeters, one path passes through the differential circuit for ignition detection and judgment, and the other two paths, one path is detected by the detector and used for amplitude closed-loop judgment, and the other path of the signal passes through the detector 1 and the pulse-to-continuous circuit to output a pulse with a gradually widened duty cycle. The pulse signal with a gradually widened duty cycle is input to the AND gate and CPU for AND operation, and the AND operation result outputs a pulse signal with a gradually widened duty cycle;

[0093] 3) The pulse signal with gradually widened duty cycle is sent to high frequency switch 3, and is also sent to high frequency switches 1 and 2;

[0094] 4) According to the pulse signal with gradually widened duty cycle, the high-frequency switch 3 selects one 3db attenuator when the pulse is at high level and one 14db attenuator when the pulse is at low level, so as to achieve the widening of the low-level output pulse signal; according to the pulse signal with gradually widened duty cycle, the high-frequency switch 1 and the high-frequency switch 2 of the tuning module select one attenuator when the pulse is at high level and one amplification when the pulse is at low level; because the power is increased in the pulse search state, the cavity forward signal Forward and the cavity sampling signal Pickup1 with increased power enter the phase detector through the attenuator;

[0095] 5) Subtracting the ADC analog signal derived from the phase detector from the tuning parameter setting value, and sending the result of the operation to the digital controller through the ADC and to the tuning comparator through the other path;

[0096] 6) When the tuning comparator determines that the cavity frequency and the high-frequency signal frequency are consistent, it outputs a tuning closed-loop signal PhaseOK to the CPU, implements the tuning closed-loop in the pulse search state, enters the power boost state, and closes the tuning comparator.

[0097] Furthermore, the step 4 of entering the power boost state in the continuous closed-loop mode and realizing the amplitude closed-loop in the power boost state is specifically performed as follows:

[0098] 1) After the CPU receives the tuning closed-loop signal PhaseOK in the power search state, its forced conversion signal ForceCW output is 1;

[0099] 2) After the cavity sampling signal Pickup2 is three centimeters, one path passes through the differential circuit for ignition detection and judgment, and the other two paths, one path is detected by the detector and used for amplitude closed-loop judgment, and the other path of the signal passes through the detector 1 and the pulse-to-continuous circuit to output a high-level continuous signal, which is input into the AND gate and CPU for AND operation, and the AND operation result outputs a high-level continuous signal;

[0100] 3) A high-level continuous signal is sent to high-frequency switch 3, and a high-level continuous signal is sent to high-frequency switches 1 and 2 at the same time;

[0101] 4) The high-frequency switch 3 selects the 3db attenuator according to the high-frequency signal; the high-frequency switches 1 and 2 of the tuning module select one attenuator according to the high-frequency signal;

[0102] 5) The digital controller controls the digital controlled attenuator to continuously reduce the attenuation, and then continuously increase the power, until the amplitude modulation comparator of the amplitude demodulation module outputs a continuous amplitude closed-loop VDeeOK signal to the CPU. At this time, the power boost stage is completed, the amplitude closed-loop is realized, and the normal operation state is entered.

[0103] Furthermore, the step 5 of entering the normal operation state in the continuous closed-loop mode and achieving cavity pressure balance in the normal operation state is specifically performed as follows:

[0104] 1) After the CPU receives the amplitude closed-loop signal VDee_OK in the power boost state, its forced conversion signal ForceCW output is 1;

[0105] 2) After the cavity sampling signal Pickup2 is three centimeters, one path passes through the differential circuit for ignition detection and judgment, and the other two paths, one path is detected by the detector and used for amplitude closed-loop judgment, and the other path of the signal passes through the detector 1 and the pulse-to-continuous circuit to output a high-level continuous signal. The continuous signal is input to the AND gate and CPU for AND operation, and the AND operation result outputs a high-level continuous signal;

[0106] 3) A high-level continuous signal is sent to high-frequency switch 3, and a high-level continuous signal is sent to high-frequency switches 1 and 2 at the same time;

[0107] 4) The high-frequency switch 3 selects the 3db attenuator according to the high-frequency signal; the high-frequency switches 1 and 2 of the tuning module select one attenuator according to the high-frequency signal;

[0108] 5) The numerically controlled attenuator is a constant value;

[0109] 6) The digital controller starts the DSP balancing algorithm unit to balance the cavity pressure between the two cavities.

[0110] Furthermore, the digital controller of the process 6) starts the DSP balance algorithm unit to balance the cavity pressure between the two cavities, and the specific steps are as follows:

[0111] 1) When the two cavities of the accelerator are capacitively coupled, the ratio of the voltage imbalance between the two cavities due to factors such as processing design is shown in the following formula [1]:

[0112]

[0113] Wherein, C12 is the coupling capacitance value between the two groups of cavities, which is divided into two parts, C12" and C12', where C12" is the capacitance of the D1 cavity and C12' is the capacitance of the D2 cavity;

[0114] 2) The D voltage can be adjusted by changing the ratio of C12” and C12', and its balance control algorithm is as follows: The phase detector output result Tphase determines the movement frequency of the capacitor motor, and the motor movement step setting value Dsteps determines the movement steps of the motor. When Dsteps>0, Tphase>0, the motor of the D1 cavity group moves in the positive direction at 2 times the speed, and the motor of the D2 cavity group stops; when Dsteps>0, Tphase<0, the motor of the D2 cavity group moves in the reverse direction at 2 times the speed, and the motor of the D1 cavity group does not move; when Dsteps<0, TPhase>0, the motor of the D2 cavity group moves in the positive direction at twice the speed, and the motor of the D1 cavity group does not move; when Dsteps<0, TPhase<0, the motor of the D1 cavity group moves in the reverse direction at twice the speed, and the motor of the D2 cavity group does not move.

[0115] Furthermore, the closed-loop tuning of step 2 and step 3 is implemented by the PID tuning algorithm unit of the digital controller as follows:

[0116] 1) The digital PID algorithm is expressed as:

[0117] y(n)=y(n-1)+K0x(n)+K1x(n-1)+K2(n-2);

[0118] Where y(n) is the PID operation output, y(n-1) is the PID operation output at the previous moment, K0, K1, and K2 are PID adjustment coefficients, and x(n), x(n-1), and x(n-2) are the PID inputs at the current moment, the previous moment, and the previous two moments;

[0119] 2) Use R0 and R3 registers in the DSP's X memory, and read and write operations are performed by the global data bus;

[0120] 3) Store the PID inputs x(n), x(n-1) and x(n-2) of the current moment, the previous moment and the previous two moments into register R0, and store k0, k1, k2 into register R3;

[0121] 4) Use the global bus to read and write these two registers and use the accumulator and multiplication function in the DSP to implement y(n)=y(n-1)+k0*x(n)+k1*x(n-1)+k2*x(n-2).

[0122] Embodiment 2

[0123] Based on the above-mentioned cyclotron optimization startup device, the present invention also relates to a cyclotron optimization startup method based on a pulse closed-loop mode. Figure 3-2 As shown, its characteristic is that it includes the following steps:

[0124] Step 1: Initialization preparation

[0125] 1) Establish a one-button start-up process for the cyclotron low-level system;

[0126] 2) Establish a CPU state machine, the state of the state machine is S0~S4;

[0127] Step 2: Enter the low-power tuning state in the pulse closed-loop mode and implement the tuning closed-loop in the low-power tuning state;

[0128] Step 3: Enter the pulse search state in the pulse closed-loop mode and implement the tuning closed-loop in the pulse search state;

[0129] Step 4: Enter the power boost state in the pulse closed-loop mode and realize the amplitude closed-loop in the power boost state;

[0130] Step 5: Enter the normal operating state under the pulse closed-loop mode and achieve cavity pressure balance under the normal operating state.

[0131] Furthermore, the step 2 of entering the low-power tuning state in the pulse closed-loop mode and realizing the tuning closed-loop in the low-power tuning state is specifically performed as follows:

[0132] 1) The low-level modulation output module inputs a low-level pulse signal to the accelerator cavity, and the low-level pulse signal drives the accelerator cavity, and obtains the cavity forward signal Forward, cavity sampling signal Pickup1, and cavity sampling signal Pickup2 of the tuning module through the sampling cable from the accelerator;

[0133] 2) The CPU state machine changes from the shutdown state s0 to the low power tuning state s1 and sends s1 to the digital controller.

[0134] 3) The digital controller gives a low level signal to the high frequency switch 1 and high frequency switch 2 of the tuning module and the high voltage switch 3 of the low level modulation output module respectively;

[0135] 4) The forward signal Forward of the cavity and the cavity sampling signal Pickup1 are connected to their respective amplifiers through high-frequency switch 1 and high-frequency switch 2 to ensure that the low-power signal can enter the phase detector range; high-voltage switch 3 selects a 14db attenuator;

[0136] 5) performing a subtraction operation on the ADC analog signal derived from the phase detector and the tuning parameter setting value, and sending the operation result to the digital controller through the ADC in one way and to the tuning comparator in the other way;

[0137] 6) The PID tuning algorithm unit performs a tuning closed-loop operation under low-power tuning state: when it is determined that the cavity frequency and the high-frequency signal frequency are consistent, a tuning closed-loop signal PhaseOK is output to the CPU to implement the tuning closed-loop under low-power tuning state and enter the pulse search phase; under low-power tuning state, the tuning comparator determines the tuning closed-loop under continuous signals.

[0138] Furthermore, the step 3 of entering the pulse search state in the pulse closed-loop mode and realizing the tuning closed-loop in the pulse search state is specifically performed as follows:

[0139] 1) After receiving the tuning closed-loop signal PhaseOK in the low-power tuning state, the CPU sends the s2 signal to the digital controller;

[0140] 2) The digital controller sends a pulse signal with a fixed duty cycle to high-frequency switch 3, and to high-frequency switches 1 and 2 at the same time;

[0141] 3) The high-frequency switches 1 and 2 of the tuning module select one attenuator according to the high-level signal of the pulse signal with a fixed duty cycle. Since the power is increased in the pulse search state, the cavity forward signal Forward and the cavity sampling signal Pickup1 after the power is increased enter the phase detector through the attenuator; the high-frequency switch 3 selects one 3db attenuator when the pulse is at a high level and one 14db attenuator when the pulse is at a low level according to the pulse signal with a fixed duty cycle, thereby realizing equal-width pulses in the power search state;

[0142] 4) performing a subtraction operation on the ADC analog signal derived from the phase detector and the tuning parameter setting value, and sending the operation result to the digital controller through the ADC in one way and to the tuning comparator in the other way;

[0143] 5) The PID tuning algorithm unit performs a tuning closed-loop operation in the pulse search state: when it is determined that the cavity frequency and the high-frequency signal frequency are consistent, a pulse tuning closed-loop signal PhaseOK is output to the CPU to implement the pulse tuning closed-loop in the pulse search state, and the tuning comparator is closed to enter the power boost state; in the pulse search state, the tuning comparator determines the tuning point when the pulse is at a high level.

[0144] Furthermore, the step 4 of entering the power boost state in the pulse closed-loop mode and realizing the amplitude closed-loop in the power boost state is specifically performed as follows:

[0145] 1) After receiving the pulse tuning closed-loop signal PhaseOK in the power search state, the CPU sends the s3 signal to the digital controller;

[0146] 2) The digital controller sends a pulse signal with a fixed duty cycle to high-frequency switch 3, and to high-frequency switches 1 and 2 at the same time;

[0147] 3) The high-frequency switch 3 selects a 3db attenuator when the pulse is at a high level and a 14db attenuator when the pulse is at a low level according to the pulse signal with a fixed duty cycle, thereby realizing equal-width pulses in the power boost state; the high-frequency switches 1 and 2 of the tuning module select an attenuator when the pulse signal with a fixed duty cycle is at a high level and selects an amplifier when the pulse is at a low level.

[0148] 4) The digital controller controls the digital controlled attenuator to continuously reduce the attenuation, and then continuously increase the power, until the amplitude modulation comparator of the amplitude demodulation module outputs the pulse amplitude closed-loop VDeeOK signal to the CPU. At this time, the power boost stage is completed, the amplitude closed-loop is realized, and the normal operation state is entered.

[0149] Furthermore, the step 5 of entering the normal operation state under the pulse closed-loop mode and achieving cavity pressure balance under the normal operation state is specifically performed as follows:

[0150] 1) After receiving the pulse amplitude closed-loop signal VDee_OK in the power boost state, the CPU sends the s4 signal to the digital controller;

[0151] 2) The digital controller sends a pulse signal of equal width to high-frequency switch 3 and to high-frequency switches 1 and 2 at the same time;

[0152] 3) According to the pulse signal of fixed duty cycle, high frequency switch 3 selects one 3db attenuator when the pulse is at high level and one 14db attenuator when the pulse is at low level, so as to realize the pulse of fixed duty cycle under normal operation; high frequency switch 1 and high frequency switch 2 of the tuning module select one attenuator according to the high level signal of equal width pulse signal and select one amplifier when the pulse is at low level.

[0153] 4) The numerically controlled attenuator is a constant value;

[0154] 5) The digital controller starts the DSP balancing algorithm unit to balance the cavity pressure between the two cavities.

[0155] Furthermore, the digital controller of the process 5) starts the DSP balance algorithm unit to balance the cavity pressure between the two cavities, and the specific steps are as follows:

[0156] 1) When the two cavities of the accelerator are capacitively coupled, the voltage imbalance between the two cavities due to factors such as processing design is expressed by a ratio relationship:

[0157]

[0158] Among them, C 12 is the coupling capacitance between the two groups of cavities, which is divided into two parts C 12 ” and C 12 ', where C 12 ” is the capacitance of cavity D1, C 12 ' is the capacitance of cavity D2;

[0159] 2) Change C 12 ” and C 12The D voltage can be adjusted by the ratio of ', and the balance control algorithm is as follows: the phase detector output result Tphase determines the movement frequency of the capacitor motor, and the motor movement step setting value Dsteps determines the movement steps of the motor. When Dsteps>0, Tphase>0, the D1 cavity group motor moves in the positive direction at 2 times the speed, and the D2 cavity group motor stops; when Dsteps>0, Tphase<0, the D2 cavity group motor moves in the reverse direction at 2 times the speed, and the D1 cavity group motor does not move; when Dsteps<0, TPhase>0, the D2 cavity group motor moves in the positive direction at twice the speed, and the D1 cavity group motor does not move; when Dsteps<0, TPhase<0, the D1 cavity group motor moves in the reverse direction at twice the speed, and the D2 cavity group motor does not move.

[0160] Furthermore, the PID tuning algorithm unit performs a closed-loop tuning operation, and the implementation process is as follows:

[0161] 1) The digital PID algorithm is expressed as:

[0162] y(n)=y(n-1)+K0x(n)+K1x(n-1)+K2(n-2);

[0163] Where y(n) is the PID operation output, y(n-1) is the PID operation output at the previous moment, K0, K1, and K2 are PID adjustment coefficients, and x(n), x(n-1), and x(n-2) are the PID inputs at the current moment, the previous moment, and the previous two moments;

[0164] 2) Use R0 and R3 registers in the DSP's X memory, and read and write operations are performed by the global data bus;

[0165] 3) Store the PID inputs x(n), x(n-1) and x(n-2) of the current moment, the previous moment and the previous two moments into register R0, and store k0, k1, k2 into register R3;

[0166] 4) Use the global bus to read and write these two registers, and use the accumulator and multiplication functions in the DSP and assembly language to implement y(n)=y(n-1)+k0*x(n)+k1*x(n-1)+k2*x(n-2).

[0167] It should be emphasized that the above specific embodiments are merely explanations of the present invention, and they are not limitations of the present invention. After reading this specification, those skilled in the art can make modifications to the above embodiments without any creative contribution as needed, but as long as they are within the scope of the claims of the present invention, they are protected by patent law.

Claims

1. A cyclotron optimization startup device, the device comprising a tuning module for finding tuning points based on a continuous closed loop or pulse closed loop mode, a low level modulation output module based on a continuous closed loop or pulse closed loop mode, an amplitude demodulation module based on a continuous closed loop or pulse closed loop mode, a CPU based on a continuous closed loop or pulse closed loop mode, and a digital controller based on a continuous closed loop or pulse closed loop mode; the CPU based on a continuous closed loop or pulse closed loop mode is provided with a state machine for controlling a high-frequency cavity startup process, the state machine comprising a shutdown state s0, a low power tuning state s1, a pulse search state s2, a power boost state s3, and a normal operation state s4 during the high-frequency cavity startup process; the digital controller based on a continuous closed loop or pulse closed loop mode is provided with a PID tuning algorithm unit, a DSP balancing algorithm unit, and a signal received from an analog circuit and communicating with the CPU; the PID tuning algorithm unit avoids cavity detuning by accelerating the PID operation rate; the DSP balancing algorithm unit ensures cavity pressure balance of two groups of cavities by adjusting a capacitor motor; Features: The tuning module for finding tuning points based on the continuous closed-loop or pulse closed-loop mode makes the cavity frequency and the high-frequency signal frequency consistent by finding the tuning points in the low-power tuning stage and the pulse search stage, so as to improve the Q value of the cavity and meet the conditions for accelerating particles; the continuous closed-loop mode means that the closed-loop modes of the low-power tuning state, the pulse search state, and the power boost state are all continuous closed-loop modes; the pulse closed-loop mode means that the closed-loop mode of the low-power tuning state is the continuous closed-loop mode, and the closed-loop modes of the pulse search state and the power boost state are the pulse closed-loop mode; The continuous closed-loop mode sets the low-power tuning state, power boost state, and normal operating state as the continuous signal operating mode, sets the pulse search state as the pulse signal operating mode, and the tuning closed loop in the low-power tuning state, the tuning closed loop in the power search state, and the amplitude modulation closed loop in the power boost state are all closed loops under continuous signals; the pulse closed-loop mode sets only the low-power tuning state as the continuous signal operating mode, and the power search state, power boost state, and normal operating state are all pulse signal operating modes, and only the tuning closed loop in the low-power tuning state is a closed loop in the continuous signal operating mode, and the tuning closed loop in the power search state and the amplitude modulation closed loop under power boost are all closed loops under pulse signals, and the closed loop under the pulse signal is determined to be closed when the pulse is at a high level; The tuning module for finding the tuning point based on the continuous closed-loop or pulse closed-loop mode is provided with a cavity forward signal Forward, a cavity sampling signal Pickup1, a high-frequency switch 1 and a high-frequency switch 2, an amplifier and an attenuator, a phase detector, a tuning parameter setting module and a tuning comparator in sequence between the accelerator cavity and the CPU; the ADC analog signal derived from the phase detector is subtracted from the tuning parameter setting value, and the operation result is sent to the digital controller through the ADC in one way and to the tuning comparator in the other way; in the low-power tuning and pulse search states, the tuning comparator uses a continuous signal to judge the tuning closed loop, and when the tuning comparator judges that the cavity frequency and the high-frequency signal frequency are consistent, the tuning closed loop signal PhaseOK is output respectively, and the signal is sent to the CPU through the digital controller; the cavity forward signal Forward and the cavity sampling signal Pickup1 are obtained by sampling the sampling cable after the low-level modulation output module in the continuous closed-loop or pulse closed-loop mode drives the accelerator cavity; In the low-power tuning state of the continuous closed-loop mode, the pulse-to-continuous circuit of the amplitude demodulation module outputs a pulse signal with a duty cycle of 10%, and the CPU controls the ForceCW signal to output a low-level signal, and performs an AND operation with the output of the pulse-to-continuous circuit. The result is still a low-level signal. The AND operation output result is given to the high-frequency switch 1 and high-frequency switch 2 of the tuning module, and the high-voltage switch 3 of the low-level modulation output module. A low-level signal, the forward signal Forward of the cavity and the cavity sampling signal Pickup1 are selected to connect to their respective 25db amplifiers through the high-frequency switch 1 and the high-frequency switch 2, and the high-voltage switch 3 selects a 14db attenuator. In the power search state of the continuous closed-loop mode, the pulse-to-continuous circuit of the amplitude demodulation module outputs a pulse signal with a duty cycle that is continuously widened from 10% to 50%. The CPU controls the ForceCW signal to output a high-level signal, and performs an AND operation with the pulse signal output by the pulse-to-continuous circuit. The result is still a pulse signal with a continuously widened duty cycle. , high-frequency switches 1 and 2 select between the amplifier and the attenuator according to the pulse signal, and high-frequency switch 3 also selects between 3db attenuation and 14db attenuation, that is, when the pulse is at a high level, switch 1 and switch 2 select the 23db attenuator, and switch 3 selects 3db attenuation. When the pulse is at a low level, switch 1 and switch 2 select the 25db amplifier, and switch 3 selects 14db attenuation; in the power boost state and normal operation state of the continuous closed-loop mode, the pulse-to-continuous circuit output of the amplitude demodulation module is a high-level continuous signal, the CPU controls the ForceCW signal to output a high-level signal, and performs an AND operation with the output result of the pulse-to-continuous circuit, the result is a high-level signal, and the AND operation output result is given to high-frequency switch 1 and high-frequency switch 2, as well as high-frequency switch 3 of the low-level modulation output module. A high level, the forward signal Forward of the cavity and the cavity sampling signal Pickup1 are selected to connect to their respective attenuators through high-frequency switch 1 and high-frequency switch 2, and high-frequency switch 3 is connected to a 3db attenuator; In the low-power tuning state of the pulse closed-loop mode, the CPU state machine turns from the off state s0 to the low-power tuning state s1, and sends s1 to the digital controller. The digital controller gives a low-level signal to the high-frequency switch 1 and high-frequency switch 2 of the tuning module, and the high-voltage switch 3 of the low-level modulation output module. The forward signal Forward of the cavity and the cavity sampling signal Pickup1 are selected to connect to their respective amplifiers through the high-frequency switch 1 and the high-frequency switch 2, and the high-voltage switch 3 selects a 14db attenuator. In the power search state, power boost state, and normal operation state of the pulse closed-loop mode, the CPU state machine changes according to the low-power tuning state. The continuous tuning closed-loop signal PhaseOK in the state, the pulse amplitude closed-loop signal PhaseOK in the pulse search state, and the pulse amplitude closed-loop signal VDeeOK in the power boost state respectively send s2, s3, and s4 signals to the digital controller in the pulse closed-loop mode. The digital controller in the pulse closed-loop mode gives a high level to the high-frequency switch 1 and high-frequency switch 2 of the tuning module and the high-voltage switch 3 of the low-level modulation output module. The forward signal Forward of the cavity and the cavity sampling signal Pickup1 are selected to connect to their respective attenuators through the high-frequency switch 1 and high-frequency switch 2, and the high-voltage switch 3 is connected to the 3db attenuator.

2. The cyclotron optimization startup device according to claim 1, characterized in that: The amplitude demodulation module based on the continuous closed-loop or pulse closed-loop mode is provided with a cavity sampling signal Pickup2, a detector, a pulse-to-continuous circuit, an amplitude modulation parameter setting module and an amplitude comparator in sequence between the accelerator cavity and the CPU; in the continuous closed-loop mode, the cavity sampling signal Pickup2 is three centimeters away, one path passes through a differential circuit for ignition detection and judgment, and the other two paths, one path passes through detector 1 and the pulse-to-continuous circuit, and the pulse signal or continuous signal is input into the AND gate and the CPU for AND operation; one path is detected by detector 2 and used for amplitude closed-loop judgment; in the power boost state, when If the voltage value of the detection result of detector 1 is subtracted from the amplitude modulation parameter setting and it is judged to be within the allowable range, it is judged to be an amplitude closed loop, and a continuous amplitude closed loop signal VDee_OK is output to the CPU; in the pulse closed loop mode, after the cavity sampling signal Pickup2 is two centimeters, one path passes through the differential circuit for ignition detection judgment, and the other path passes through the detector for amplitude closed loop judgment; in the power boost state, when the voltage value of the detection result of the detector is subtracted from the amplitude modulation parameter setting and it is judged to be within the allowable range, it is judged to be an amplitude closed loop, and a pulse amplitude closed loop signal VDee_OK is output to the CPU.

3. The cyclotron optimization startup device according to claim 2, characterized in that: The pulse-to-continuous circuit in the continuous closed-loop mode, in the low-power tuning stage, the pulse-to-continuous circuit inputs a low-power signal and outputs a signal with a 10% duty cycle, the signal is given to the AND gate and performs an AND operation with the ForceCW controlled by the CPU, and the result of the AND operation is a low level; in the pulse search stage, the pulse-to-continuous circuit determines that the current power has reached the power of the low-power tuning closed loop, then outputs a pulse with a gradually widened duty cycle to the AND gate and performs an AND operation with the ForceCW controlled by the CPU, the AND gate gives the pulse with a gradually widened duty cycle to the high-frequency switch 3, and selects to connect a 14db attenuator when the pulse is at a low level, and selects a 3db attenuator when it is at a high level, thereby achieving pulse widening; in the power boost stage, the pulse-to-continuous circuit determines that the current power has reached the power of the pulse search state amplitude closed loop, then outputs a continuous signal to the AND gate and performs an AND operation with the CPU, the output of the AND gate is a continuous high level and is given to the high-frequency switch 3, and the high-frequency switch 3 is connected to the 3db attenuator according to the continuous high level signal.

4. The cyclotron optimization startup device according to claim 1, characterized in that: The low-level modulation output module based on the continuous closed-loop or pulse closed-loop mode is provided with a high-frequency signal digital-to-analog module, an amplitude-phase modulation module, a 3db attenuator and a 14db attenuator, a high-frequency switch 3, a digitally controlled attenuator, and a low-level output signal in sequence along the direction from the digital controller to the accelerator cavity; in the low-power tuning state, the low-level output signal drives the accelerator cavity, thereby obtaining the cavity forward signal Forward and the cavity sampling signal Pickup1 of the tuning module through the sampling cable.

5. The cyclotron optimization startup device according to claim 4, characterized in that: In the power search state of the continuous closed-loop mode, after the CPU receives the continuous tuning closed-loop PhaseOK signal in the low-power tuning state, it controls the high-frequency switch 3 to connect to the 3db attenuator and the 14db attenuator at different times through the AND gate operation result to achieve pulse width widening. At this time, the digitally controlled attenuator is a fixed value and remains unchanged; in the power boost state of the continuous closed-loop mode, after the CPU receives the continuous tuning closed-loop signal PhaseOK in the pulse search phase, it controls the high-frequency switch 3 to connect to the 3db attenuator through the AND gate operation result, and instructs the digital controller to control the digitally controlled attenuator to continuously reduce attenuation, thereby continuously increasing power, until the amplitude modulation comparator of the amplitude demodulation module outputs a continuous amplitude closed-loop VDeeOK signal to the CPU. At this time, the power boost stage is completed and the normal operating state is entered.

6. The cyclotron optimization startup device according to claim 5, characterized in that: In the power search state of the pulse closed-loop mode, after the CPU receives the continuous tuning closed-loop PhaseOK signal of the low-power tuning state, the CPU state machine sends the s2 signal to the digital controller, and the digital controller sends a pulse with a certain duty cycle to the high-frequency switch 3. According to the fixed duty cycle pulse, the high-frequency switch 3 is connected to a 3db attenuator when the pulse is high and a 14db attenuator when the pulse is low. At this time, the digitally controlled attenuator is a fixed value and remains unchanged; in the power boost state, after the CPU receives the pulse tuning closed-loop signal PhaseOK of the pulse search state, its state machine sends the s3 signal to the digital controller, and the digital controller sends a pulse with a certain duty cycle to the high-frequency switch 3. According to the fixed duty cycle pulse, the high-frequency switch 3 is connected to a 3db attenuator when the pulse is high and a 14db attenuator when the pulse is low. At the same time, the digital controller controls the digitally controlled attenuator to continuously reduce the attenuation, and then continuously increase the power until the amplitude modulation comparator of the amplitude demodulation module outputs a pulse amplitude closed-loop signal VDeeOK to the CPU. At this time, the power boost stage is completed and the normal operation stage is entered.

7. The cyclotron optimization startup device according to claim 6, characterized in that: When the CPU based on the continuous closed-loop or pulse closed-loop mode receives the amplitude closed-loop signal VDeeOK from the amplitude demodulation module and enters the normal operation state, the digital controller starts the DSP balancing algorithm unit to balance the cavity pressure between the two cavities.

8. The cyclotron optimization startup device according to claim 1, characterized in that: The PID tuning algorithm unit of the digital controller based on the continuous closed-loop or pulse closed-loop mode is arranged in the digital controller, using a PID operation module, a data arithmetic logic module, and a multi-bus architecture; the data arithmetic logic module is used to realize the addition and multiplication functions in the PID operation module, and the PID tuning algorithm unit describes the PID digital operation algorithm in the assembly language of DSP and uses parallel processing instructions under the multi-bus architecture to realize the synchronous execution of multiple operation instructions, thereby speeding up the PID operation rate and avoiding cavity detuning.

9. The cyclotron optimization startup device according to claim 8, characterized in that: The PID operation module is provided with a PID operation output y(n) submodule for driving the accelerator cavity motor, a PID operation output y(n-1) submodule at the last moment, a PID adjustment coefficient K0, K1, K2 submodule, and a PID input submodule of x(n), x(n-1) and x(n-2) at the current moment, the last moment and the previous two moments; the data arithmetic logic module includes a DSP5600 series digital signal processor, which stores the PID input x(n), x(n-1) and x(n-2) at the current moment, the last moment and the previous two moments in register R0, stores the PID adjustment coefficients K0, K1, K2 in register R3, uses a global bus to read and write these two registers, and uses the accumulator and multiplication functions in the DSP to implement y(n)=y(n-1)+ K0*x(n)+ K1*x(n-1)+ K2*x(n-2) using assembly instructions.

10. The cyclotron optimization startup device according to claim 9, characterized in that: The DSP balance algorithm unit is provided with a voltage balance ratio calculation unit and a voltage balance adjustment unit; the voltage balance ratio calculation unit is used for the ratio relationship: N=V D1 / V D2 = C 12 ” / C 12 ’; Among them, C12 is the coupling capacitance value between the two groups of cavities, which is divided into two parts C12" and C12', wherein C12" is the capacitance of the D1 cavity, and C12' is the capacitance of the D2 cavity; the voltage balancing unit can adjust the cavity D plate voltage by changing the ratio of C12" and C12'.

11. The cyclotron optimization startup device according to claim 1, characterized in that: For the CPU based on the continuous closed-loop mode, when in the low-power tuning state, the forced conversion signal ForceCW of the CPU is 0, and when in the power search, power boost, and normal operation states, the forced conversion signal ForceCW of the CPU is 1.

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