Setting power modes based on workload levels in a memory subsystem

Abstract

A workload level in an incoming request queue is determined based on one or more operations requested by a host system for execution by a memory subsystem. Based on the workload level in the incoming request queue, a set of memory dies of the memory subsystem to be activated for execution of the one or more operations is identified. A power mode configuration for memory dies of the set of memory dies is determined based on a power budget level. One or more parameters of the memory dies are configured to establish the power mode configuration.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to a memory subsystem, and more specifically, to setting a power mode based on the workload level in the memory subsystem. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0005] Figure 2 This is a flowchart of an example method for establishing a power mode configuration for a memory die, according to some embodiments.

[0006] Figure 3 The description describes an example system, according to some embodiments, that includes a power mode management component configured according to some embodiments to establish a power mode configuration for one or more memory dies.

[0007] Figure 4 It is a table containing, according to some embodiments, an instance power mode configuration such as that determined by the power mode management component.

[0008] Figure 5 It is a table containing, according to some embodiments, an instance power mode configuration such as that determined by the power mode management component.

[0009] Figure 6 This is a block diagram of an example computer system in which embodiments of this disclosure may operate. Detailed Implementation

[0010] This disclosure relates to setting power modes based on workload levels in a memory subsystem. The memory subsystem can be a storage device, a memory module, or a hybrid of both. The following is combined with… Figure 1Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0011] The memory subsystem can perform multiple parallel operations (e.g., random read, sequential read, random write, sequential write, etc.) involving multiple memory devices with multiple memory dies. The parallel performance of operations involving multiple memory devices leads to higher current and power demands on the power supply, which adversely affects data stability and reliability. To address the power issues arising from overlapping operations, conventional memory devices employ a power budget to set a level or limit within which multiple multi-die memory devices can operate during the execution of concurrent operations. However, this approach results in a predefined power performance level based on the specific memory device design. Therefore, the controller in a conventional system is constrained by the predefined optimal performance level and is forced to limit the number of memory dies that can be active at a given time to perform parallel programming and read operations. Furthermore, conventional power management methods can be implemented by pausing the operation execution algorithm of one or more memory devices in response to identifying overlap of multiple power instances corresponding to concurrently executing memory dies. However, algorithmic pauses that can result in a 5 to 10 microsecond pause are not effective for certain short or fast operations with short execution durations (e.g., fast read operations, single-level cell (SLC) programming operations), resulting in significant performance loss (e.g., approximately 30% performance loss).

[0012] This disclosure addresses the above and other shortcomings through a memory subsystem that selectively configures power mode settings for one or more memory dies within one or more memory packages. The controller of the memory subsystem can switch one or more individual dies or memory packages (e.g., a collection of dies) between multiple power mode configurations by setting one or more parameters corresponding to the power levels of the respective memory dies. The multiple power mode configurations may include a default or medium power mode configuration (e.g., where one or more power mode parameters of the memory die are configured to establish a threshold power level), a low power mode configuration (e.g., where one or more power mode parameters of the memory die are configured to establish a power level below the threshold power level), and a high power mode configuration (e.g., where one or more power mode parameters of the memory die are configured to establish a power level above the threshold power level).

[0013] The memory subsystem controller monitors power budget requests from the host system. In parallel, the controller tracks task requests (e.g., requests for operations) issued by the host system to determine the workload level in the incoming request queue. Based on the task workload level and the type of operation to be issued to the memory dies (e.g., random read, sequential read, random write, sequential write, etc.), the controller determines the number of memory dies to be accessed in parallel (e.g., the number of memory dies to be activated). The controller calculates power levels corresponding to multiple different sets of memory die configurations. Each set of memory die configurations contains the number of memory dies to be activated given the identified workload level and a corresponding power mode (i.e., medium power mode or low power mode) for each of the activated memory dies.

[0014] After determining the power level for each of a plurality of different sets of memory die configurations, the controller selects and implements the desired memory die configuration to perform the identified workload within the constraints of the requested power budget. In one embodiment, the controller may select the desired power mode from a plurality of power modes, including a low-power mode configuration exhibiting power levels below a threshold power level, a medium-power mode configuration exhibiting power levels equal to the threshold power level, and a high-power mode configuration exhibiting power levels above the threshold power level. The desired power mode configuration can be established by sending corresponding commands at the die level (e.g., individually for each die, where dies may be in different packages) or at the package level (e.g., for all dies in a particular package). Each of the power mode configurations (e.g., low, medium, and high power mode configurations) may be defined by a set of corresponding values ​​or ranges of values ​​for one or more parameters that affect the power level associated with the memory die (e.g., internal trim value, latch value, register value, flag value, charge pump voltage level, charge pump clock frequency, internal bias current, charge pump output resistance, operating algorithm (e.g., multi-plane parallel operating algorithm, serialized single-plane operating algorithm, etc.).

[0015] Advantageously, the system according to embodiments of the present disclosure selectively identifies and sets the desired power mode configuration for each memory die to achieve increased throughput and optimized operation execution given the applicable power budget. Furthermore, the system according to embodiments of the present disclosure efficiently manages the power budget for short or fast operations (e.g., fast read operations, SLC programming operations, etc.) with a lower performance penalty (e.g., 1 microsecond penalty) compared to conventional operation pause methods.

[0016] Figure 1This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., storage device 140), one or more non-volatile memory devices (e.g., storage device 130), or a combination of the like.

[0017] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0018] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device that includes memory and processing power.

[0019] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical, optical, magnetic and the like.

[0020] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0021] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110.

[0022] When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 can further utilize the NVM High-Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0023] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0024] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0025] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion, and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0026] While non-volatile memory components such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0027] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include digital circuitry with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0028] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0029] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0030] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry translates commands received from the host system into instructions for accessing the memory device 130 and translates responses associated with the memory device 130 into information for the host system 120.

[0031] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0032] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0033] The memory subsystem 110 includes a power mode management component 113 that monitors operation requests from the host system 120 to determine the workload level in the incoming request queue. Based on the workload level in the incoming request queue, the power mode management component 113 can identify a set of memory dies to be accessed or activated simultaneously to perform the workload. The workload level in the incoming request queue may include the number and type of operations to be performed (e.g., read operations, write operations, random read operations, sequential read operations, etc.). The power mode management component 113 can further determine a power budget level (e.g., the total power level or maximum power level that can be supplied to the one or more active memory dies).

[0034] In one embodiment, the power mode management component 113 selects a power mode configuration for each of the activated memory dies from a set of power mode configurations based on a power budget level, the number of memory dies in the set of memory dies to be activated, and characteristics related to power consumption associated with one or more operations to be performed. In one embodiment, the power mode configuration set may include low power mode configurations, medium power mode configurations, and high power mode configurations. Each of the power mode configurations (e.g., low, medium, and high power mode configurations) is associated with a set of values ​​or ranges of values ​​for one or more parameters for the memory die (e.g., internal trim values, latch values, register values, flag values, charge pump voltage levels, charge pump clock frequencies, internal bias currents, charge pump output resistances, operation algorithms (e.g., multi-plane parallel operation algorithms, serialized single-plane operation algorithms, etc.). The power mode management component 113 can configure the one or more parameters to set values ​​corresponding to the selected power mode configuration to place the memory die in the selected power mode configuration.

[0035] A low-power mode configuration can be established by setting one or more parameters of the memory die to a first set of values, resulting in a power level lower than a threshold power level. A medium-power mode configuration can be established by setting one or more parameters of the memory die to a second set of values, resulting in a power level equal to a threshold power level. A high-power mode configuration can be established by setting one or more parameters of the memory die to a third set of values, resulting in a power level higher than a threshold power level.

[0036] In one embodiment, the first set of parameter values, the second set of parameter values, and the third set of parameter values ​​used to define or establish corresponding low-power mode, medium-power mode, or high-power mode can be preset during the manufacture of the memory device or established by the power mode management component 113.

[0037] After selecting a power mode configuration (e.g., low, normal, or high) for the memory die, the power mode management component 113 configures one or more parameters of the memory die to set the desired power mode configuration. In one embodiment, the power mode management component 113 may configure or set the one or more parameters before or during the execution of the one or more operations. The parameters of the memory die configured to set the selected power mode configuration may include, for example, internal trimming values, latches, registers, flags, charge pump voltage levels, charge pump clock frequencies, internal bias currents, charge pump output resistances, operating algorithms (e.g., multi-plane parallel operation algorithms, serialized single-plane operation algorithms), etc.

[0038] In one embodiment, the power mode management component 113 can individually configure the desired power mode configuration for each memory die (e.g., memory dies located in different memory packages) by sending commands or command sequences (e.g., setting feature command sequences) via a suitable interface (e.g., a flash interface, such as an Open NAND Flash Interface (ONFI)) to set one or more parameters of the memory die.

[0039] In one embodiment, a selected power mode configuration is established for the active memory die set such that the total power associated with the execution of the workload is within or below the power budget. Advantageously, the power mode management component 113 monitors task or workload requests from the host system 120 to determine the workload level in the incoming request queue.

[0040] Figure 2This is a flowchart of an example method 200 for identifying and establishing a desired power mode configuration for one or more memory dies to be simultaneously activated for performing one or more operations requested by a host system. Method 200 may be performed by processing logic that may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 200 is performed by… Figure 1 The power mode management component 113 is executed. Additionally... Figure 3 Example memory subsystem 115 is described, which includes a power mode management component 113 configured to perform the operations of method 200. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0041] like Figure 2 As shown, at operation 210, the processing logic determines the workload level in the incoming request queue based on one or more operations requested by the host system for execution by the memory subsystem. In one embodiment, the workload level represents the number of tasks or operations, the amount of work (e.g., the size of the data payload, the amount of data to be transferred, etc.), and the type of operation requested by the host system associated with one or more memory devices (e.g., read, write, random read, etc.). In one embodiment, the processing logic monitors the one or more requests generated by the host system to determine the workload level in the incoming request queue.

[0042] In one embodiment, the workload level may represent the bandwidth level required by the host system to perform one or more operations. The bandwidth level may be determined based on the one or more requested operations. In one embodiment, the bandwidth level is based on the size of data to be written to or read from the one or more memory devices, given the operation requests in the incoming request queue. For example, the processing logic may determine that the host system requires a sequential read bandwidth level of 2000 MB / s. In one embodiment, the power budget level and bandwidth level may be determined in parallel by monitoring requests from the host system. In another example, the processing logic may determine that the host system requires a sequential write bandwidth level of 900 MB / s.

[0043] like Figure 3As shown, the power mode management component 113 can monitor the incoming request queue 350 to identify the one or more operation requests issued by the host system 120. In one embodiment, the task queue 350 may contain a data structure stored in a storage location (e.g., a cache memory accessible by the memory subsystem controller 115) that stores information related to the one or more operation requests from the host system 120 (e.g., operation type, corresponding bandwidth level, etc.). Figure 3 In this context, the power mode management component 113 can monitor the host system 120 to identify power requests that identify the power budget.

[0044] At operation 220, the processing logic identifies a set of memory dies of a memory subsystem to be activated for performing the one or more operations based on the workload level in the queue. In one embodiment, the processing device calculates the number of memory dies to be activated (e.g., parallel access) based on the workload level in the incoming request queue (e.g., the number of operations to be performed and the one or more types of those operations). In one embodiment, each type of operation (e.g., random read operation, sequential read operation, random write operation, sequential write operation, etc.) may be associated with a corresponding workload or bandwidth level, as characterized by the corresponding power or current consumption associated with the execution of a particular operation type. In one embodiment, the workload level in the incoming request queue represents the number of operations to be performed, and the corresponding operation type is taken into account when calculating the number of memory dies to be activated simultaneously or in parallel to satisfy the workload level (e.g., complete the one or more operations). For example, the number of memory dies used during a sequential read operation may be determined based on the size of the read operation divided by the access cell size of each memory die. In one embodiment, the number of memory dies activated to perform one or more random read operations can be determined based on the number of pending read requests in the queue divided by the total number of memory dies. In another embodiment, the number of memory dies to be activated for sequential writes can be determined based on the system bandwidth detected on the storage interface (e.g., general-purpose flash memory) divided by the bandwidth level of each memory die. Figure 3 In the example shown, the power mode management component 113 can identify a set of memory dies, including memory dies A1, A2, A3...An of memory die package A and memory dies Y1, Y2, Y3...Yn of memory die package Y, to perform operations corresponding to the workload level in the incoming request queue.

[0045] At operation 230, the processing logic determines the power mode configuration of the memory dies for the memory die set based on a power budget level. In one embodiment, the processing logic determines the power budget level by monitoring the host system to identify power budget requests. In one embodiment, the power budget request identifies the level or amount of total power budgeted or allocated to perform the workload level in the incoming request queue. For example, the power budget level may be established as a value of 800mA, such that the execution of the requested operation has a total or current level of 800mA that can be consumed by the concurrently operating memory dies.

[0046] After determining the number of memory dies to be activated (e.g., the number of memory dies to be accessed in parallel to perform the workload level in the incoming request queue), the processing logic may determine which power mode configuration to place each of the active memory dies in, based on the power budget level and the corresponding current level consumed by each memory die when in the respective power mode configuration. Each of the power mode configurations (e.g., low, medium, high) may be associated with a corresponding current level consumed by each memory die when operating in a given power mode configuration. For example, a low power mode configuration may be associated with a current level of 100mA per memory die, a medium power mode configuration may be associated with a current level of 200mA per memory die, and a high power mode configuration may be associated with a current level of 400mA per memory die. In one embodiment, the processing logic determines the number of memory dies to be placed in a power mode configuration based on the corresponding current level for each power mode configuration, such that the total current level of the memory die set is within the power budget level. For example, if the processing logic has a default total system power limit or budget of 800mA, then the processing logic can calculate that two memory dies are to be configured in a high-power mode, four memory dies in a medium-power mode, and eight memory dies in a low-power mode. In one embodiment, the total system power limit can be configured by the end user or configured during operation based on one or more parameters associated with the memory subsystem (e.g., battery level, temperature, etc.).

[0047] like Figure 3 As shown, the power mode management component 113 can identify one of the applicable power mode configurations (e.g., low power mode configuration, medium power mode configuration, and high power mode configuration) at the memory die level or memory die package level for each memory die. As shown, each of the power mode configurations is associated with a corresponding set of parameter values.

[0048] At operation 240, the processing logic configures one or more parameters of the memory die to establish a power mode configuration. In one embodiment, the processing logic sets the one or more parameters of the memory die to a set of values ​​corresponding to a selected power mode configuration. In another embodiment, the processing logic may configure the one or more parameters to a set of values ​​corresponding to a desired power mode configuration. Figure 3 In the example shown, power mode management component 113 may issue a power mode configuration command (e.g., a setting characteristic command) to configure or adjust one or more parameters of a specific memory die (e.g., die A1) to a first set of parameter values ​​to put the memory die in a low-power mode configuration. In one embodiment, as Figure 3 As shown, the power mode management component 113 can issue a power mode configuration command to configure or adjust one or more parameters of a specific memory die (e.g., die A1) to a second set of parameter values ​​to put the memory die in a normal power mode configuration. In one embodiment, as... Figure 3 As shown, the power mode management component 113 can issue a power mode configuration command to configure or adjust one or more parameters of a specific memory die (e.g., die A1) to a third set of parameter values ​​so that the memory die is in a high power mode configuration.

[0049] In one embodiment, the processing logic can configure the memory die to be in a low-power mode configuration (i.e., a transition from a normal power mode configuration) by issuing a sequence of commands to set one or more of the values ​​of internal trimmers, latches, registers, flags, etc., to a first set of values ​​to indicate a power reduction requirement during operation. In one embodiment, the processing logic can configure the memory die to be in a low-power mode configuration by configuring one or more of the following parameters to correspond to the first set of parameter values: configuring the charge pump to a lower output voltage, slowing down the charge pump clock frequency, limiting the internal bias current, increasing the charge pump output resistance, changing the operating algorithm (e.g., switching from multi-plane parallel operation to serialized single-plane operation), etc.

[0050] In one embodiment, the memory die may be configured to default to a medium power mode (e.g., the default parameter values ​​correspond to a second set of parameter values). In one embodiment, processing logic may configure the memory die to a low power mode configuration (i.e., a transition from a normal power mode configuration) by issuing a sequence of commands to configure one or more of the values ​​of internal trimmers, latches, register flags, etc., to a first set of values ​​to reduce the power level during operation (e.g., compared to a threshold power level associated with a medium or default power mode configuration). In one embodiment, processing logic may configure the memory die to a low power mode configuration by configuring one or more of the following parameters to correspond to the first set of parameter values: setting the charge pump to a lower output voltage, slowing down the charge pump clock frequency, limiting the internal bias current, increasing the charge pump output resistance, changing the operating algorithm (e.g., switching from multi-plane parallel operation to serialized single-plane operation), etc.

[0051] In one embodiment, the processing logic can put the memory die in a high-power mode configuration (i.e., a transition from a normal power mode configuration) by issuing a sequence of commands to configure one or more of the values ​​of internal trimmers, latches, register flags, etc., to a third set of values ​​to increase the power level during operation (e.g., compared to a threshold power level associated with a medium or default power mode configuration). In one embodiment, the processing logic can put the memory die in a high-power mode configuration by configuring one or more of the following parameters to correspond to a third set of parameter values: setting the charge pump to a higher output voltage, accelerating the charge pump clock frequency, increasing the internal bias current, decreasing the charge pump output resistance, changing the operating algorithm (e.g., switching from serialized single-plane operation to multi-plane parallel operation), etc.

[0052] Figure 4 The description includes a table of instances of power mode configurations established by the processing device based on the workload level in the identified incoming request queue, the set of memory dies to be activated, and the power budget. Figure 4 In the example shown, the processing logic can position the memory die in one of three power mode configurations: a low power mode configuration with a per-memory die current level of 100mA, a medium power mode configuration with a per-memory die current level of 200mA, and a high power mode configuration with a per-memory die current level of 400mA.

[0053] exist Figure 4In one example shown, the processing logic determines the workload level in an incoming request queue of thirty-two operations. Based on the workload level in the incoming request queue, the processing logic determines to activate a set of eight memory dies to execute the workload level. Given a power budget of 800mA, the processing logic determines to configure the eight memory dies in a low-power mode. In this example, configuring the eight memory dies in a low-power mode enables the execution of the workload level in the incoming request queue within the identified power budget.

[0054] exist Figure 4 In another example shown, the processing logic determines the workload level in the incoming request queue of eight operations. Given the workload level in the incoming request queue, the processing logic determines to activate a set of four memory dies to execute the workload level. Given a power budget of 800mA, the processing logic determines to place the four memory dies in a normal power mode configuration. In this example, placing the four memory dies in a normal power mode configuration enables the execution of the workload level in the incoming request queue within the identified power budget, while optimizing the power mode configuration for the set of memory dies (e.g., placing the set of memory dies in a power mode configuration with the highest applicable setting (e.g., normal) given the workload level and power budget).

[0055] exist Figure 4 In another example shown, the processing logic determines the workload level in the incoming request queue of an operation. Given the workload level in the incoming request queue, the processing logic determines to activate a set of memory dies to perform the workload level. Given a power budget of 800mA, the processing logic determines to put one memory die in a high-power mode configuration. In this example, putting the activated memory die in a high-power mode configuration enables the workload level in the incoming request queue to be performed within the identified power budget, while optimizing the power mode configuration for the set of memory dies (e.g., putting one memory die in a power mode configuration with the highest applicable setting given the workload level and power budget).

[0056] In one embodiment, the power mode configuration may be one of a low power mode configuration, a medium power mode configuration, and a high power mode configuration. In one embodiment, each of the applicable power mode configurations (e.g., low, medium, and high) is associated with a corresponding set of memory die parameter values ​​(or value ranges). In one embodiment, the low power mode configuration is associated with a first set of parameter values, the medium power mode configuration is associated with a second set of parameter values, and the high power mode configuration is associated with a third set of parameter values. In one embodiment, the different power mode configurations and corresponding parameter value sets may be predefined, such that processing logic can identify the set of values ​​corresponding to the desired power mode configuration. The multiple different power mode configurations represent the relative power levels consumed by each in the memory die when activated during the execution of the corresponding operation.

[0057] Figure 5 This describes a table illustrating instances of power mode configurations established by the processing device based on embodiments of the present disclosure, considering the identified workload level in the incoming request queue represented by the requested operation type and the corresponding bandwidth level requirements. Figure 5 In one example shown, the host system may issue a request for a sequential read operation, requiring a bandwidth level of 2000 MB / s with an 800 mA power budget. The power mode component 113 can determine the workload level in the incoming request queue of thirty-two read commands and calculate which eight memory dies should be activated to serve the 2000 MB / s bandwidth level, where each memory die has a read throughput of 250 MB / s. In one embodiment, a set of eight memory dies is identified for activation to perform read operations in parallel. To meet the 800 mA power budget, the power mode component 113 may configure six of the eight active memory dies in a low-power mode configuration and the remaining two active memory dies in a medium-power mode configuration.

[0058] exist Figure 5 In another example shown, the host system may issue a request for a sequential write operation, requiring a bandwidth level of 1000 MB / s with an 800 mA power budget. The power mode component 113 can determine the workload level in the incoming request queue of eight 128 kB write commands and identify the set of four memory dies to activate for sequential write operations, since in this example each memory die can handle 32 kB. To meet the 800 mA power budget and optimize power performance, the power mode component 113 can configure all four active memory dies in a medium power mode configuration.

[0059] exist Figure 5In another example shown, the host system may issue a request for a sequential read operation, requiring a bandwidth level of 100 MB / s with a 400 mA power budget. In this example, the power mode component 113 may determine the workload level in the incoming request queue of a large write operation and identify a set of memory dies to activate for sequential write operations, since the large write operation has low throughput requirements and can be served by a memory die with a throughput of 250 MB / s. To meet the 400 mA power budget and optimize power performance, the power mode component 113 may configure the active memory die in a high-power mode configuration.

[0060] Figure 6 An example machine illustrating computer system 600 is described, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein is executable. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., to execute the operating system to perform operations corresponding to...). Figure 1 (Operation of the power mode management component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0061] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch or bridge, or non-digital circuit system, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be considered to include any collection of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0062] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0063] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0064] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) storing one or more instruction sets 626 or software embodying any or more of the methods or functions described herein. Instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0065] In one embodiment, instruction 626 includes implementing a data protection component (e.g., Figure 1 The power mode management component 113) contains functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0066] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0067] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0068] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions and each coupled to a computer system bus.

[0069] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0070] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0071] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method comprising: The processing unit of the memory subsystem determines the workload level in the incoming request queue based on one or more operations requested by the host system for the memory subsystem to perform; Based on the workload level in the incoming request queue, identify the set of memory dies of the memory subsystem to be activated for performing the one or more operations. The power mode configuration for the memory die set is selected from a set of power mode configurations based on the power budget level, wherein each power mode configuration in the set of power mode configurations corresponds to a different power consumption level; Identify the set of parameter values ​​associated with the power mode configuration; as well as The processing device issues one or more commands to the memory die, causing the parameter set of the memory die to be adjusted to the parameter value set, thereby putting the memory die into the power mode configuration.

2. The method according to claim 1, wherein the power mode configuration set includes a low power mode configuration, a medium power mode configuration, or a high power mode configuration.

3. The method of claim 2, wherein the first power consumption level corresponding to the low power mode configuration is lower than the second power consumption level corresponding to the medium power mode configuration; and wherein the third power consumption level corresponding to the high power mode configuration is higher than the second power consumption level corresponding to the medium power mode configuration.

4. The method of claim 1, wherein the one or more parameters of the memory die are adjusted to a set of parameter values ​​corresponding to the high-power mode configuration to establish the high-power mode configuration.

5. The method of claim 1, wherein the set of parameter values ​​includes one of the following: an internal trim value, a latch value, a register value, a flag value, a charge pump voltage level, a charge pump clock frequency, an internal bias current, or a charge pump output resistance.

6. The method of claim 1, further comprising selecting one of a low-power mode configuration, a medium-power mode configuration, or a high-power mode configuration for each memory die in the set of memory dies.

7. The method of claim 1, wherein the workload level in the incoming request queue is determined at least in part based on the type of the one or more operations and the bandwidth level corresponding to the execution of the one or more operations.

8. A non-transitory computer-readable medium including instructions that, when executed by a processing means, cause the processing means to perform operations including: The workload level in the incoming request queue is determined based on one or more operations requested by the host system for execution by the storage subsystem. Based on the workload level in the incoming request queue, identify the set of memory dies of the memory subsystem to be activated for performing the one or more operations. Identify the first set of parameter values ​​associated with the low-power mode configuration associated with the first power consumption level; One or more first commands are issued to a first portion of the memory die set, such that one or more parameters of the first portion of the memory die set are adjusted to a first set of parameter values ​​corresponding to the low power mode configuration selected from the power mode configuration set; Identify the set of second parameter values ​​associated with the high-power mode configuration associated with the second power consumption level; and One or more second commands are issued to a second portion of the memory die set, such that one or more parameters of the second portion of the memory die set are adjusted to a set of second parameter values ​​corresponding to the high-power mode configuration selected from the power mode configuration set.

9. The non-transitory computer-readable medium of claim 8, wherein configuring the one or more parameters to the second set of parameter values ​​includes at least one of the following: setting the charge pump to a higher output voltage, accelerating the charge pump clock frequency, increasing the internal bias current, decreasing the charge pump output resistance, or changing from serialized single-plane operation to multi-plane parallel operation.

10. The non-transitory computer-readable medium of claim 8, wherein the second power consumption level associated with the high-power mode configuration is higher than a threshold power level.

11. The non-transitory computer-readable medium of claim 8, the operation further comprising establishing at least an additional portion of the memory die set as a medium-power mode configuration.

12. The non-transitory computer-readable medium of claim 8, wherein the operation further comprises: Identify power budget levels; as well as The second portion of the memory die set is configured to be in the high-power mode, at least in part based on the power budget level.

13. The non-transitory computer-readable medium of claim 8, wherein the operation of at least the memory die set in the high-power mode configuration produces a power level within a power budget level.

14. A system comprising: Memory devices; as well as A processing device operatively coupled to the memory device, the processing device performing operations including the following: The processing unit determines the workload level in the incoming request queue based on one or more operations requested by the host system for execution by the memory subsystem; Based on the workload level in the incoming request queue, identify the set of memory dies of the memory subsystem to be activated for performing the one or more operations. The power mode configuration for the memory die set is selected from a set of power mode configurations based on the power budget level, wherein each power mode configuration in the set of power mode configurations corresponds to a different power consumption level; Identify the set of parameter values ​​associated with the power mode configuration; as well as One or more commands are issued to the memory die to adjust the set of parameters of the memory die to the set of parameter values, thereby putting the memory die into the power mode configuration.

15. The system of claim 14, wherein the power mode configuration set includes a low power mode configuration, a medium power mode configuration, or a high power mode configuration.

16. The system of claim 15, wherein a first power consumption level corresponding to the low power mode configuration is lower than a second power consumption level corresponding to the medium power mode configuration; and wherein a third power consumption level corresponding to the high power mode configuration is higher than the second power consumption level corresponding to the medium power mode configuration.

17. The system of claim 14, wherein the one or more parameters of the memory die are configured to a set of parameter values ​​corresponding to a high-power mode configuration to establish the high-power mode configuration.

18. The system of claim 14, wherein the one or more parameters correspond to one or more of the following: internal trim value, latch value, register value, flag value, charge pump voltage level, charge pump clock frequency, internal bias current, or charge pump output resistance.

19. The system of claim 14, the operation further comprising determining one of a low-power mode configuration, a medium-power mode configuration, or a high-power mode configuration for each memory die in the set of memory dies.

20. The system of claim 14, wherein the workload level in the incoming request queue is determined at least in part based on the type of the one or more operations and the bandwidth level corresponding to the execution of the one or more operations.

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