Architecture for fast content addressable memory search

Abstract

A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a first set of signals representing the input search word and a second set of signals representing a second sequence of bits comprising a complement of the first sequence of bits. The search pattern is provided as input to a search line of a content addressable memory (CAM) block. The search pattern causes at least one string in the CAM block to conduct, and a signal is provided to a page buffer connected to the string in response to the input search word matching a data entry stored on the string. A location of the data entry is determined based on data read from the page buffer, and the location is output.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Application No. 16 / 727,671, filed December 26, 2019, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to memory device architectures for facilitating fast content-addressable memory (CAM) search. Background Technology

[0004] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Attached Figure Description

[0005] This disclosure will be more fully understood from the embodiments given below and from the accompanying drawings of various embodiments thereof.

[0006] Figure 1 Examples of computing systems including a content-addressable memory (CAM) architecture implemented within a memory subsystem are shown according to some embodiments of the present disclosure.

[0007] Figure 2 A block diagram illustrating additional details of a CAM architecture implemented within a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 3 The present disclosure illustrates components of a CAM block implemented in an exemplary form of a NAND flash memory device according to some embodiments of the present disclosure.

[0009] Figure 4 A single CAM cell is shown as an implementation of a CAM block within a NAND flash memory device according to some embodiments of the present disclosure.

[0010] Figure 5 To illustrate a block diagram of a shift register according to some embodiments of the present disclosure, the shift register may be a portion of a CAM architecture.

[0011] Figure 6 A flowchart illustrating an instance operation of a memory subsystem performing a CAM search according to some embodiments of the present disclosure.

[0012] Figure 7This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0013] This disclosure relates to content-addressable memory (CAM) architectures for memory subsystems. The memory subsystem can be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request retrieval of data from the memory subsystem. The memory subsystem controller typically receives commands or operations from the host system and can translate these commands or operations into instructions or suitable commands to achieve the desired access to the memory components of the memory subsystem.

[0014] Content-addressable memory (CAM) is a specific type of memory device used in certain extremely high-speed search applications, such as identifier (ID) and pattern matching. Typically, CAM is searched by comparing input search data with a table of stored data entries and returning the memory address of the data matching the table. CAM is frequently implemented in dynamic random access memory (DRAM) or synchronous random access memory (SRAM). However, both DRAM and SRAM have limited memory capacity, which limits the amount of data that can be stored and searched in conventional CAM implementations.

[0015] Conventional NAND flash memory devices may include one or more blocks. A NAND block comprises a two-dimensional (2-D) array, which includes pages (rows) and strings (columns). A three-dimensional (3D) NAND flash memory device comprises multiple planes, each of which includes one or more blocks. A string comprises multiple individual NAND flash cells (hereinafter also simply referred to as "memory cells") connected in series. An individual NAND flash cell includes transistors that store charge on a memory layer isolated by upper and lower oxide insulating layers. Generally, when a charge is present on the memory layer of a memory cell, the memory cell is programmed and identified by the memory subsystem as a binary value of 0. When the memory layer of a memory cell is not charged, it is erased and identified as a binary value of 1.

[0016] A string is a unit in a NAND flash memory device. NAND flash components typically have 32 or more memory cells. Conventionally, each memory cell is used to represent a bit value (0 or 1). Therefore, in a conventional implementation, a string with 32 memory cells can represent 32 bits of data, and a string with 64 memory cells can represent 64 bits of data.

[0017] In a NAND flash memory block, individual strings are connected to allow storage and retrieval of data from selected cells. Typically, one end of a string in the block is connected to a common source line, and the other end is connected to a bit line. Each string also contains two control mechanisms connected in series with the memory cell. String select transistors and ground select transistors are connected to the string select line and the ground select line, respectively. Memory cells in a NAND flash assembly are horizontally connected to word lines at their control gates to form pages. A page is a group of connected memory cells sharing the same word line and is the smallest unit of programming. NAND flash memory devices can have page sizes of 64K or 128K cells. While conventional NAND flash memory offers larger capacities compared to DRAM and SRAM, it is generally too slow for serial data search and access.

[0018] The aspects of this disclosure address the aforementioned and other problems of the CAM architecture implemented in NAND flash memory devices to simultaneously provide fast and high-capacity search capabilities. According to this architecture, data entries are stored on strings in a NAND flash memory array. In contrast to conventional NAND implementations, each bit of a data entry is mapped to a pair of memory cells configured as complements. That is, the first memory cell of the pair stores the bit value, and the second memory cell of the pair stores the inverse of the bit value. A search pattern representing an input search word is vertically input onto each word line corresponding to a string in the array. A single read operation compares the input search word with all strings in the array and identifies the storage address of matching data.

[0019] The NAND-based CAM architecture described in this article enables new applications requiring high-speed and high-density pattern matching, such as those related to artificial intelligence, machine vision, and large genetic databases. This type of CAM architecture also improves existing database search systems and algorithms, such as cloud networking and index storage in servers.

[0020] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0021] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include SSDs, flash drives, Universal Serial Bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer contained in a vehicle, industrial equipment or a commercially available connected device), or such a computing device that includes memory and processing means (e.g., a processor).

[0023] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0024] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0025] Host system 120 may be coupled to memory subsystem 110 via a physical host interface, Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple independent communication connections, and / or combinations of communication connections.

[0026] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0027] Some examples of non-volatile memory devices (such as memory device 130) include NAND-type flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Each memory device 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), stores one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), store multiple bits per cell. In some embodiments, each memory device 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0029] Although non-volatile memory devices, such as NAND flash memory (e.g., 2D NAND, 3D NAND) and 3D cross-point non-volatile memory cell arrays, are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0030] As shown, any one or more of the memory devices 130 may be configured to include one or more content-addressable memory (CAM) blocks 112. CAM block 112 includes one or more arrays of memory cells organized as strings. Each string stores data entries and includes memory cells connected in series between a match line and a page buffer. That is, CAM block 112 includes multiple match lines, and each match line is connected to one of the multiple strings in the array. The match lines of CAM block 112 correspond to the bit lines of the NAND block on which CAM block 112 is implemented. Within a given string, memory cells are organized into complementary memory cell pairs. Each bit value of a data entry stored in a string maps to one of the complementary memory cell pairs in the string.

[0031] The CAM block 112 can be searched by providing a search pattern as input to the search lines of the CAM block 112. The search lines of the CAM block 112 correspond to the word lines of the NAND block on which the CAM block 112 is implemented. The matching lines of the CAM block 112 are pre-charged to facilitate the search. That is, a voltage signal is applied to the matching lines of the CAM block 112 before the search is input. During the search operation, if the input search word matches any data entry stored by the CAM block 112, one or more matching lines (e.g., matching lines corresponding to the string storing the matching data entry) become conductive and release signals in response to the search pattern input at the search line. If the search word does not match any stored entry, all matching lines become deconductive. Each matching line is further connected to a page buffer (e.g., including one or more latching circuits), which receives the discharge signal and stores data indicating matching data stored along the connected matching lines.

[0032] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading, writing, or erasing data and other such operations performed at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0034] In some embodiments, local memory 119 may include memory registers storing memory pointers, acquired data, etc. Local memory 119 may also include ROM for storing microcode. Although Figure 1 The instance memory subsystem 110 has been shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0037] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with a memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] The memory subsystem 110 also includes a search component 113 that facilitates the search of the CAM block 112. According to some embodiments, the search component 113 is included in the memory device 130, as shown. In some embodiments, the controller 115 includes at least a portion of the search component 113. For example, the controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119 for performing the operations of the search component 113 described herein. In some embodiments, the search component 113 is part of the host system 120, an application, or an operating system.

[0039] Search component 113 generates a search pattern based on the received input search word and vertically inputs the search pattern along the search line of CAM block 112. If a data entry matching the input search word is stored by CAM block 112, the search pattern makes the matching line (also referred to as the "matched line") storing the data entry conductive, and because the matching line is pre-charged, the matched line provides a signal indicating where the search word is stored to the connected page buffer. The location (e.g., storage address) of any matching data entry can be identified based on the signal provided by the matched line due to the string becoming conductive. More specifically, the page buffer connected to any matched line stores data in response to detecting a discharge signal indicating that the matching data is stored along the matched line. Components of search component 113 (e.g., readout circuitry) can read data from the page buffer. Based on the data read from the page buffer, search component 113 outputs an indication of whether the search word is stored by CAM block 112 and an indicator of the location of the matching line.

[0040] Figure 2 A block diagram illustrating additional details of a CAM architecture implemented within a memory subsystem 110 according to some embodiments of the present disclosure. (See diagram below.) Figure 2 As shown, memory device 200 can be organized into multiple planes, namely planes 201-1 to 201-4. Memory device 200 is an example of one of memory devices 130. Although Figure 2 The memory device 200 is shown as comprising four planes, but it should be understood that the memory device 200 is not limited to four planes, and in other embodiments may include more or fewer planes. Each of the planes 201-1 to 201-4 is configured to include one or more CAM blocks 112. The number of CAM blocks 112 per plane may be configured via software or hardware.

[0041] As shown, search component 113 receives input search word 206 and generates search pattern 208 based on input search word 206. Input search word 206 includes a first bit sequence (e.g., "1011"). Search pattern 208 generated by search component 113 includes a first set of voltage signals 209A (SL) representing the input search word. 0-M ), and the second set of voltage signals 209B representing the second bit sequence. The second bit sequence includes the inverse of the first bit sequence (e.g., "0100"). The search component 113 includes an inverter 210 for generating the inverse of the input search word and a level selector 211 for generating the first and second signals. The level selector 211 can use voltage V when generating the first and second voltage signals. high To represent the binary value "1", and using voltage V low To represent the binary value "0", where V highAbove the threshold voltage (Vt) and V low Below the threshold voltage.

[0042] To search for one of the CAM blocks 112, the search component 113 vertically inputs search mode 208 along the search line of the CAM block 112 being searched. The input of search mode 208 causes any complementary memory cell pairs representing the stored bit values ​​of the match to become conductive. If the string is storing matching data, then the entire string becomes conductive. The matching line in the CAM block 112 is pre-charged (e.g., connected to V). high Since the matching lines are pre-charged, input to search mode 208 on the search lines causes any matching line storing matching data (e.g., the same data entry as search word 206) in the block to output a discharge signal, because the corresponding string is conductive. The discharge signal provides an indication that matching data (e.g., input search word 206) is stored thereon. The discharge signal provides an indication that the matching data is stored on the string connected to the matching lines.

[0043] Each string is connected between a match line and a page buffer (e.g., including one or more latching circuits), and the page buffer of the match line stores data indicating that match data is stored along the match line in response to a signal provided by the match line discharging along the string. As shown, plane 201-4 includes page buffer 212. Page buffer 212 may include one or more latching circuits. Physically, page buffer 212 resides below or near the memory cell array in which CAM block 112 is implemented. When match data is stored by the connected string that conducts signals to page buffer 212, page buffer 212 latches the data based on the signal provided by the match line. Search component 113 reads data from page buffer 212 and provides an input search word 206 as an indicator of whether it is stored in one of the CAM blocks 112 being searched, along with the location of the match data (e.g., the memory address of the string in the array) as output.

[0044] In some embodiments, the search component 113 may sequentially search for matching data in CAM blocks 112 of planes 201-1 to 201-4. That is, the search component 113 may initially search for CAM blocks 112 of plane 201-1, then search for CAM blocks 112 of plane 201-2, then search for CAM blocks 112 of plane 201-3, and finally search for CAM blocks 112 of plane 201-4.

[0045] In some embodiments, the search component 113 can search for matching data in parallel across the CAM blocks 112 of planes 201-1 to 201-4. That is, the search component 113 can simultaneously search all CAM blocks 112 of planes 201-1 to 201-4 to find matching data. Parallel searching of planes 201-1 to 201-4 allows all data entries stored in all CAM blocks 112 of planes 201-1 to 201-4 to be searched in a single search operation, rather than completing the search for all data entries in four separate search operations. Therefore, the parallel search utilized in the embodiments described above allows the search component 113 to achieve a faster search speed compared to embodiments utilizing sequential searching.

[0046] In some embodiments, data entries may be stored on two or more of planes 201-1 to 201-4. In these cases, search component 113 may simultaneously search for portions of matching data on two or more of planes 201-1 to 201-4. Dividing data entries across planes enables larger word lengths compared to embodiments where data entries are stored within a single plane. For example, if each of the CAM blocks 112 supports 64-bit words, then dividing data entries across all four planes would allow memory device 200 to support 256-bit words (4 * 64 = 256).

[0047] To avoid confusion between the subject matter of this invention and unnecessary details, it has been... Figure 2 Various functional components not closely related to conveying the subject matter of the invention have been omitted. However, those skilled in the art will readily recognize that various additional functional components may be included as part of the memory subsystem 110 to facilitate additional functionality not specifically described herein. For example, the memory subsystem 110 may include additional circuitry (e.g., one or more multiplexers) that allows conventional read and write operations to be performed relative to any one or more of the memory devices 130.

[0048] Figure 3 Components of a CAM block 300 implemented in an exemplary form of a NAND flash memory device according to some embodiments of the present disclosure are shown. CAM block 300 is an example of CAM block 112.

[0049] As shown, CAM block 300 includes mating lines 302-0 to 302-N, search lines 304-0 to 304-M, and reverse search lines 306-0 to 306-M. In this embodiment, the mating lines 302-0 to 302-N of CAM block 300 correspond to the bit lines of a NAND flash memory device, and the search lines 304-0 to 304-M and the reverse search lines 306-0 to 306-M of CAM block 300 correspond to the word lines of a NAND flash memory device.

[0050] Each of the matching lines 302-0 to 302-N is connected to a string comprising multiple memory cells connected in series. For example, matching line 302-0 is connected to a string comprising memory cells 308-0 to 308-X, where X = 2M. The memory cells in each string of CAM block 300 are configured as complementary pairs. For example, when the string is connected to matching line 302-0, memory cells 308-0 to 308-X are programmed as complementary memory cell pairs 310-0 to 310-M.

[0051] The memory cells are configured to be complementary because one memory cell in the pair stores a data value ("0"), and the other memory cell in the pair stores the complement ("1") of the data value. For example, such as Figure 4 As shown, memory cell pair 310-0 (CAM cell) includes two memory cells 308-0 and 308-1. Memory cell 308-0 stores the data bit value DATA, and memory cell 308-1 stores the inverse of the data bit value DATA. Furthermore, as shown in the figure, search line 304-0 is connected to the control gate of memory cell 308-0, and reverse search line 306-0 is connected to the control gate of memory cell 308-1.

[0052] Search line 304-0 receives a first signal SL representing the search bit value from the input search word, and reverse search line 306-0 receives a second signal representing the inverse code of the search bit value. If SL matches DATA and and If a match is found, the memory cell pair 310-0 will change from conductivity condition A to conductivity condition B. For example, Table 1 provided below is a truth table defining the behavior of any given memory cell pair from 310-0 to 310-M.

[0053]

[0054] Table 1

[0055] In Table 1, "SL" is the search position value. It is the inverse complement of the search bit value, where "DATA" is the stored bit value, and It is the complement of the stored bit value. As shown in the figure, the complementary cell pair is conductive when the search data value matches the stored data value and the complement of the search data value matches the complement of the stored data value. In other cases, the memory cell pair 310 is not conductive because the stored data does not match the search bit.

[0056] Return to Figure 3 Each string in CAM block 300 stores a data entry and maps each data bit value in the data entry to one of the memory cell pairs 310-0 to 310-M in the string. In this way, in each of the complementary memory cell pairs 310 in the string, the first memory cell stores the bit value from the data entry, and the second memory cell stores the inverse code of the bit value from the data entry.

[0057] In one example where the NAND flash memory device supports a 128-bit string (i.e., X is 128), the matching line 302-0 is connected to memory cells 308-0 to 308-127, which store bit values ​​including D. 0,0 -D 63,63 A 64-bit data entry. In this example, the bit value D... 0,0 Mapped to memory cell pair 310-0, which includes memory cells 308-0 and 308-1. More specifically, memory cell 308-0 stores bit value D. 0,0 Furthermore, complementary memory cell 308-1 stores the bit value D. 0,0 one's complement

[0058] Search mode 312 can be vertically input along search lines 304-0 to 304-M and reverse search lines 306-0 to 306-M. More specifically, search lines 304-0 to 304-M receive the first set of voltage signals SL representing search word 206. 0-M Furthermore, the reverse search lines 306-0 to 306-M receive the second set of voltage signals representing the inverse code of the search word. Entering search mode 312 along the search line makes any string storing matching data conductive, because, as discussed above, each individual memory cell pair 310 in the string will be conductive. Since the matching line 302 is pre-charged, the conductive string allows the matching line 302 to discharge. Page buffer 212 connected to the conductive string latches data indicating the position of the matching data (i.e., search word 206) in CAM block 300.

[0059] Search component 113 outputs an indication of whether search word 206 is stored in CAM block 300 and an indicator of the location (e.g., memory address) of matching data. In some embodiments, search component 113 includes readout circuitry that reads data from page buffer 212 of CAM block 300 to identify the location of the data.

[0060] In some embodiments, the two page buffers 212 in CAM block 300 may be bound together to form a serial shift register. According to these embodiments, search component 113 shifts data from the first page buffer to the second page buffer, and search component 113 includes an output compare and counter component to track the number of shifts from one page buffer 210 to the other page buffer to identify the location of matching data stored in CAM block 300.

[0061] In some embodiments, two page buffers can be bonded together using a single transistor to form a shift register. For example, such as Figure 5 As shown, the shift register 500 includes page buffer 502 and page buffer 504 connected by transistor 506.

[0062] Figure 6 This is a flowchart illustrating an example method 600 for searching CAM components in a memory subsystem 110 according to some embodiments of the present disclosure. Method 600 may be performed by processing logic that may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing means), or a combination thereof. In some embodiments, it is performed by... Figure 1 The search component 113 executes method 600. Although the processes are shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all operations are required in every embodiment. Other process flows are possible.

[0063] At operation 605, the processing device receives an input search word. The input search word may be received from a host system (e.g., host system 120). The input search word includes a first M-bit sequence (e.g., "100110101011").

[0064] At operation 610, the processing device generates a search pattern based on an input search word. The search pattern includes a first set of voltage signals representing the search word. That is, the first set of voltage signals represents a first M-bit sequence. The search pattern further includes a second set of voltage signals representing a second M-bit sequence, the second M-bit sequence including the inverse of the first bit sequence (e.g., "0110 01010100"). Therefore, when generating the search pattern, the processing device generates the second bit sequence by inverting the input search word and converts the first bit sequence and the second bit sequence into the first set of voltage signals and the second set of voltage signals, respectively. Alternatively, the processing device can generate a first signal based on the first bit sequence and generate the second signal by generating the inverse of the first signal. When generating the first and second voltage signals, the processing device can use a voltage V. high To represent the binary value "1" and using voltage V low To represent the binary value "0", where V high Above the threshold voltage (Vt) and V low Below Vt.

[0065] At operation 615, the processing device provides a search mode to the search lines of the CAM block. The CAM block includes an array of memory cells (e.g., a NAND flash memory array). The array includes multiple strings, and each of the multiple strings stores a data entry. Each string includes multiple memory cells connected in series between a precharge match line and a page buffer. The match line is precharged because it is connected to a voltage signal (e.g., indicating a logic high state). The CAM block further includes multiple search lines, and each memory cell in the string is connected to one of the multiple search lines.

[0066] As mentioned above, the memory cells in each string are organized as complementary memory cell pairs. Each bit value of a data entry stored in the string is mapped to a complementary memory cell pair in the string. Specifically, the first memory cell stores the bit value, and the second memory cell stores the inverse of the bit value. More precisely, the first memory cell stores a first charge representing the bit value, and the second memory cell stores a second charge representing the inverse of the bit value.

[0067] When providing a search mode to the search line of the CAM, the processing device provides a first signal representing the search bit value from the first bit sequence to the first search line connected to the first memory cell in the complementary memory cell pair, and provides a second search signal representing the inverse code of the search bit value to the second search line connected to the second memory cell in the complementary memory cell pair.

[0068] If the input search word is stored in the CAM block, then the input of the search mode makes the string on which the input search word is stored conductive. Since the matched line is pre-charged, the conductive string allows the matched line to discharge. That is, the string conducts a signal generated by the matching line discharge based on the matching of the input search word with the data entry stored on the string connected to the matched line. The conductive string provides the signal to a page buffer connected at the other end of the string. The page buffer latches data in response to the signal provided by the matching line discharge. The latched data instructs the matched line connected to the page buffer to store the same data entry as the input search word.

[0069] The processing unit determines whether any matching data is stored by the CAM block (at operation 630). The processing unit can determine whether any matching data is stored by the CAM block by reading data from the page buffer of the CAM block.

[0070] At operation 625, the processing device determines the location of any matching data stored in the CAM block. That is, the processing device determines the location of the stored data entry that is identical to the input search word. The processing device may determine the location of the matching data based on data read from the page buffer. The location of the matching data may include one or more memory addresses corresponding to one or more strings within the array.

[0071] At operation 630, the processing device outputs an indication of whether the matching data is stored by the CAM block and the location of the matching data. The location of the matching data can, for example, be used to retrieve additional data associated with the input search word stored by the memory subsystem. The associated data can be stored in different parts of the memory device on which the CAM block is implemented or on another memory device of the memory subsystem.

[0072] Example

[0073] Example 1 is a system comprising: a memory device including a content-addressable memory (CAM) block, the CAM block including an array of memory cells organized into multiple strings, one of the strings storing data entries, each string including multiple memory cells connected in series between a precharge match line and a page buffer, each of the memory cells being connected to one of a plurality of search lines; and a processing means coupled to the memory device, the processing means being configured to perform operations including: generating a search pattern based on an input search word including a bit sequence; providing the search pattern as input to the plurality of search lines, the search pattern making the string conductive, and providing a signal to the page buffer in response to the input search word matching a data entry stored on the string, the signal being generated by discharging the precharge match line, the page buffer storing data based on the signal; and outputting the position of the data entry within the CAM block based on the data stored by the page buffer.

[0074] In Example 2, the multiple memory cells of Example 1 are optionally configured as multiple complementary memory cell pairs, and the bit values ​​of data entries are mapped to one of the multiple complementary memory cell pairs.

[0075] In Example 3, the object of any of Examples 1 and 2 optionally includes a pair of complementary memory cells, comprising: a first memory cell storing bit values ​​of data entries, and a second memory cell connected in series with the first memory cell, the second memory cell storing the inverse of the bit values, wherein a first search line of a plurality of search lines is connected to the first memory cell; and wherein a second word line of a plurality of word lines is connected to the second memory cell.

[0076] In Example 4, the object of any of Examples 1 to 3 optionally includes: a first search line that receives a first search signal representing a search bit value from an input search word; and a second search line that receives a second search signal representing the inverse of the search bit value.

[0077] In Example 5, the object of any of Examples 1 to 4 optionally includes determining whether the input search word is stored by the CAM block based on the data stored by the page buffer; and an indication of whether the output input search word is stored by the CAM block.

[0078] In Example 6, the object of any of Examples 1 to 5 optionally includes data read from the page buffer, the data indicating the location of the string.

[0079] In Example 7, the subject matter of any of Examples 1 to 6 optionally includes a system, which further includes: a shift register including a page buffer, a second page buffer and a transistor connected between the page buffer and the second page buffer, the shift register being used to serially shift data out of the page buffer; and a counter being used to determine the position of the matching line by counting the number of shifts performed to serially shift data out of the page buffer.

[0080] In Example 8, the input search word includes a first bit sequence, the search mode includes a first set of signals representing the input search word and a second set of signals representing a second bit sequence, the second bit sequence including the inverse of the first bit sequence, and the object of any of Examples 1 to 7 optionally includes: an inverter for generating the second bit sequence based on the input search word; and a level shifter for generating a first signal based on the first bit sequence and a second signal based on the second bit sequence.

[0081] In Example 9, the location of a data entry in any of Examples 1 through 8 may optionally include the memory address of the string within the CAM block.

[0082] In Example 10, the memory device of any of Examples 1 to 9 optionally includes a NAND flash memory device.

[0083] Example 11 is a method comprising: receiving an input search word comprising a bit sequence via at least one hardware processor; generating a search pattern based on the input search word via at least an inverter and a level selector; providing the search pattern as input to a search line of a content-addressable memory (CAM) block, the search pattern causing at least one string in the CAM block to conduct electricity, and providing a signal to a page buffer connected to the string in response to the input search word matching a data entry stored in the string, the signal being generated by a precharged match line discharging along the string; and outputting the position of the data entry within the CAM block based on data read from the page buffer connected to the string, the page buffer storing the data based on the signal generated by the precharged match line discharging along the string.

[0084] In Example 12, the plurality of memory cells in Example 11 are optionally configured as a plurality of complementary memory cell pairs, and the bit values ​​of data entries are mapped to one of the complementary memory cell pairs.

[0085] In Example 13, the object of any of Examples 11 and 12 optionally includes a pair of complementary memory cells, comprising: a first memory cell for storing bit values ​​of data entries, and a second memory cell connected in series with the first memory cell for storing the inverse of the bit values, wherein a first search line of a plurality of search lines is connected to the first memory cell; and wherein a second word line of a plurality of word lines is connected to the second memory cell.

[0086] In Example 14, providing the search mode as input in any of Examples 11 to 13 optionally includes providing a first search signal representing the search bit value from the input search word to the first search line, and providing a second search signal representing the inverse code of the search bit value to the second search line.

[0087] In Example 15, the subject of any of Examples 11 to 14 optionally includes determining whether the input search word is stored by the CAM block based on data stored by the page buffer; and an indication of whether the output input search word is stored by the CAM block.

[0088] In Example 16, the object of any of Examples 11 to 15 optionally includes determining the location of a data entry by reading data from a page buffer, the location of the data indication string.

[0089] In Example 17, the page buffer of any of Examples 11 to 16 is a first page buffer, and the subject optionally includes: serially shifting data from the first page buffer to a second page buffer, wherein the first page buffer and the second page buffer are connected by a transistor; and counting the number of shifts performed to serially shift data from the first page buffer.

[0090] In Example 18, the bit sequence is the first bit sequence, the search mode includes a first set of signals representing the input search word and a second set of signals representing the second bit sequence, the second bit sequence including the inverse of the first bit sequence; and the generation search mode in any of Examples 11 to 17 optionally includes: inverting the first bit sequence to generate the second bit sequence; generating a first voltage signal representing the first bit sequence; and generating a second voltage signal representing the first bit sequence.

[0091] In Example 19, the location of a data entry in any of Examples 11 to 18 may optionally include the memory address of a string within the CAM block.

[0092] Example 20 is a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, configure the processing means to perform operations including: receiving an input search word including a first bit sequence; generating a search pattern based on the input search word, the search pattern including a first set of signals representing the input search word and a second set of signals representing a second bit sequence, the second bit sequence including the inverse of the first bit sequence; providing the search pattern as input to a search line of a content-addressable memory (CAM) block, the search pattern causing at least one string in the CAM block to conduct electricity, and providing a signal to a page buffer connected to the string in response to the input search word matching a data entry stored in the string, the signal being generated by a precharged match line discharging along the string; determining the location of a data entry within the CAM block based on data read from the page buffer, the page buffer storing the data based on the signal generated by the precharged match line discharging; and outputting the location of the data entry within the CAM block.

[0093] Machine architecture

[0094] Figure 7 An example machine in the form of a computer system 700 is shown, within which a set of instructions can be executed to cause the machine to perform any or more of the methods discussed herein. In some embodiments, the computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110, or may be used to perform operations of the controller 115 (e.g., execute an operating system to perform operations corresponding to...). Figure 1(Operation of search component 113). In alternative embodiments, the machine may connect (e.g., network) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment within the capacity of a server or client machine in a client-server network environment.

[0095] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is shown, it should also be understood that the term "machine" includes any collection of machines that individually or collectively execute a set (or more) of instructions to perform any one or more of the methods discussed herein.

[0096] The example computer system 700 includes a processing device 702 that communicates with each other via a bus 730, a main memory 704 (e.g., ROM, flash memory, DRAM, such as SDRAM or Rambus DRAM (RDRAM)), a static memory 707 (e.g., flash memory, static random access memory (SRAM)), and a data storage system 718.

[0097] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, processing device 702 may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as ASICs, FPGAs, digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 to perform the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication on network 720.

[0098] Data storage system 718 may include machine-readable storage medium 724 (also referred to as computer-readable medium) on which one or more sets of instructions 727 or software embodying any one or more of the methods or functions described herein are stored. The instructions 727 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, the main memory 704 and processing device 702 also constituting the machine-readable storage medium. Machine-readable storage medium 724, data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0099] In one embodiment, instruction 727 includes instructions to implement a security component (e.g., Figure 1 The function of the search component 113). Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions that are executed by a machine and causing a machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0100] Some parts of the previously described algorithms and symbolic representations of operations on data bits in computer memory have been presented. These algorithms are described and represented in a way that those skilled in the art of data processing can most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and generally are, considered as a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical manipulation of a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for common use, it has proven convenient sometimes to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0101] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of a computer system into other data representing physical quantities similarly represented in the memory or registers or other such information storage systems of a computer system.

[0102] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks); ROM; RAM; erasable programmable read-only memory (EPROM); EEPROM; magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0103] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to execute the methods. Structures for various such systems will be presented as described above. Furthermore, embodiments of this disclosure are described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0104] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as ROM, RAM, disk storage media, optical storage media, flash memory devices, etc.

[0105] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A memory system comprising: A memory device includes a content-addressable memory (CAM) block comprising an array of memory cells organized into a plurality of strings, one of the strings storing data entries, the string comprising a plurality of memory cells connected in series between a precharge matching line and a first page buffer, each of the memory cells being connected to one of a plurality of search lines. A processing device, coupled to the CAM block, is configured to perform operations including the following: A search pattern is generated based on an input search word that includes a bit sequence; The search pattern is provided as input to the plurality of search lines, the search pattern makes the string conductive, and a signal is provided to the first page buffer in response to the input search word matching the data entry stored on the string, the signal being generated by the discharge of the precharged matching line, the first page buffer storing data based on the signal; as well as The output is based on the position of the data entry within the CAM block determined by the data stored in the first page buffer; A shift register, comprising a first page buffer, a second page buffer, and a transistor connected between the first page buffer and the second page buffer, the shift register being used to serially shift the data out of the first page buffer; as well as A counter is used to determine the position of the data entry by counting the number of shifts performed serially to remove the data from the first page buffer.

2. The memory system according to claim 1, wherein: The plurality of memory cells are configured as a plurality of complementary memory cell pairs; and The bit value of the data entry is mapped to one of the plurality of complementary memory cell pairs.

3. The memory system according to claim 2, wherein: The complementary memory cell pair includes: A first memory unit is used to store the bit values ​​of the data entries, and A second memory unit connected in series with the first memory unit is used to store the inverse complement of the bit value. The first search line of the plurality of search lines is connected to the gate of the first memory cell; and The second search line of the plurality of search lines is connected to the gate of the second memory cell.

4. The memory system according to claim 3, wherein: The first search line receives a first search signal representing the search bit value from the input search word, and The second search line receives a second search signal representing the inverse code of the search bit value.

5. The memory system of claim 1, wherein the operation further comprises: Determine whether the input search term is stored by the CAM block; as well as Output an indication of whether the input search term is stored in the CAM block.

6. The memory system of claim 1, wherein the system further includes readout circuitry configured to read the data from the first page buffer, the data indicating the position of the string.

7. The memory system according to claim 1, wherein: The input search term includes the first sequence; The search mode includes a first set of signals representing the input search word and a second set of signals representing a second bit sequence, wherein the second bit sequence includes the inverse of the first bit sequence; The processing device includes: An inverter, used to generate the second bit sequence based on the input search word; as well as A level shifter for generating a first signal based on the first bit sequence and a second signal based on the second bit sequence.

8. The memory system of claim 1, wherein the location of the data entry includes the memory address of the string within the CAM block.

9. The memory system of claim 1, wherein the memory device comprises a NAND flash memory device.

10. A method for operating a memory device, comprising: The input search word, including a bit sequence, is received through at least one hardware processor; A search pattern is generated based on the input search word, at least through an inverter and a level selector; The search pattern is provided as input to a plurality of search lines of a content addressable memory (CAM) block in the memory device, the search pattern causing at least one string in the CAM block to conduct electricity, and providing a signal to a first page buffer connected to the string in response to the input search word matching a data entry stored on the string, the signal being generated by a precharged match line discharging along the string; Data is serially shifted from the first page buffer to the second page buffer, the first page buffer and the second page buffer being connected by a transistor, the first page buffer storing the data based on the signal generated by the precharge matching line discharging along the string; The position of the data entry within the CAM block is determined based on the number of shifts performed to serially remove the data from the first page buffer; as well as Output the position of the data entry within the CAM block.

11. The method of claim 10, wherein: The memory cells in the memory device are configured as multiple complementary memory cell pairs; and The bit value of the data entry is mapped to one of the plurality of complementary memory cell pairs.

12. The method according to claim 11, wherein: The complementary memory cell pair includes: A first memory unit is used to store the bit values ​​of the data entries, and A second memory unit connected in series with the first memory unit is used to store the inverse complement of the bit value. The first search line of the plurality of search lines is connected to the first memory cell; and The second word line of the plurality of word lines is connected to the second memory cell.

13. The method of claim 12, wherein providing the search pattern as input comprises: A first search signal representing the search bit value is provided from the input search word to the first search line, and A second search signal representing the inverse code of the search bit value is provided to the second search line among the plurality of search lines.

14. The method of claim 10, further comprising: Determine whether the input search term is stored in the CAM block based on the data stored in the page buffer; as well as Output an indication of whether the input search term is stored in the CAM block.

15. The method of claim 10, further comprising determining the position of the data entry by reading the data from the page buffer, the data indicating the position of the string.

16. The method of claim 10, wherein: The bit sequence is the first bit sequence; The search mode includes a first set of signals representing the input search word and a second set of signals representing a second bit sequence, wherein the second bit sequence includes the inverse of the first bit sequence; The generation of the search pattern includes: Invert the first bit sequence to generate the second bit sequence; Generate a first voltage signal representing the first bit sequence; and A second voltage signal representing the second bit sequence is generated.

17. The method of claim 10, wherein the location of the data entry includes the memory address of the string within the CAM block.

18. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, configure the processing means to perform operations including: Receive the input search word, including the first sequence. A search pattern is generated based on the input search word. The search pattern includes a first set of signals representing the input search word and a second set of signals representing a second bit sequence, wherein the second bit sequence includes the inverse of the first bit sequence. The search pattern is provided as input to a plurality of search lines of a content-addressable memory (CAM) block in a memory device, the search pattern causing at least one string in the CAM block to conduct, and providing a signal to a first page buffer connected to the string in response to the input search word matching a data entry stored on the string, the signal being generated by a precharged match line discharging along the string; The data is serially shifted from the first page buffer to the second page buffer, the first page buffer and the second page buffer are connected by a transistor, and the first page buffer stores the data based on the signal generated by the precharge matching line discharging along the string; The position of the data entry within the CAM block is determined based on the number of shifts performed to serially remove the data from the first page buffer; as well as Output the position of the data entry within the CAM block.

19. The non-transitory computer-readable storage medium according to claim 18, wherein: The memory cells in the memory device are configured as multiple complementary memory cell pairs; and The bit value of the data entry is mapped to one of the plurality of complementary memory cell pairs.

20. The non-transitory computer-readable storage medium of claim 19, wherein the complementary memory cell pair comprises: A first memory unit is used to store the bit values ​​of the data entries, and A second memory unit is connected in series with the first memory unit, and the second memory unit is used to store the inverse code of the bit value, wherein... The first search line of the plurality of search lines is connected to the gate of the first memory cell; and The second search line of the plurality of search lines is connected to the gate of the second memory cell.

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