Adjusting read voltage levels based on programmed bit count in memory subsystems

Abstract

A target value of a program bit is established for each program distribution of a set of program distributions of a memory sub-system. A read voltage level is applied to determine a measured value of the program bit in one or more program distributions of the set of program distributions. The target value of the program bit is compared to the measured value of the program bit to determine a comparison result and an action is performed in view of the comparison result.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more specifically, to adjusting read voltage levels based on a count of programmed bits in a memory sub-system. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at and retrieve data from the memory devices. BRIEF DESCRIPTION OF DRAWINGS

[0003] The present disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which various embodiments of the present disclosure are illustrated. The drawings, however, are not to be taken into constraint with the present disclosure, which is merely to be understood as illustrative and explanatory.

[0004] Figure 1 An example computing system including a memory sub-system according to some embodiments of the present disclosure is illustrated.

[0005] Figure 2 is a flowchart of an example method for managing a read voltage level in view of a comparison of a measured value of a programmed bit in a program distribution to a target value of the programmed bit in the program distribution according to some embodiments.

[0006] Figure 3 A set of example program distributions of an example memory device having target values of programmed bits established by a read level adjustment component according to some embodiments is illustrated.

[0007] Figure 4 An example circuit diagram corresponding to an example read level adjustment component and corresponding functionality according to some embodiments is illustrated.

[0008] Figure 5 is a plot illustrating a plot of a number of programmed bits corresponding to an applied sense voltage level according to some embodiments.

[0009] Figure 6 is a plot illustrating various techniques that can be used by a read level adjustment component to adjust an applied read voltage level to lock to a desired read voltage level in view of a comparison of a measured value of a programmed bit to a target value of the programmed bit.

[0010] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure can operate. DETAILED DESCRIPTION

[0011] Aspects of the present disclosure relate to adjusting a read level based on a count of programmed bits in a memory sub-system. The memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following description is presented to enable one of ordinary skill in the art to make and use the Figure 1 Examples of storage devices and memory modules are described. Generally, a host system can utilize a memory sub-system including one or more components such as a memory device that stores data. The host system can provide data stored at the memory sub-system and can request data retrieved from the memory sub-system.

[0012] A memory sub-system can include a plurality of memory devices having one or more arrays of memory cells for storing data. A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more binary bits of information and have various logic states related to the number of bits stored. The logic states can be represented by binary values such as “0” and “1” or combinations of such values. A memory device can be composed of bits arranged in a two-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (also referred to below as bit lines) and rows (also referred to below as word lines). A word line can refer to one or more rows of memory cells of a memory device that, together with one or more bit lines, are used to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes an address of a memory cell. A block refers to a cell of a memory device for storing data below and can include a group of memory cells, a group of word lines, a word line, or an individual memory cell.

[0013] A memory device can store an amount of charge into a memory cell based on a program level voltage or threshold voltage (Vt) corresponding to a plurality of program distributions associated with respective data values. The memory device can read or determine a data value stored in the memory cell using a read level voltage (also referred to as a “read level”) corresponding to a threshold voltage for each program distribution for the memory cell.

[0014] However, as memory cells experience program, sense, and erase cycles over time, the threshold voltage corresponding to the program distribution of the memory cell can change, which can result in the memory cell being read incorrectly. That is, the determined state of the memory cell during a read operation performed on the memory cell can be a state other than the state to which the memory cell can be programmed.

[0015] Aspects of the present disclosure address the above-described and other drawbacks by having a memory sub-system that includes a feedback system to dynamically adjust to changes in read level threshold voltage corresponding to a program distribution of the memory sub-system. During a program process, the system establishes a fixed or target ratio of program bits to erase bits (referred to herein as a "target ratio of program bits") for each program distribution of a memory device. The target ratio of program bits can include a substantially equal number of program bits in each of the program distributions (e.g., for an MLC memory device having four program distributions, the target ratio of program bits for each distribution can be 1 / 4).

[0016] During a read operation, a read voltage level associated with a distribution state is applied and a summation function is performed to determine or measure a cumulative or total number of program bits corresponding to the applied read voltage level. The measured total number of program bits is used to identify a measured ratio of program bits that is compared to the target ratio of program bits to produce a comparison result. The comparison result is used by the system as a signal to drive the applied read voltage level to a target read voltage level. For example, using the comparison result, the system can adjust (e.g., increase or decrease) the applied read voltage level to establish a target read voltage level for performing a read operation.

[0017] Advantageously, the system according to embodiments of the present disclosure does not need to implement expensive calibration algorithms to continuously predict read levels within a memory device. This results in a more efficient read path to result in an improved trigger rate (i.e., the rate at which a device fails error correction and needs an additional correction read to return the requested data). Further, the target read level corresponding to each of the program distributions is individually tuned based on bit signals to reflect a desired convergence. Advantages of the present disclosure further include establishing the best read value when performing a read process without adding additional latency. Further, since the read operation uses an internal calibration within the feedback system at each read, movement of the read level (e.g., due to disturbance mechanisms) is tracked. Thus, no additional calibration scheme is needed to predict changes in threshold voltage levels due to operational or environmental related wear or changes over time.

[0018] Figure 1 An example computing system 100 including a memory sub-system 110 according to some embodiments of the present disclosure is illustrated. The memory sub-system 110 can include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0019] The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0020] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes memory and a processing device.

[0021] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1 One example of a host system 120 coupled to one memory sub-system 110 is described. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0022] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., a NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory sub-system 110 to, for example, write data to and read data from the memory sub-system 110.

[0023] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a double data rate (DDR) memory bus, a small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface that supports double data rate (DDR)), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a PCIe interface, the host system 120 can further access components (e.g., the memory devices 130) using an NVM Express (NVMe) interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1 The memory sub-system 110 is illustrated as an example. In general, the host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0024] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory devices 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0025] Some examples of non-volatile memory devices (e.g., the memory devices 130) include negative-and (NAND) type flash memories and in-place writeable memories, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory can perform bit storage based on bulk resistance changes in combination with a stackable cross-grid format data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memories can perform in-place write operations, where a non-volatile memory cell can be programmed without needing to be previously erased. NAND type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0026] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, a single-level cell (SLC), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs), can store multiple bits per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, such as SLCs, MLCs, TLCs, QLCs, or any combination thereof. In some embodiments, a particular memory device can include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of the memory devices 130 can be grouped into pages, which can refer to a logical unit of the memory device for storing data. For some types of memory, such as NAND, pages can be grouped to form blocks.

[0027] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) have been described, the memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non- (NOR) flash memory and electrically erasable programmable read-only memory (EEPROM).

[0028] The memory sub-system controller 115 (or simply the controller 115) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, and other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with specialized (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0029] The memory sub-system controller 115 can be a processing device configured to execute instructions stored in local memory 119, including one or more processors (e.g., processor 117). In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0030] In some embodiments, the local memory 119 can include storage registers that store memory pointers, fetched data, and the like. The local memory 119 can also include read-only memory (ROM) for storing microcode. Although the example memory sub-system 110 has been illustrated as including the memory sub-system controller 115, in another embodiment of the present disclosure, the memory sub-system 110 does not include the memory sub-system controller 115, but can rely upon external control (e.g., provided by an external host or a processor or controller separate from the memory sub-system). Figure 1

[0031] In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical block address (e.g., logical block address (LBA), namespace) and a physical block address (e.g., physical block address) associated with the memory devices 130. The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert commands received from the host system into command instructions for accessing the memory devices 130, as well as convert responses associated with the memory devices 130 into information for the host system 120.

[0032] The memory sub-system 110 can also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive an address from the memory sub-system controller 115 and decode the address to access the memory devices 130.

[0033] ​In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory sub-system controller 115 to perform operations on one or more memory units of the memory device 130. An external controller, such as the memory sub-system controller 115, can externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0034] The memory sub-system 110 includes a read level adjustment component 113 that can be used to adjust to a target read voltage level value in view of a number of program bits (or bit lines) in each program distribution of the memory device. In embodiments, the read level adjustment component 113 establishes a target value for the program bits for each program distribution state during a write or program process. In embodiments, the target value is based on a ratio of program bits to erase bits for each program distribution state of any type of memory sub-system (e.g., SLC memory device, MLC memory device, QLC memory device, etc.). In one example, for a MLC memory sub-system having four program distributions, a target value or target ratio can be established such that each program distribution includes ¼ of a total number of program bits.

[0035] During a read operation, the read level adjustment component 113 applies an initial read voltage level to determine a measured value of the program bits in the program distribution. In embodiments, the measured value can be based on a ratio of program bits to erase bits for the program distribution. The read level adjustment component 113 can perform a summation function to measure a count of the program bits and a corresponding measured ratio of the program bits. The measured value of the program bits is compared to the target value of the program bits to determine a comparison result. In view of the comparison result, the read level adjustment component 113 performs a corresponding action. In embodiments, if the comparison result indicates that the measured value of the program bits is substantially equal to (e.g., within a predefined tolerance or range) the target value of the program bits, then the read level adjustment component 113 performs the read operation and reads the data using the applied read voltage level. In embodiments, if the comparison result indicates that the measured value of the program bits is greater than the target value of the program bits, then the read level adjustment component 113 decreases the applied read voltage level to an adjusted read voltage level. In embodiments, if the comparison result indicates that the measured value of the program bits is less than the target value of the program bits, then the read level adjustment component 113 increases the applied read voltage level to an adjusted read voltage level. The read level adjustment component 113 can iteratively apply the adjusted read voltage level until the measured value of the program bits is substantially equal to (e.g., within a tolerance or threshold) the target value of the program bits.

[0036] Figure 2 is a flowchart of an example method 200 for managing a read voltage level during performance of a read operation to read data in a memory device. The method 200 can be performed by processing logic that can comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by a read level adjustment component 113 of Figure 1 Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0037] As shown in Figure 2 , at operation 210, the processing logic establishes a target value of program bits for each program distribution of a set of program distributions of the memory sub-system. In an embodiment, the target value of program bits can be a ratio of program bits to erase bits of the program distribution. In an embodiment, the target value of program bits corresponding to each of the program distributions can be established during a program time of the memory sub-system.

[0038] For example, for an MLC memory device having four program distributions, the processing logic can establish a target value of program bits, where each of the four program distributions includes ¼ of the program bits. Figure 3 An example set of program distributions 210 (e.g., program distribution (PD) 0, PD 1, PD 2, and PD 3) of an example MLC memory device having a target value of program bits established by the read level adjustment component 113 (e.g., according to operation 210 of the process 200 shown in Figure 2 As illustrated, during a program process, the target value of program bits for each of the program distributions (PD 0, PD 1, PD 2, and PD 3) is established. In this example, each of the four program distributions can be programmed to include ¼ of the total number of program bits.

[0039] At operation 220, the processing logic applies a read voltage level to determine a measured value of program bits corresponding to one or more program distributions of the set of program distributions. In an embodiment, the measured value can be a ratio of program bits to erase bits in the program distribution. In an embodiment, the measured value can be determined by performing a sum function to total or count a total number of program bit lines corresponding to the program distribution. The application of the read voltage level and the sum of the measured values of program bits are described in more detail below with respect to Figure 4 For example, as Figure 3As shown in FIG. 2, a read voltage level (RL2) can be applied to determine or measure the number of program bits of the program distribution 1 (PD 1). As shown in FIG. 2, the target value of the program bits associated with PD 1 is 1 / 2 of the total number of program (e.g., readable) bits. Figure 3 As shown in FIG. 2, the target value of the program bits associated with PD 1 is 1 / 2 of the total number of program (e.g., readable) bits.

[0040] At operation 230, the processing logic compares the target value of the program bits to the measured value of the program bits to determine a comparison result. In embodiments, the comparison can be between the target ratio of program bits to erase bits for the program distribution and the measured ratio of program bits to erase bits for the program distribution.

[0041] At operation 240, the processing logic performs an action in view of the comparison result. In embodiments, the action can include performing a read operation using the applied read level voltage in response to determining that the comparison result indicates that the measured value of the program bits substantially equals the target value of the program bits. In embodiments, if the measured value of the program bits and the target value of the program bits are equal or within a predetermined tolerance or range, then the two values are determined to substantially equal. In embodiments, the action can include decreasing the applied read voltage level to an adjusted read voltage level in response to determining that the comparison result indicates that the measured value of the program bits is greater than the target value of the program bits. In embodiments, the action can include increasing the applied read voltage level to an adjusted read voltage level in response to determining that the comparison result indicates that the measured value of the program bits is less than the target value of the program bits.

[0042] In embodiments, operations 220, 230, and 240 can be iteratively performed each time an adjusted read voltage level is generated. In this regard, the adjusted read voltage level is applied to determine an updated measured value of the program bits (as in operation 220) to compare (in operation 230) to the target value of the program bits until the comparison result indicates that the updated measured value of the program bits substantially equals the target value of the program bits.

[0043] Figure 4 An example circuit diagram 400 corresponding to example read level adjustment component 113 of the present application is illustrated. A read voltage level is applied to a word line of a memory device 420 and a summing function 410 is performed to determine a number count of program bit lines (e.g., BL1, BL2, BL3...BLN). The sum or accumulated value is used by the read level adjustment component 113 to determine a measured value of the program bits (e.g., number of program bit lines) and compare it to a target value of the program bits. At 430, the read voltage adjustment component 113 can determine that the measured value of the program bits substantially equals the target value of the program bits. Based on this comparison result, at 435, the read voltage adjustment component 113 performs a read operation using the applied read voltage level.

[0044] In an embodiment, at 440, the read voltage adjustment component 113 can determine that the measured value of the program bit is greater than the target value of the program bit. Based on this comparison result, at 445, the read voltage adjustment component 113 decreases the applied read voltage level to an adjusted (decreased) read voltage level. The adjusted read voltage level is fed back and applied to the word line at 420 and the summation operation is repeated to identify an updated measured value of the program bit.

[0045] In an embodiment, at 450, the read voltage adjustment component 113 can determine that the measured value of the program bit is less than the target value of the program bit. Based on this comparison result, at 455, the read voltage adjustment component 113 increases the applied read voltage level to an adjusted (increased) read voltage level. The adjusted read voltage level is fed back and applied to the word line at 420 and the summation function is repeated to identify an updated measured value of the program bit.

[0046] Figure 5 is a graph illustrating a plot of the number of program bits when using a common applied measurement voltage for independent bit line settings. As shown, the read voltage level adjustment component can use a comparison result to drive the read threshold level (e.g., RL1, RL2, and RL3) to a value where the measured value of the program bit substantially equals the target value of the program bit. As shown, the target value of the program bit (or target program bit level) is established and it corresponds to a valley between adjacent program distributions. Advantageously, by performing an action in view of the comparison result, the applied read voltage level can be adjusted and locked in when the target value of the program bit is achieved. In Figure 5 In the example shown in, the target program bit level for RL1 is ¼ of the total program bits, the target program bit level for RL2 is ½ of the total program bits, and the target program bit level for RL3 is ¾ of the total program bits.

[0047] Figure 6 is a graph illustrating various techniques that can be used by the read level adjustment component to adjust the applied read voltage level to lock in at a desired read voltage level (e.g., a read voltage level that results in a measured value of the program bit that substantially equals the target value of the program bit). As shown, the read level adjustment component can adjust the applied read voltage level to overshoot or saturate the read voltage level and then back off from the saturation to determine the desired read voltage level (e.g., a read voltage level that results in a measured value of the program bit that substantially equals the target value of the program bit). In an embodiment, the read level adjustment component can adjust the read voltage level to approach a convergence point, but not overshoot (e.g., under-damped), depending on the characteristics of the memory device and the feedback system described above. Figure 6 In an embodiment, the read level adjustment component can ramp the read voltage level applied to the word line, where the summation function iteratively samples the measured value of the program bit and locks in at the read voltage level after determining that the measured value of the program bit substantially equals the target value of the program bit. In an embodiment, the read voltage level can be over-driven by the read level adjustment component to overshoot or saturate the read voltage level and then back off from the saturation to determine the desired read voltage level (e.g., a read voltage level that results in a measured value of the program bit that substantially equals the target value of the program bit). In an embodiment, the read level adjustment component can adjust the read voltage level to approach a convergence point, but not overshoot (e.g., under-damped), depending on the characteristics of the memory device and the feedback system described above.

[0048] According to embodiments of this application, the read voltage level can be significantly suppressed by interference mechanisms, such as changes in array conditions from the programming state (e.g., transient VT), read interference, programming interference, data retention, thermal correction, etc., given the target number of programming bits. Specifically, the systems and methods described herein are used to address anticipated charge loss in replacement gate memory devices (e.g., NAND devices).

[0049] Furthermore, the read voltage adjustment component and its corresponding functionality reduce chip complexity and time-to-market by dynamically adjusting and internally monitoring the read voltage level. Therefore, the memory device including the read voltage adjustment component uses internal signals to determine the optimized or desired read point. This enables the memory device to dynamically adjust to shifted or disturbed data.

[0050] Advantageously, to read intermediate states, the memory device can be adjusted or driven to the target value of the programmed bit and latched during the read. The system and method described herein compensate for positional differences and return correct data. Furthermore, the read retry path is shortened by the read level adjustment component because an internally provided signal is actively used to determine the valley position (e.g., mitigating the need to perform a second read in response to an inaccurate initial read level offset). Therefore, no specific offset is required for data holding or crossover temperature.

[0051] Furthermore, the system and method described herein remove constraints on the placement distribution at identical points across all word lines. Because the read process cuts off internal signals, substantial changes in valley locations can be targeted without adversely affecting the trigger rate. This provides additional flexibility in generating the read window budget. In an embodiment, the read voltage level can be tuned for each memory cell read.

[0052] Figure 7 The example machine illustrating computer system 700 may execute within computer system 700 a set of instructions for causing the machine to perform any or more of the methodologies discussed herein. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., a memory subsystem). Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of the read level adjustment component 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0053] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0054] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0055] Processing device 702 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device can be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 702 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 can further include a network interface device 708 to communicate over the network 720.

[0056] The data storage system 718 can include a machine-readable storage medium 724 (also known as a computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. The instructions 726 can also reside, completely or at least partially, within the main memory 704 and / or processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, data storage system 718, and / or main memory 704 can correspond to memory subsystem 110 of FIG. 1. Figure 1

[0057] In one embodiment, the instructions 726 include instructions to implement a data protection component (e.g., a data protection component 108 of FIG. 1) corresponding to a data protection component 108 of FIG. 1. Figure 1 ​instructions to implement functionalities of the read level adjustment component 113) of the video encoder 112. While the machine-readable storage medium 724 is shown in an example implementation to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0058] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These

[0059] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0060] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0061] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as follows from the description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure described herein.

[0062] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium, such as a read only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0063] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific embodiments thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method of adjusting a read voltage level, the method comprising: establishing, by a processing device, a target value of program bits for each program distribution of a set of program distributions of a memory sub-system, wherein the target value of program bits for a first program distribution comprises a target ratio of a first number of program bits to a second number of erase bits in the first program distribution; applying a read voltage level to determine a measured value of program bits in one or more program distributions of the set of program distributions; comparing the target value of program bits to the measured value of program bits to determine a comparison result; and performing an action in view of the comparison result.

2. The method of claim 1, wherein the comparison result indicates that the measured value of program bits is substantially equal to the target value of program bits; and wherein the action comprises performing a read operation using the read voltage level.

3. The method of claim 1, wherein the comparison result indicates that the measured value of program bits is greater than the target value of program bits; and wherein the action comprises decreasing the read voltage level to an adjusted read voltage level.

4. The method of claim 3, further comprising: applying the adjusted read voltage level to determine an updated measured value of program bits; comparing the updated measured value of program bits to the target value of program bits to determine an updated comparison result, wherein the updated comparison result indicates that the updated measured value of program bits is substantially equal to the target value of program bits; and performing a subsequent action in view of the updated comparison result, wherein the subsequent action comprises performing a read operation using the adjusted read voltage level.

5. The method of claim 1, wherein the comparison result indicates that the measured value of program bits is less than the target value of program bits; and wherein the action comprises increasing the read voltage level to an adjusted read voltage level.

6. The method of claim 5, further comprising: applying the adjusted read voltage level to determine an updated measured value of program bits; comparing the updated measured value of program bits to the target value of program bits to determine an updated comparison result, wherein the updated comparison result indicates that the updated measured value of program bits is substantially equal to the target value of program bits; and performing a subsequent action in view of the updated comparison result, wherein the subsequent action comprises performing a read operation using the adjusted read voltage level.

7. The method of claim 1, wherein a sum function is performed to determine a count of program bits corresponding to the one or more program distributions in view of the read voltage level.

8. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: establishing, by a processing device, a target value of program bits for a set of program distributions of a memory sub-system, wherein the target value of program bits comprises an equal number of program bits for each program distribution of the set of program distributions; applying a first read voltage level to a word line portion of the memory sub-system; performing a summing function to determine a cumulative count of program bits in one or more program distributions corresponding to the first read voltage level; determining a measured value of program bits in view of the cumulative count of program bits; comparing the target value of program bits to the measured value of program bits to determine a comparison result; setting an adjusted read voltage level in view of the comparison result; and applying the adjusted read voltage level to the word line portion of the memory sub-system.

9. The non-transitory computer-readable medium of claim 8, wherein the adjusted read voltage level is generated by decreasing the first read voltage level in response to the comparison result indicating that the measured value of program bits is greater than the target value of program bits.

10. The non-transitory computer-readable medium of claim 8, wherein the adjusted read voltage level is generated by increasing the first read voltage level in response to the comparison result indicating that the measured value of program bits is less than the target value of program bits.

11. The non-transitory computer-readable medium of claim 8, the operations further comprising: determining an updated measured value of program bits in view of an updated cumulative count of program bits corresponding to the adjusted read voltage level.

12. The non-transitory computer-readable medium of claim 8, wherein the target value of program bits for a first program distribution comprises a target ratio of a first number of program bits to a second number of erase bits in the first program distribution.

13. A system for adjusting a read voltage level, the system comprising: a memory device; and a processing device operably coupled with the memory device to perform operations comprising: establishing a target value of program bits for each program distribution in a set of program distributions of a memory sub-system, wherein the target value of program bits for a first program distribution comprises a target ratio of a first number of program bits to a second number of erase bits in the first program distribution; applying a read voltage level to determine a measured value of program bits in one or more program distributions of the set of program distributions; comparing the target value of program bits to the measured value of program bits to determine a comparison result; and performing an action in view of the comparison result.

14. The system of claim 13, wherein the comparison result indicates that the measured value of program bits is substantially equal to the target value of program bits; and wherein the action comprises performing a read operation using the read voltage level.

15. The system of claim 13, wherein the comparison result indicates that the measured value of program bits is greater than the target value of program bits; and wherein the action comprises decreasing the read voltage level to an adjusted read voltage level.

16. The system of claim 15, the operations further comprising: applying the adjusted read voltage level to determine an updated measured value of program bits; comparing the updated measured value of program bits to the target value of program bits to determine an updated comparison result, wherein the updated comparison result indicates that the updated measured value of program bits is substantially equal to the target value of program bits; and performing a subsequent action in view of the updated comparison result, wherein the subsequent action comprises performing a read operation using the adjusted read voltage level.

17. The system of claim 13, wherein the comparison result indicates that the measured value of the programmed bit is less than the target value of the programmed bit; and wherein the action comprises increasing the read voltage level to an adjusted read voltage level.

18. The system of claim 17, the operations further comprising: applying the adjusted read voltage level to determine an updated measured value of the programmed bit; comparing the updated measured value of the programmed bit to the target value of the programmed bit to determine an updated comparison result, wherein the updated comparison result indicates that the updated measured value of the programmed bit is substantially equal to the target value of the programmed bit; and performing a subsequent action in view of the updated comparison result, wherein the subsequent action comprises performing a read operation using the adjusted read voltage level.

19. The system of claim 18, wherein the subsequent action comprises determining a second updated measured value of the programmed bit using a second adjusted read voltage level.

20. The system of claim 19, wherein the second adjusted read voltage level is greater than the adjusted read voltage level.

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