Image sensor and driving method thereof

Abstract

The present disclosure provides an image sensor and a driving method. The driving method includes the following steps. During a standard scan in a high frame rate mode, a plurality of first control signals generated according to a first clock pulse frequency are provided by a portion of a plurality of drivers to a plurality of target gate lines included in a portion of a plurality of gate line groups. During a fast scan in the high frame rate mode, a plurality of second control signals generated according to a second clock pulse frequency are provided by the portion of the plurality of drivers to a plurality of remaining gate lines included in the portion of the plurality of gate line groups, and the first clock pulse frequency is slower than the second clock pulse frequency.

Description

Technical Field

[0001] This invention relates to an image sensor, and more particularly to an image sensor suitable for high-speed sampling of local areas and its driving method. Background Technology

[0002] In today's image sensing technology, with the widespread use of X-ray dynamic images, how to provide more realistic images for users to interpret is an important issue in this field. Summary of the Invention

[0003] This disclosure provides a driving method for driving an image sensor. The image sensor includes a plurality of gate line groups and a plurality of drivers corresponding to the plurality of gate line groups. Each of the plurality of gate line groups includes a plurality of gate lines. Each of the plurality of drivers is configured to provide a plurality of control signals to a plurality of gate lines corresponding to one of the plurality of gate line groups. The driving method includes the following steps: During a standard scan in a high frame rate mode, a portion of the plurality of drivers provides a plurality of first control signals, generated according to a first clock pulse frequency, to a plurality of target gate lines included in a portion of the plurality of gate line groups. During a fast scan in a high frame rate mode, the portion of the plurality of drivers provides a plurality of second control signals, generated according to a second clock pulse frequency, to a plurality of remaining gate lines included in the portion of the plurality of gate line groups, where the first clock pulse frequency is slower than the second clock pulse frequency.

[0004] This disclosure provides another driving method for driving an image sensor. The image sensor includes a plurality of gate line groups and a plurality of drivers corresponding to each of the plurality of gate line groups. Each of the plurality of gate line groups includes a plurality of gate lines. Each of the plurality of drivers is configured to provide a plurality of control signals to a plurality of gate lines corresponding to one of the plurality of gate line groups. The driving method includes the following steps: During a standard scan in a high frame rate mode, a portion of the plurality of drivers is configured to provide a plurality of first control signals, generated according to a first clock pulse frequency, to a plurality of target gate lines included in a portion of the plurality of gate line groups. During a fast scan in a high frame rate mode, another portion of the plurality of drivers is configured to provide a plurality of third control signals, generated according to a second clock pulse frequency, to the plurality of gate lines included in that portion of the plurality of gate line groups, where the first clock pulse frequency is slower than the second clock pulse frequency.

[0005] This disclosure provides an image sensor including an image sensing array and multiple drivers. The image sensing array includes multiple gate line groups. Each of the multiple gate line groups includes multiple gate lines. The multiple drivers correspond to the multiple gate line groups respectively. Each of the multiple drivers is used to provide multiple control signals to a plurality of gate lines in a corresponding group of the multiple gate line groups. During a standard scan in a high frame rate mode, a portion of the multiple drivers is used to provide multiple first control signals, generated according to a first clock pulse frequency, to a plurality of target gate lines included in a portion of the multiple gate line groups. During a fast scan in a high frame rate mode, the same portion of the multiple drivers is used to provide multiple second control signals, generated according to a second clock pulse frequency, to a plurality of remaining gate lines included in that portion of the multiple gate line groups, where the first clock pulse frequency is slower than the second clock pulse frequency.

[0006] In summary, when driving an image sensor in a high frame rate mode, this disclosure utilizes rapid scanning of a portion of the gate lines to reset the pixel circuitry in non-target areas, thereby increasing the frame rate of the image and enhancing its realism. Attached Figure Description

[0007] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described below:

[0008] Figure 1 This is a schematic diagram of an image sensor and electronic device in some embodiments of this disclosure.

[0009] Figure 2 This is a frame of an image output by an image sensor in standard mode in some embodiments of this disclosure.

[0010] Figure 3 This is a schematic diagram of the functional blocks of an image sensor in some embodiments of this disclosure.

[0011] Figure 4A This is a schematic diagram of the circuit architecture of an image sensor in some embodiments of this disclosure.

[0012] Figure 4B This is a schematic diagram of the circuit architecture between the driver, gate line group and pixel circuit in some embodiments of this disclosure.

[0013] Figure 5 This is a schematic diagram of the circuit architecture of the pixel circuit in some embodiments of this disclosure.

[0014] Figure 6A This is a flowchart of a driving method in some embodiments of this disclosure.

[0015] Figure 6B In some embodiments of this disclosure, the corresponding Figure 6A The flowchart of step S630b in the driving method of the above.

[0016] Figure 6C In some other embodiments of this disclosure, the corresponding Figure 6A The flowchart of step S630c in the driving method.

[0017] Figure 7 This is a schematic diagram of the circuit architecture between the driver, gate line group and pixel circuitry in some embodiments of this disclosure.

[0018] Figure 8 For some embodiments of this disclosure Figure 7 The timing diagram of the first control signal, the second control signal, and the third control signal provided by the driver in the middle.

[0019] Figure 9 For some embodiments of this disclosure Figure 7 The timing diagram of the first control signal, the second control signal, and the third control signal provided by the driver in the middle.

[0020] Figure 10 This is a frame of a second image output by an image sensor in some embodiments of this disclosure.

[0021] The attached figures are labeled as follows:

[0022] 100: Image sensor

[0023] 110: Image sensing array

[0024] 120: Timing control circuit

[0025] 200: Electronic devices

[0026] 600: Driver Method

[0027] READOUT[1]~READOUT[o]: Readout circuit

[0028] G1~Gm: Drivers

[0029] CS1[1]~CSm[n],CSr[s],CSr[s+1]: Control signals

[0030] CS2[x]~CS2[n],CS3[1]~CS3[y]: First control signal

[0031] CS2[1]~CS2[x-1],CS3[y+1]~CS3[n]c Second control signal

[0032] CS1[1]~CS1[n],CS4[1]~CS4[n]: Third control signal

[0033] PIX1~PIXm: Pixel Circuit Group

[0034] P1[1]~P1[n],P2[1]~P2[n],Pm[1]~Pm[n]:Pixel circuit

[0035] GL1~GLm: Gate line group

[0036] GL1[1]~GL1[n],GL2[1]~GL2[n],GLm[1]~GLm[n]: gate lines

[0037] PD1, PD2: Photodiodes

[0038] T1, T2: Transistors

[0039] Vcom: System voltage terminal

[0040] RL1[1]~RL[p],RL[q],RL[q+1],RL[q+2]: Read lines

[0041] OUTPUT: Frame data

[0042] ROIC_Activate: Enable signal

[0043] ROI: Region of Interest

[0044] S610, S620, S630, S640, S650, S660, S670, S680, S682, S684, S686, S690, S695: Steps

[0045] PHC1, PHC2: During rapid scan

[0046] PNC: During standard scanning

[0047] PREF: During the update period

[0048] FrameData_ROI: Region of Interest Image Data Detailed Implementation

[0049] The following detailed description, in conjunction with the accompanying drawings, provides examples to better illustrate the invention. However, the provided examples are not intended to limit the scope of the invention, and the description of structural operations is not intended to limit the order of execution. Any structure resulting from the recombination of elements, producing a device with equivalent functionality, falls within the scope of this invention. Furthermore, in accordance with industry standards and common practice, the accompanying drawings are for illustrative purposes only and are not drawn to their original dimensions. In fact, the dimensions of various features may be arbitrarily increased or decreased for ease of explanation. In the following description, the same elements will be designated with the same symbols for ease of understanding.

[0050] The indices 1 to n in the component and signal numbers used in this specification and drawings are merely for convenience in referring to individual components and signals, and are not intended to limit the number of the aforementioned components and signals to a specific number. In this specification and drawings, if a component or signal number is used without specifying its index, it means that the component or signal number refers to any unspecified component or signal within the corresponding component or signal group.

[0051] Furthermore, the terms "comprising," "including," "having," "containing," etc., used in this document are all open-ended terms, meaning "including but not limited to." Additionally, the term "and / or" as used in this document includes any one or more of the related listed items and all combinations thereof.

[0052] In this document, when an element is referred to as a “connection” or “coupled,” it may mean an “electrical connection” or “electrical coupling.” “Connection” or “coupled” can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as “first,” “second,” etc., are used in this document to describe different elements, these terms are only used to distinguish elements or operations described using the same technical terminology.

[0053] Please see Figure 1 , Figure 1 This is a schematic diagram of an image sensor 100 and an electronic device 200 in some embodiments of this disclosure. In some embodiments, the image sensor 100 may be implemented as a complementary metal-oxide-semiconductor (CMOS) sensor. In some embodiments, the image sensor 100 may be a dynamic X-ray sensor.

[0054] In some embodiments, the electronic device may be implemented by a computer, and the electronic device may include a display screen (not shown) for displaying the image output by the image sensor 100. In some embodiments, the electronic device 200 may instruct the image sensor 100 to operate in a standard mode or a high frame rate mode.

[0055] Please see Figure 2, Figure 2 This is a frame of an image output by the image sensor 100 in standard mode in some embodiments of this disclosure. For example... Figure 2 As shown, the image sensor 100 can be used for angiography, visceral angiography, and other X-ray imaging. In some cases, the first image output by the image sensor 100 may have a lower or similar frame rate (e.g., 30Hz, 60Hz, or 80Hz) compared to a human heartbeat or pulse, causing the first image to not directly represent the area to be observed during the cardiac cycle or arterial / venous pulsation (e.g., region of interest, such as...). Figure 2 The precise variations are shown. In other embodiments, the image sensor 100 may be applied to dental or chest X-ray imaging. Therefore, the invention is not limited thereto.

[0056] Please see Figure 3 , Figure 3 This is a schematic diagram of the functional blocks of an image sensor 100 in some embodiments of this disclosure. For example... Figure 3 As shown, the image sensor 100 includes an image sensing array 110, a timing control circuit 120, drivers G1 to Gm, and readout circuits READOUT[1] to READOUT[o], wherein the “m” in the driver Gm and the “o” in the readout circuit READOUT[o] can be implemented by any positive integer.

[0057] The image sensing array 110 includes pixel circuit groups PIX1 to PIXm and readout lines RL[1] to RL[p], wherein the aforementioned “p” can be implemented by any positive integer. The pixel circuit groups PIX1 to PIXm correspond to drivers G1 to Gm, respectively. Furthermore, drivers G1 to Gm are used to provide control signals CS1[1] to CS1[n], CS2[1] to CS2[n] to CSm[1] to CSm[n], respectively, wherein the aforementioned “n” can be implemented by any positive integer (e.g., 128, 256, or 512).

[0058] The readout circuits READOUT[1] to READOUT[o] are electrically coupled to the image sensing array 110 via readout lines RL[1] to RL[p]. The readout circuits READOUT[1] to READOUT[o] are used to receive the potential changes of the pixel circuits in the image sensing array 110 after illumination via readout lines RL[1] to RL[p], thereby outputting frame data OUTPUT. In some embodiments, each of the readout circuits READOUT[1] to READOUT[o] includes a Correlated Doublesampling (CDS) circuit, which is electrically coupled to the corresponding readout lines RL[1] to RL[p], thereby taking the potential difference value between the leakage potential of readout lines RL[1] to RL[p] and the reset potential of readout lines RL[1] to RL[p].

[0059] In some embodiments, the timing control circuit 120 provides a clock pulse signal GCLK to the drivers G1 to Gm to control the scanning frequency of the drivers G1 to Gm. In some embodiments, the timing control circuit 120 provides an enable signal ROIC_Activate to the readout circuits READOUT[1] to READOUT[o] to control the readout circuits.

[0060] READOUT[1]~READOUT[o] performs readout operations on the pixel circuits in the image sensing array 110.

[0061] Please see Figure 4A , Figure 4A This is a schematic diagram of the circuit architecture of the image sensor 100 in some embodiments of this disclosure. Figure 4A As shown, the pixel circuit groups PIX1 to PIXm respectively include pixel circuits P1[1] to P1[n], P2[1] to P2[n] to Pm[1] to Pm[n], and P1[1] to P1[n] and P2[1] to P2[n] to Pm[1] to Pm[n] in the same row are electrically coupled to one of the readout circuits READOUT[1] to READOUT[o] via a corresponding one of the read lines RL[1] to RL[p].

[0062] In this situation, if the pixel circuits of only a portion of the aforementioned region of interest (ROI) are read and reset according to the aforementioned method, the potential changes of the internal nodes in the other pixel circuits that have not been reset may generate leakage current after illumination, and this leakage current may be transmitted to the readout circuit [1] via the corresponding readout line, resulting in data distortion. Therefore, this disclosure provides a driving method for driving the image sensor 100 to improve the aforementioned problem, and the driving method is described in detail in the following embodiments.

[0063] Please see Figure 4B This is a schematic diagram of the circuit architecture between the drivers G1-Gm, the gate line groups GL1-GLm, and the pixel circuits P1[1]-P1[n], P2[1]-P2[n]-Pm[1]-Pm[n] in some embodiments of this disclosure. Figure 4B As shown, the image sensing array 110 includes gate lines GL1[1]~GL1[n], GL2[1]~GL2[n]~GLm[1]~GLm[n], and the middle pixel circuits P1[1]~P1[n] and P2[1]~P2[n]~Pm[1]~Pm[n] located in the same column are electrically coupled to one of the drivers G1~Gm via a corresponding one of the gate lines GL1[1]~GL1[n]. Furthermore, the gate line groups GL1~GLm correspond to the drivers G1~Gm respectively.

[0064] Specifically, pixel circuit P1[1] is electrically coupled to driver G1 via gate line GL1[1], thereby receiving control signal CS1[1] generated by driver G1 via gate line GL1[1]. Similarly, pixel circuit P1[n] is electrically coupled to driver G1 via gate line GLn[1], thereby receiving control signal CS1[n] generated by driver G1 via gate line GL1[n].

[0065] Similarly, pixel circuit P2[1] is electrically coupled to driver G2 via gate line GL2[1], thereby receiving control signal CS2[1] generated by driver G2 via gate line GL2[1]. Likewise, pixel circuit P2[n] is electrically coupled to driver G2 via gate line GL2[n], thereby receiving control signal CS2[n] generated by driver G1 via gate line GL2[n].

[0066] The connection relationship between the driver Gm and the pixel circuits Pm[1]~Pm[n] and the transmission method of the corresponding control signals Csm[1]~CSm[n] are similar to those of the drivers G1 and G2, and will not be repeated here.

[0067] Please see Figure 5 , Figure 5 This is a schematic diagram of the circuit architecture of pixel circuits Pr[s] and Pr[s+1] in some embodiments of this disclosure. The "s" in pixel circuits Pr[s] and Pr[s+1] can be any positive integer. Furthermore, the 4A and... Figure 4B Each of the pixel circuits P1[1]~P1[n] and P2[1]~P2[n]~Pm[1]~Pm[n] can be derived from... Figure 5 The pixel circuit Pr[s] is implemented in the process.

[0068] like Figure 5 As shown, each pixel circuit Pr[s] includes a transistor T1 and a photodiode PD1. The second terminal of photodiode PD1 is electrically coupled to the system voltage terminal Vcom. The first terminal of photodiode PD1 is electrically coupled to the second terminal of transistor T1.

[0069] The first terminal of transistor T1 in the pixel circuit Pr[s] of the same column is electrically coupled to one of the read lines RL[q] to RL[q+1], and the gate terminal of transistor T1 in the pixel circuit Pr[s] of the same column is electrically coupled to the gate line GLr[s] to receive the control signal CSR[s]. According to the control signal CSR[s], the photodiode PD1 contained in each pixel circuit Pr[s] transmits the voltage that changes after illumination to the corresponding readout circuit (e.g., READOUT[1]) via the read lines RL[q] to RL[q+1].

[0070] Similarly, each pixel circuit Pr[s+1] includes a transistor T2 and a photodiode PD2. The first terminal of the transistor T2 in the same column of pixel circuit Pr[s+1] is electrically coupled to a corresponding one of the readout lines RL[q] to RL[q+1], and the gate terminal of the transistor T2 in the same column of pixel circuit Pr[s+1] is electrically coupled to the gate line GLr[s+1] to receive the control signal CSR[s+1]. According to the control signal CSR[s+1], the pixel circuit Pr[s+1] is turned on, so that the photodiode PD2 included in each pixel circuit Pr[s+1] transmits the voltage that changes after illumination to the corresponding readout circuit (e.g., READOUT[1]) via the readout lines RL[q] to RL[q+1].

[0071] The aforementioned control signal CSR[s] corresponds to Figure 4A as well as Figure 4B One of the control signals CS1[1]~CS1[n], CS2[1]~CS2[n]~CSm[1]~CSm[n] will not be elaborated here.

[0072] In other embodiments, in standard mode, all drivers G1 to Gm generate and provide control signals CS1[1] to CS1[n], CS2[1] to CS2[n] to CSm[1] to CSm[n] according to a first clock pulse frequency (e.g., 50 kHz) to the corresponding gate lines CS1[1] to CSm[n], so as to sequentially scan the gate lines CS1[1] to CSm[n] and the readout circuits READOUT[1] to READOUT[o] sequentially read the potential changes of the pixel circuits P1[1] to Pm[n] after illumination, so as to generate global image data. In some embodiments, the image sensor 100 outputs the global image data as a first image at a first frame frequency.

[0073] For a clearer explanation of how the image sensor operates in high frame rate mode, please also refer to [link to relevant documentation]. Figures 1 to 8 . Figure 6A This is a flowchart of a driving method 600 in some embodiments of this disclosure. The driving method 600 includes steps S610 to S650. Figure 6B In some embodiments of this disclosure, the corresponding Figure 6A The flowchart of step S630b in the driving method of the above. Figure 6C In some other embodiments of this disclosure, the corresponding Figure 6A The flowchart of step S630c in the driving method.

[0074] Figure 7 This is a schematic diagram of the circuit architecture between drivers G1-G4, gate line groups GL1-GL4, and pixel circuits P1[1]-P4[n] in some embodiments of this disclosure. It should be noted that in the following embodiments, four drivers G1-G4 will be used as an example for clarity. However, the present invention is not limited thereto. Figure 8 For some embodiments of this disclosure Figure 7 Timing diagrams of the first control signals CS2[x]~CS2[n] and CS3[1]~CS3[y], the second control signals CS2[1]~CS2[x-1] and CS3[y+1]~CS3[n], and the third control signals CS1[1]~CS1[n] and CS4[1]~CS4[n] provided by the drivers G1~G4.

[0075] In step S610, the image sensor operates in a high frame rate mode. In some embodiments, after fixing the image sensor 100, the region of interest (ROI) can be determined by the user, such as in dental or thoracic applications. In some embodiments, the image sensor 100 may automatically start operating in a high frame rate mode in response to an instruction from the electronic device 200.

[0076] In step S620, several target gate lines included in a portion of the plurality of gate line groups are determined based on the region of interest (ROI). For example, if the scanning range of the ROI corresponds to gate lines GL2[x] to GL3[y] in gate line groups GL2 and GL3 of the pixel sensor 100, gate lines GL2[x] to GL3[y] can be considered as target gate lines. Gate lines GL2[1] to GL2[x-1] and GL3[y+1] to GL3[n] in gate line groups GL2 and GL3 can be considered as remaining gate lines, and gate lines GL1[1] to GL1[n] and GL4[1] to GL4[n] in the remaining gate line groups GL1 and GL4 can also be considered as remaining gate lines, such as... Figure 7 As shown.

[0077] In step S630, a reset operation is performed on the internal nodes of each pixel circuit electrically coupled to the remaining gate lines. Figure 7 In the embodiment, drivers G1 and G4 are used to provide third control signals CS1[1] to CS1[n] to the gate lines GL1[1] to GL1[n] and GL4[1] to GL4[n] in the gate line group GL1 and GL4.

[0078] Drivers G2 and G3 are used to provide second control signals CS2[1]~CS2[x-1] and CS3[y+1]~CS3[n] to the gate lines GL2[1]~GL2[x-1] and GL3[y+1]~GL4[n] in the gate line group GL2 and GL3.

[0079] Drivers G2 and G3 are used to provide first control signals CS2[x]~CS2[n] and CS3[1]~CS3[y] to the gate lines GL2[x]~GL2[n] and GL3[1]~GL4[y] in the gate line groups GL2 and GL3.

[0080] One embodiment of this disclosure is that step S630 in the driving method 600 is performed by... Figure 6B The operation method implemented in step S630b. Step S630b includes steps S632 and S636.

[0081] In step S632, during rapid scanning in high frame rate mode, the image sensor provides multiple third control signals, generated according to the second clock pulse frequency, to each of the multiple gate lines contained in another portion of the multiple gate line groups. For example, please refer to... Figure 8During the fast scan of PHC1 and PHC2 in high frame rate mode, the image sensor 100 provides the third control signals CS1[1]~CS1[n] and CS4[1]~CS4[n] to the gate lines GL1[1]~GL1[n] and GL4[1]~GL4[n] contained in the gate line groups GL1 and GL4 with the third control signals CS1[1]~GL1[n] and GL4[1]~GL4[n] generated according to the second clock pulse frequency (the second clock pulse frequency of the clock pulse signal GCLK during the fast scan of PHC1 and PHC2, for example 200KHz). This causes the readout circuit READOUT[1]~READOUT[o] to reset the potential of the internal nodes (e.g., the connection between photodiode PD1 and transistor T1) of the corresponding pixel circuits P1[1]~P1[n] and P4[1]~P4[n] via the read lines RL[1]~RL[p].

[0082] In this case, since the readout circuits READOUT[1] to READOUT[o] do not need to output / return sensing data, they can operate based on the second clock pulse frequency, which is faster than the first clock pulse frequency, thereby reducing the scan time.

[0083] In step S636, during rapid scanning in high frame rate mode, the image sensor provides a plurality of second control signals, generated according to the second clock pulse frequency, to the plurality of remaining gate lines contained in that portion of the plurality of gate line groups. For example, see [link to relevant documentation]. Figure 8 During the fast scan of PHC1 and PHC2 in the high frame rate mode, the image sensor 100 provides the second control signals CS2[1]~CS2[x-1] and CS3[y+1]~CS3[n] generated by the drivers G2 and G3 according to the second clock pulse frequency (the second clock pulse frequency of the clock pulse signal GCLK during the fast scan of PHC1 and PHC2, 200KHz) to the gate line group GL2 and the gate lines GL2[1]~GL2[x-1] and GL3[y+1]~GL3[n] contained in GL2, thereby causing the readout circuit READOUT[1]~READOUT[o] to reset the potential of the internal nodes (e.g., the connection between photodiode PD1 and transistor T1) of the corresponding pixel circuits P2[1]~P2[x-1] and P3[y+1]~P3[n) via the read lines RL[1]~RL[p].

[0084] Similarly, in this case, since the readout circuits READOUT[1] to READOUT[o] do not need to output / return sensing data, they can operate according to the second clock pulse frequency, which is faster than the first clock pulse frequency, thereby reducing the scan time.

[0085] In step S640, multiple first control signals generated according to the first clock pulse frequency are provided to multiple target gate lines, and a region of interest image data is read from multiple pixel circuits electrically coupled to the multiple target gate lines using a readout circuit. During the standard scan period PNC in high-speed frame rate mode, the image sensor 100 generates and provides first control signals CS2[x] to CS2[n] and CS3[1] to CS3[y] to the corresponding gate lines GL2[x] to GL2[n] and GL3[1] to GL3[y] according to the first clock pulse frequency (the first clock pulse frequency of the clock pulse signal GCLK during the standard scan period PNC, for example, 50KHz). This sequentially scans the gate lines GL2[x] to GL2[n] and GL3[1] to GL3[y] and the readout circuit...

[0086] READOUT[1]~READOUT[o] sequentially reads the potential changes of pixel circuits P2[x]~P2[n] and P3[1]~P2[y] after illumination, in order to generate and output image data of the region of interest.

[0087] In step S650, the region of interest (ROI) image data is output as a second image. In some embodiments, the image sensor 100 outputs the ROI image data FrameData_ROI as a second image at a second frame rate (e.g., 300 frames per second (FPS)). In some embodiments, since the frame rate of the second image is higher than that of the first image, the dynamic image presented by the image sensor 100 in high-speed frame mode is more realistic.

[0088] In some embodiments, when observing blood or internal organs, a smaller Region of Interest (ROI) can effectively increase the frame rate. Thus, the image sensor 100 can achieve a frame rate of 300 FPS in high frame rate mode.

[0089] Another embodiment of this disclosure is that step S630 in driving method 600 is performed by... Figure 6C For the operation method implemented in step S630c, please refer to Figures 4A and 4B. Figure 5 , Figure 6C , Figure 7 as well as Figure 9 Step S630c includes steps S634 and S636. Figure 9 For some embodiments of this disclosure Figure 7Timing diagrams of the first control signals CS2[x]~CS2[n] and CS3[1]~CS3[y], the second control signals CS2[1]~CS2[x-1] and CS3[y+1]~CS3[n], and the third control signals CS1[1]~CS1[n] and CS4[1]~CS4[n] provided by the drivers G1~G4.

[0090] In step S634, during the update of the image sensor in high frame rate mode, a plurality of third control signals with enable levels are provided to the gate lines contained in each of the plurality of gate line groups. For example, during the update of the image sensor 100 in high frame rate mode PREF, the drivers G1 and G4 simultaneously generate third control signals CS1[1]~CS1[n] and CS4[1]~CS4[n] with enable levels according to the first clock pulse frequency and provide the third control signals CS1[1]~CS1[n] and CS4[1]~CS4[n] to the gate lines GL1[1]~GL1[n] and GL4[1]~GL4[n] contained in each of the plurality of gate line groups GL1 and GL4.

[0091] At this time, since the enable signal ROIC_Activate has a low logic level, the readout circuits READOUT[1]~READOUT[o] do not perform read operations, and the pixel circuits P1[1]~P1[n] and P4[1]~P4[n] are reset simultaneously.

[0092] It is worth noting that during the PREF update in high frame rate mode, the duration of the third control signals CS1[1]~CS1[n] and CS4[1]~CS4[n] at the enable level is a multiple of the reciprocal of the first clock pulse frequency (the first clock pulse frequency of the clock pulse signal GCLK during the PREF update). In some embodiments, the third control signals CS1[1]~CS1[n] and CS4[1]~CS4[n] may not be a multiple of the reciprocal of the first clock pulse frequency. Therefore, the present invention is not limited thereto.

[0093] Thus, since pixel circuits P1[1]~P1[n] and P4[1]~P4[n] are simultaneously reset, the time length of a frame can be shortened, thereby increasing the frame rate. Figure 9 The operation methods in other time periods are similar. Figure 8 The embodiments described herein are not repeated here.

[0094] Please see Figure 10 , Figure 10This is a frame of an image output by the image sensor 100 in a high frame rate mode in some embodiments of this disclosure. Figure 10 As shown, the sensing area (e.g., region of interest) corresponding to the image output by the image sensor 100 in high frame rate mode is smaller than the sensing area corresponding to the image output in standard mode. Furthermore, the image output by the image sensor 100 in high frame rate mode has a higher frame rate than the image output in standard mode, and can improve leakage current in pixel circuits in non-target areas of the pixel sensing array 110, thereby providing a more realistic dynamic image.

[0095] In summary, this disclosure utilizes a driving method 600 to drive an image sensor 100 to operate in a standard mode or a high frame rate mode. When operating in the high frame rate mode, it utilizes a rapid scan of a portion of the gate lines to reset the pixel circuitry in non-target areas, thereby increasing the frame rate of the image and enhancing the realism of the image.

[0096] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A driving method for driving an image sensor, wherein the image sensor includes a plurality of gate line groups and a plurality of drivers corresponding to the plurality of gate line groups, wherein each of the plurality of gate line groups includes a plurality of gate lines, wherein each of the plurality of drivers is configured to provide a plurality of control signals to a plurality of gate lines corresponding to a plurality of the gate line groups, and wherein the driving method comprises: During a standard scan in a high frame rate mode, a plurality of first control signals, generated according to a first clock pulse frequency, are provided by a portion of the plurality of drivers to a plurality of target gate lines comprised of a portion of the plurality of gate line groups; and During a fast scan in this high frame rate mode, a plurality of second control signals generated according to a second clock pulse frequency are provided by the portion of the plurality of drivers to the plurality of remaining gate lines contained in the portion of the plurality of gate line groups, wherein the first clock pulse frequency is slower than the second clock pulse frequency; During the fast scan in this high frame rate mode, another portion of the plurality of drivers provides a plurality of third control signals, generated according to the second clock pulse frequency, to the plurality of gate lines contained in each of the plurality of gate line groups, or During an update in this high frame rate mode, a plurality of third control signals with enable levels are provided by another portion of the plurality of drivers to the plurality of gate lines contained in each of the plurality of gate line groups.

2. The driving method of claim 1, wherein during the update period in the high frame frequency mode, the duration of the enable level of the plurality of third control signals is a multiple of the reciprocal of the frequency of the first clock pulse.

3. The driving method as described in claim 1, further comprising: In a standard mode, multiple drivers provide multiple control signals generated according to the first clock pulse frequency to the multiple gate lines contained in each of the multiple gate line groups.

4. The driving method as described in claim 1, further comprising: During the standard scan in this high frame rate mode, multiple target pixel circuits electrically coupled to multiple target gate lines transmit multiple sense voltages to multiple readout circuits via multiple readout lines according to multiple first control signals; and The potential of the internal nodes of the respective target pixel circuits is reset by the multiple readout circuits to generate a region of interest image data.

5. The driving method as described in claim 4, further comprising: During this fast scan in the high frame rate mode, the potentials of the internal nodes of the respective target pixel circuits are reset by the multiple readout circuits.

6. The driving method as described in claim 4, wherein: In a standard mode, the image sensor outputs a global image data as a first image at a first frame rate; as well as In this high frame rate mode, the image sensor outputs the region of interest image data as a second image at a second frame rate, wherein the first frame rate is slower than the second frame rate, and wherein the sensing area corresponding to the global image data is larger than the sensing area corresponding to the region of interest image data.

7. A driving method for driving an image sensor, wherein the image sensor includes a plurality of gate line groups and a plurality of drivers corresponding to the plurality of gate line groups, wherein each of the plurality of gate line groups includes a plurality of gate lines, wherein each of the plurality of drivers is configured to provide a plurality of control signals to a plurality of gate lines corresponding to a plurality of the gate lines in the plurality of gate line groups, and wherein the driving method includes: During a standard scan in a high frame rate mode, a portion of the plurality of drivers is used to provide a plurality of first control signals generated according to a first clock pulse frequency to a plurality of target gate lines included in a portion of the plurality of gate line groups; and During a fast scan in this high frame rate mode, another portion of the plurality of drivers is used to provide a plurality of third control signals generated according to a second clock pulse frequency to the plurality of gate lines contained in each of the plurality of gate line groups, wherein the first clock pulse frequency is slower than the second clock pulse frequency; During the update of the image sensor in the high frame rate mode, a plurality of third control signals with enable levels are provided to the plurality of gate lines contained in each of the plurality of gate line groups.

8. An image sensor, comprising: An image sensing array comprising multiple gate line groups, each of the multiple gate line groups comprising multiple gate lines; and Multiple drivers, each corresponding to a plurality of said gate line groups, each driver being configured to provide multiple control signals to a plurality of said gate lines in a corresponding group of said gate line groups, wherein: During a standard scan in a high frame rate mode, a portion of the plurality of drivers are used to provide a plurality of first control signals generated according to a first clock pulse frequency to a plurality of target gate lines contained in a portion of the plurality of gate line groups; as well as During a fast scan in this high frame rate mode, this portion of the plurality of drivers is used to provide a plurality of second control signals generated according to a second clock pulse frequency to the plurality of remaining gate lines included in the plurality of gate line groups, wherein the first clock pulse frequency is slower than the second clock pulse frequency; During the fast scan in this high frame rate mode, another portion of the plurality of drivers provides a plurality of third control signals, generated according to the second clock pulse frequency, to the plurality of gate lines contained in each of the plurality of gate line groups, or During an update in this high frame rate mode, a plurality of third control signals with enable levels are provided by another portion of the plurality of drivers to the plurality of gate lines contained in each of the plurality of gate line groups.

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