Non-volatile memory and its write cycle recording device

Abstract

This disclosure provides a write cycle recording apparatus, comprising a storage device and a controller. The storage device corresponds to a memory block of non-volatile memory. The storage device has multiple bits for recording multiple recorded write cycle counts corresponding to multiple write operations on the memory block. The controller is configured to: perform write operations on the memory block; record the executed write cycle counts of the write operations; and update the recorded write cycle counts corresponding to the write operations in the storage device based on the executed write cycle counts.

Description

Technical Field

[0001] The present invention relates to a non-volatile memory and a write cycle recording device thereof, and more specifically, to a write cycle recording device for improving the reliability of a non-volatile memory. Background Technology

[0002] For non-volatile memories, write cycle counts consistently provide useful cycle information to improve the reliability of the memory. In conventional technologies, write cycle counts always occupy a large circuit area for storage, and the stored write cycle counts often have reliability issues. Therefore, providing a memory device with a smaller circuit size that can provide highly reliable write cycle counts is an important challenge for non-volatile memory designers. Summary of the Invention

[0003] The present invention provides a non-volatile memory and a write cycle recording device thereof to improve the efficiency of write operations on memory blocks.

[0004] The write cycle recording device includes a storage device and a controller. The storage device corresponds to a memory block of non-volatile memory. The storage device has multiple bits for recording multiple recorded write cycle counts corresponding to multiple write operations on the memory block. The controller is configured to: perform write operations on the memory block; record the executed write cycle counts of the write operations; and update the recorded write cycle counts corresponding to the write operations in the storage device based on the executed write cycle counts.

[0005] The non-volatile memory includes at least one memory block, a storage device, and a controller. Each of the at least one memory block has multiple memory blocks. The storage device is disposed in at least one memory block ad corresponding to the at least one memory block of the non-volatile memory, wherein the storage device has multiple bits for recording multiple recorded write cycle counts corresponding to multiple write operations on the memory block. The controller is coupled to the storage device and the memory block. The controller is configured to: perform write operations on the memory block; record the executed write cycle counts of the write operations; and update the recorded write cycle counts corresponding to the write operations in the storage device based on the executed write cycle counts.

[0006] Based on the above, the storage device records multiple recorded write cycle counts corresponding to multiple write operations on a memory block. The controller can obtain the state for performing write operations on the memory block and can well define the characteristics of the write pulse used to perform the write operation on the current memory block based on the recorded write cycle counts. In this way, the efficiency of the write operation can be improved.

[0007] To enable a better understanding of the above features and advantages of this disclosure, several embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0008] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and form a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0009] Figure 1 A schematic diagram of a write cycle recording apparatus according to an embodiment of the present disclosure is shown;

[0010] Figure 2 A schematic diagram showing recorded information for writing loop counts in a storage device according to an embodiment of the present disclosure;

[0011] Figure 3 Showing according to this disclosure Figure 2 The detailed contents of the information recorded in the storage device of the embodiment;

[0012] Figure 4 A block diagram of a non-volatile memory according to an embodiment of the present disclosure is shown;

[0013] Figure 5A and Figure 5B Flowcharts of different write operations for non-volatile memory according to embodiments of the present disclosure are shown respectively;

[0014] Figure 6 A schematic diagram illustrating the relationship between the recorded write cycle count and the dual-mode write operation scheme according to embodiments of the present disclosure;

[0015] Figure 7 A flowchart illustrating a write operation for a non-volatile memory according to an embodiment of the present disclosure is shown.

[0016] Explanation of icon numbers

[0017] 100: Write cycle recording device;

[0018] 101, MB1, MB2: Memory blocks;

[0019] 110, 440: Storage devices;

[0020] 120: Controller;

[0021] 200: Recorded information;

[0022] 400: Non-volatile memory;

[0023] 410: X Decoder;

[0024] 420: Y multiplexer;

[0025] 430: Readout amplifier;

[0026] BT0, BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8, BT9: bit;

[0027] IDX: Index value;

[0028] MA: Memory Array;

[0029] Reg: Register;

[0030] Reg<3:0>: Register value;

[0031] S511, S512, S513, S514, S515, S521, S522, S523, S524, S525, S710, S720, S730, S740, S750, S760: Steps. Detailed Implementation

[0032] Reference will now be made in detail to the present preferred embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0033] Please refer to Figure 1 This diagram illustrates a write cycle recording apparatus according to an embodiment of the present disclosure. The write cycle recording apparatus 100 includes a storage device 110 and a controller 120. The storage device 110 is coupled to the controller 120. The storage device 110 corresponds to a memory block 101 of non-volatile memory. In one embodiment, the storage device 110 may be disposed within the memory block 101, or in another embodiment, the storage device 110 may be disposed outside the memory block 101. The controller 120 is further coupled to the memory block 101. The non-volatile memory may be flash memory. The storage device 110 may have multiple bits. The bits of the storage device 110 are used to record multiple recorded write cycle counts corresponding to multiple write operations on the memory block 101.

[0034] Figure 2 This diagram illustrates a recorded write loop information according to an embodiment of a storage device based on the present disclosure. Please refer to... Figure 1 and Figure 2 ,exist Figure 2In the record, the write cycle information 200 has multiple bits BT0 to BT9. Bits BT0 to BT2 are used to store the recorded write cycle counts of the programming operations performed on the corresponding memory block 101. Bits BT3 to BT5 are used to store the recorded write cycle counts of the post-programming operations performed on the corresponding memory block 101. Bits BT6 to BT9 are used to store the recorded write cycle counts of the erase operations performed on the corresponding memory block 101.

[0035] Please refer to Figure 3 It shows that, according to this disclosure Figure 2 The embodiments described herein detail the recorded write cycle information in the storage device. The recorded write cycle information can be represented by an index value IDX, and different index values ​​IDX can correspond to different recorded write cycle counts. In this embodiment, taking a programming operation as an example, if the recorded write cycle count performed on memory block 101 is not greater than 2, then the index value IDX can be set to 0; if the recorded write cycle count performed on memory block 101 is greater than 2 and not greater than 4, then the index value IDX can be set to 1… and so on. If the recorded write cycle count performed on memory block 101 is greater than 256 and not greater than 512, then the index value IDX can be set to 8. In other embodiments, the write operation may include erase operations, post-programming operations, refresh operations, etc.

[0036] In this embodiment, since the index value IDX can be set to 8, the storage device needs 3 bits to record the index execution IDX of the programming operation. However, the index value IDX recorded by the storage device, the required number of bits, and the corresponding recorded write cycle count can be adjusted according to design requirements, and the present invention is not limited thereto.

[0037] Please refer to this again. Figure 1 The controller 120 performs write operations on the memory block 101. Taking a programming operation as an example, the controller 120 can pre-read the storage device 110 to obtain a recorded write cycle count of the programming operations performed on the memory block 101. During the programming operation, one or more write pulses (programming pulses) can be applied to the memory block 101, and the controller 120 can record the number of write pulses (programming pulses) to obtain a count of the executed write cycles of the write (programming) operation. When the programming operation is completed according to the programming verification operation corresponding to the programming operation, the controller 120 can obtain the count of executed write cycles and compare the count of executed write cycles with the recorded write cycle count. If the count of executed write cycles is greater than the recorded write cycle count, the controller 120 can update the recorded write cycle count based on the count of executed write cycles.

[0038] For example, if the index value IDX of the programming operation read from storage device 110 is 2, then the recorded write loop count representing the programming operation performed by memory block 101 is 8. If the executed write loop count recorded by controller 120 is greater than 8 and not greater than 16, then controller 120 can update the index value IDX in storage device 110 used to record the number of recorded write loops for programming operations to 3.

[0039] It should be noted here that the recorded write cycle counts in storage device 110 can be used to demonstrate the aging of the corresponding memory block 101. Specifically, if a write operation is performed on a young memory block 101, the controller 120 can execute one or more write pulses with normal voltage values ​​and normal pulse widths. On the other hand, if a write operation is performed on an older memory block 101, the controller 120 can execute write pulses with higher voltage values ​​and / or larger pulse widths. The controller can adjust the corresponding voltage values ​​and pulse widths based on the recorded write cycle count values.

[0040] Please refer to Figure 4 This diagram illustrates a block diagram of a non-volatile memory according to an embodiment of the present disclosure. The non-volatile memory 400 includes multiple memory blocks MB1 and MB2. Taking memory block MB1 as an example, memory block MB1 includes multiple libraries 0 to 15, an X decoder 410, a Y multiplexer (YMUX) 420, a sense amplifier (SA) 430, and a storage device 440. Each of libraries 0 to 15 has a memory array MA containing multiple memory cells. The X decoder 410 is an address decoder with an X direction and can be shared by memory block MB1 and adjacent memory block MB2. The Y multiplexer 420 is another address decoder with a Y direction, where the X direction is different from the Y direction.

[0041] Sensing amplifier 430 is coupled to Y multiplexer 420 for receiving data from the bit lines of a selected library according to Y multiplexer 420. Sensing amplifier 430 is used to sense data from the bit lines to obtain readout data from the selected library.

[0042] It should be noted here that a storage device 440 may be disposed between library 0 and the Y multiplexer 420. The storage device 440 may consist of multiple non-volatile memory cells (i.e., flash memory cells). The storage device 440 is used to record multiple recorded write cycle counts corresponding to multiple write operations of memory block MB1. The detailed operation of the storage device 440 has been discussed in the embodiments mentioned above and will not be repeated here.

[0043] Please refer to Figure 5A and Figure 5B ,in Figure 5A and Figure 5B Each shows the following according to this disclosure Figure 2 The flowcharts in the embodiments describe different write operations of the storage device for non-volatile memory. Figure 5A In step S511, the write (programming) command is received by the controller of the non-volatile memory. In step S512, the controller may pre-read the recorded write cycle count of the programming operations performed on the selected memory block from the storage device in the non-volatile memory. In step S513, the controller performs a programming operation according to the write (programming) command to apply at least one programming pulse on the selected memory block, and calculates the executed write cycle count during the programming operation. The controller further compares the executed write cycle count of the programming operation with the recorded write cycle count in step S513.

[0044] In step S514, the controller determines whether the executed write loop count of the programming operation is greater than the recorded write loop count. If the executed write loop count is not greater than the recorded write loop count in step S514, the programming operation can be completed. Conversely, if the executed write loop count is greater than the recorded write loop count, the controller updates the recorded write loop count in the storage device using the executed write loop count in step S515, and the programming operation can be completed. In this embodiment, the executed write loop count is the maximum executed write loop count during the programming operation before the programming verification is successful.

[0045] exist Figure 5B In step S521, the erase command is received by the controller of the non-volatile memory. In step S522, the controller can pre-read the write cycle counts recorded in the erase operation and post-programming operation from the storage device in the non-volatile memory. In step S523, the controller performs an erase / post-programming operation according to the erase command to apply at least one erase pulse to the selected memory block, and then, if necessary, applies at least one post-programming pulse to the selected memory block. The controller further calculates the executed write cycle counts of the erase operation and the post-programming operation during the erase operation. The controller further compares the executed write cycle counts of the erase operation and the post-programming operation with the recorded write cycle counts in step S523, respectively.

[0046] In step S524, the controller determines whether the executed write loop count of the erase operation is greater than the recorded write loop count, and also determines whether the executed write loop count of the post-programming operation is greater than the recorded write loop count. If, in step S524, the executed write loop counts of both the erase operation and the post-programming operation are not greater than the recorded write loop count, then the erase operation can be completed. Conversely, if the executed write loop counts of the erase operation and / or the post-programming operation are greater than the recorded erase loop count, then in step S525, the controller updates the recorded write loop count in the storage device using the executed write loop counts of the erase operation and the post-programming operation, and the erase operation can be completed. In this embodiment, the executed write loop counts of the erase operation and the post-programming operation are the recorded executed write loop counts of the erase operation and the post-programming operation during the erase operation period before the erase verification is determined to be successful.

[0047] Please refer to Figure 6 This diagram illustrates the relationship between write cycle information recorded by a storage device according to another embodiment of the present disclosure and the corresponding write operation settings. In this embodiment, the storage device 110 is, for example, composed of a one-time programming (OTP) memory cell. Please refer to [link / reference needed]. Figure 1 and Figure 6 The storage device 110 can store multiple lookup sets and corresponding multiple flag bits (maxbit) (e.g., 31 settings and corresponding flag bits maxbit <31:1>). Each lookup set is used to record the recorded write cycle count of the corresponding memory block 101 and the pulse width and bias level settings of the first write pulse in this embodiment.

[0048] Regarding the details of the lookup sets, lookup set 1 has the numeric value 1 0 0 0 0, corresponding to the recorded write cycle count of 32. Lookup set 2 has the numeric value 0 1 0 0 0, corresponding to the recorded write cycle count of 64. Lookup set 3 has the numeric value 1 1 0 0 0, corresponding to the recorded write cycle count of 32 + 64 = 96, and so on. When the executed write cycle count of a write operation on memory block 101 exceeds a threshold (= 32), controller 101 selects the corresponding lookup set based on the executed write cycle count and writes the corresponding flag bit maxbit. Figure 6 In the example, lookup set 0 (the number of recorded write loop counts is less than the threshold) can be used as the default value and does not need to be recorded in storage device 110.

[0049] In this embodiment, lookup sets 1 to 31, along with their corresponding pulse widths and bias levels, can also be recorded in the storage device 110. If necessary, the values ​​of the pulse width and bias level can be adjusted via the controller 120.

[0050] According to this embodiment, when the controller 120 receives a write command, it performs a write operation on the memory block 101 based on the settings in the lookup table. Each write operation includes a large first write pulse and multiple small second write pulses. Each write pulse is followed by a read verification to verify whether the write was successful. Specifically, the controller 120 sets the pulse width and voltage level of the first write pulse according to the settings in the lookup table, and sets the pulse width and voltage level of the second write pulse according to the default values.

[0051] In one embodiment, the default values ​​of the first write pulse and the second write pulse can be stored as power-on information in the power-on area of ​​the write cycle recording device 100, and read into the buffer when the write cycle recording device 100 is powered on. Figure 6 In the example description, the second write pulse is preset to have a pulse width of, for example, 1 millisecond and a bias level of 1. Furthermore, the first write pulse is preset to have a pulse width of, for example, 0 milliseconds and a bias level of 1 (lookup table 0).

[0052] If the recorded write cycle count is less than the threshold (=32), the controller can perform a write operation on memory block 101 in the first mode. In the first mode, the controller 120 can set the pulse width and voltage level of the first and second write pulses using default values. Figure 6 In the example, the controller, based on the default value, will not apply the first write pulse (pulse width = 0), but will only apply multiple second write pulses.

[0053] If the recorded write cycle count is greater than a threshold (=32), the controller can perform a write operation on memory block 101 in a second mode. In the second mode, the controller 120 performs a write operation on the selected memory block 101 based on a lookup set read from the memory cell. Specifically, the controller 120 first reads the lookup set corresponding to the largest flag bit in the flag bits maxbit<31:1> from the storage device 110, and adjusts the pulse width and bias level of the first write bias voltage according to the lookup set. Then, the controller 120 applies a first write pulse and multiple second write pulses to memory block 101 according to the set values.

[0054] For example, if the maximum flag bit maxbit is 6 (i.e., the recorded write cycle count is equal to 192), then the controller 120 can adjust the pulse width and bias level of the first write pulse of the write operation to 192 milliseconds and level 3 according to lookup set 6 (shown as field 610).

[0055] In addition, the numeric value of the read lookup set (the recorded write loop count) can be stored in a register Reg. The register Reg can have multiple bits to store the executed write loop count and the read recorded write loop count. The number of bits in the register Reg can be adjusted according to design requirements. For example, according to... Figure 6 For example, bits 0 through 8 of the register Reg can correspond to the numbers 2, 4, 8, 16, 32, 64, 128, 256, and 512, respectively. The register value Reg<3:0> represents the number of write loops executed, while the register value Reg<8:4> represents the digit value of the read lookup set. For instance, when the read lookup set is lookup set 6, the digit value 0 1 1 0 0 stored in lookup set 6 can be stored as the register value Reg<8:4>.

[0056] Figure 7 Shown according to this disclosure Figure 6 The flowchart illustrates a write operation of a storage device for non-volatile memory in an embodiment. In step S710, the write command is received by the controller of the non-volatile memory. Please refer to [link / reference needed]. Figure 7 and Figure 6 In step S720, the controller pre-reads the lookup set corresponding to the maximum flag bit stored in the storage device, and the controller stores the digit value of the lookup set as the buffer value Reg<8:4>.

[0057] In step S730, the controller sets the pulse width and bias level of the write operation to apply multiple write pulses to the memory block and verify the read, while counting the number of write cycles performed and storing it as a buffer value Reg<3:0>.

[0058] Here, when no set flag bit is found in step S720, the controller can perform a write operation on the memory in the first mode. That is, the controller will apply a first write pulse and perform a verification read to the memory according to the default value. After that, the controller will continue to apply multiple second write pulses and perform verification reads to the memory block until the verification read is successful.

[0059] When the corresponding lookup set is read based on the maximum flag bit in step S720, the controller adjusts the pulse width and bias level of the first write pulse according to the set value corresponding to the lookup set, and applies the first write pulse and performs a verification read to the memory block. Afterwards, the controller continues to apply multiple second write pulses and perform verification reads to the memory block according to the default values ​​until the verification read is successful.

[0060] In step S740, when the verification read passes, the controller can read a portion of the buffer value Reg<3:0> (i.e., the write loop count). In step S750, the controller compares a portion of the buffer value Reg<3:0> with a predefined number (e.g., binary code 1111). If the portion of the buffer value Reg<3:0> is not equal to the predefined number, the write operation is complete. If the portion of the buffer value Reg<3:0> is equal to the predefined number, the controller can set the flag bit of the next lookup set in step S760, and the write operation is complete. For example, if the pre-read lookup set is lookup set 6, and the buffer value Reg<0:3> for the write loop count is 1111 when the write verification read passes, the controller can set the control bit of lookup set 7 in step S740. In the next write operation, the controller will instead perform the write operation on the memory block according to the pulse width and bias level corresponding to lookup value 7.

[0061] In general, this disclosure provides a storage device for storing a recorded write cycle count corresponding to a memory block in non-volatile memory. When a new write operation is performed on a memory block, the controller can determine a better write operation scheme based on the recorded write cycle count. This can thus improve the efficiency of the write operation. It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that this invention cover modifications and variations thereof, provided that such modifications and variations fall within the scope of the appended claims and their equivalents.

Claims

1. A write cycle recording device, comprising: A storage device corresponding to a memory block of non-volatile memory, wherein the storage device has multiple bits for recording multiple recorded write cycle counts corresponding to multiple write operations of the memory block; as well as A controller, coupled to the storage device and the memory block, is configured to: Perform a write operation on the memory block; Record the write loop count performed during the write operation; as well as The written cycle count recorded in the storage device corresponding to the written operation is updated based on the executed write cycle count. During the execution of the write operation, the controller is further configured to: Pre-read the storage device to obtain the record write cycle count; Obtain the count of the number of write cycles performed during the write operation; Compare the recorded write loop count with the executed write loop count; and When the executed write loop count is greater than the recorded write loop count, the bit in the storage device corresponding to the recorded write loop count is updated according to the executed write loop count.

2. The write cycle recording device according to claim 1, wherein the write operation includes a programming operation and an erase operation.

3. The write cycle recording device according to claim 2, wherein the write operation further includes a post-programming operation and a refresh operation.

4. The write cycle recording device according to claim 1, wherein the storage device stores a plurality of index values, and the plurality of index values ​​correspond to the plurality of recorded write cycle counts respectively.

5. The write cycle recording device according to claim 1, wherein the controller sets at least one of the bias level and pulse width of the write pulse for the write operation based on the recorded write cycle count.

6. The write cycle recording apparatus according to claim 1, wherein the controller is further configured to: Set up multiple lookup sets corresponding to the recorded write loop count; Based on the recorded write cycle count, one of the lookup sets is selected to obtain the first pulse width and first bias level of the first write pulse. When the recorded write cycle count is not greater than a threshold, the write operation is performed in the first mode; and when the recorded write cycle count is greater than the threshold, the controller performs the write operation in the second mode. The first mode differs from the second mode. In the first mode, the controller performs the write operation by applying a plurality of second write pulses having a preset second bias level and a second pulse width. In the second mode, the controller performs the write operation by applying the first write pulse to the memory block and then applying the second write pulse to the memory block.

7. The write cycle recording device according to claim 6, The first bias level is greater than the second bias level, and the first pulse width is greater than the second pulse width.

8. The write cycle recording device according to claim 7, wherein the controller records the recorded write cycle count as a plurality of register values ​​and adjusts the first bias level and the first pulse width according to the register values.

9. The write cycle recording device according to claim 8, wherein when the verification operation of the write operation is passed, the controller checks whether the register value of the portion has reached a predefined number, and when the register value of the portion reaches the predefined number, the controller updates the recorded write cycle count to the next count state.

10. A non-volatile memory, comprising: At least one memory block, wherein each of the at least one memory block has a plurality of memory libraries; A storage device is disposed in at least one memory block corresponding to at least one memory block of the non-volatile memory, wherein the storage device has a plurality of bits for recording a plurality of recorded write cycle counts corresponding to a plurality of write operations of the memory block; as well as A controller, coupled to the storage device and the memory block, is configured to: Perform a write operation on the memory block; Record the write loop count performed during the write operation; as well as The written cycle count recorded in the storage device corresponding to the written operation is updated based on the executed write cycle count. During the execution of the write operation, the controller is configured to: The storage device is pre-read to obtain the recorded write cycle count for the write operation; Obtain the count of the number of write cycles performed during the write operation; Compare the executed write loop count with the executed write loop count; as well as When the executed write loop count is greater than the recorded write loop count, the bit in the storage device corresponding to the recorded write loop count is updated according to the executed write loop count.

11. The non-volatile memory of claim 10, wherein the write operation includes a programming operation and an erase operation.

12. The non-volatile memory according to claim 10, wherein the write operation further includes a post-programming operation and a refresh operation.

13. The non-volatile memory of claim 10, wherein the controller sets at least one of a bias level and a pulse width for the write pulse used in the write operation based on a recorded first write cycle count.

14. The non-volatile memory of claim 10, wherein the controller is further configured to: Set up multiple lookup sets corresponding to the recorded write loop count; Based on the recorded write cycle count, one of the lookup sets is selected to obtain the first pulse width and first bias level of the first write pulse. When the recorded write cycle count is not greater than a threshold, the write operation is performed in the first mode; and when the recorded write cycle count is greater than the threshold, the controller performs the write operation in the second mode. The first mode differs from the second mode. In the first mode, the controller performs the write operation by applying a plurality of second write pulses having a preset second bias level and a second pulse width. In the second mode, the controller performs the write operation by applying the first write pulse to the memory block and then applying a plurality of second write pulses to the memory block.

15. The non-volatile memory of claim 14, wherein the first bias level is greater than the second bias level, and the first pulse width is greater than the second pulse width.

16. The non-volatile memory of claim 15, wherein the controller records the written cycle count as a plurality of register values ​​and adjusts the first bias level and the first pulse width according to the register values.

17. The non-volatile memory of claim 16, wherein during the verification operation of the write operation, the controller checks whether the register value of the portion has reached a predefined number, and when the register value of the portion reaches the predefined number, the controller updates the recorded write cycle count to the next count state.

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