Memory cells and memory cell arrays

Abstract

The present disclosure relates to memory cells and arrays of memory cells. A memory cell includes first, second, third, and fourth transistors individually including a transistor gate. First and second ferroelectric capacitors individually have a capacitor electrode vertically interposed between the transistor gates of the first, second, third, and fourth transistors. Other memory cells are disclosed, as are arrays of memory cells.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with application number 201810954519.1, application date August 21, 2018, and invention name “Memory Cell and Memory Cell Array”. Technical Field

[0003] Embodiments disclosed herein relate to memory cells and memory cell arrays. Background Art

[0004] Memory is a type of integrated circuit used in computer systems to store data. Memory can be fabricated as one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). Digit lines electrically interconnect memory cells along the columns of the array, and access lines electrically interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of digit lines and access lines.

[0005] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time without power. Non-volatile memory is typically designated as memory having a retention time of at least about 10 years. Volatile memory is dissipative and therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of a few milliseconds or less. In any case, the memory cell is configured to hold or store memory in at least two different selectable states. In binary systems, the states are considered to be "0" or "1." In other systems, at least one individual memory cell can be configured to store information in more than two bits or states.

[0006] A capacitor is a type of electronic component that can be used in memory cells. A capacitor has two electrical conductors separated by an electrically insulating material. Energy, such as an electric field, can be stored electrostatically within such a material. Depending on the composition of the insulating material, the stored field will be either volatile or non-volatile. For example, a capacitor insulating material consisting solely of SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor, which has a ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarization states and can thus comprise the programmable material of a capacitor and / or memory cell. The polarization state of a ferroelectric material can be changed by applying a suitable programming voltage and remains constant (for at least a period of time) after the programming voltage is removed. Each polarization state has a different capacitance for storing charge and can ideally be used to write (i.e., store) and read (i.e., determine) a memory state without reversing the polarization state until it is desired to reverse such a polarization state. Less undesirably, in certain memories having ferroelectric capacitors, the act of reading a memory state may reverse the polarization state. Therefore, after the polarization state is determined, the memory cell is rewritten to place the memory cell in the pre-read state immediately after the polarization state is determined. Regardless, memory cells incorporating ferroelectric capacitors are ideally non-volatile due to the bistability of the ferroelectric material forming part of the capacitor.

[0007] Field effect transistors are another type of electronic component that can be used for memory cells. These transistors include a pair of source / drain regions with a semiconductor channel region between them. A conductive gate is adjacent to the channel region and separated from the channel region by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a region that can be reversibly programmable to store charge as part of the gate structure between the gate insulator and the conductive gate. Field effect transistors may be ferroelectric, wherein at least some portion of the gate structure (e.g., the gate insulator) includes a ferroelectric material. The two different polarization states of the ferroelectric material in the transistor may be characterized by different threshold voltages (V t ) or in different channel conductivities at selected operating voltages.

[0008] An individual memory cell may contain one or more transistors and one or more capacitors. Summary of the Invention

[0009] In one aspect, the present disclosure relates to a memory cell comprising: first, second, third, and fourth transistors; and first and second ferroelectric capacitors, each having a capacitor electrode at two vertically spaced levels, a ferroelectric capacitor insulator interposed between the capacitor electrode and the other capacitor electrode in one of the two levels, and no ferroelectric capacitor insulator interposed between the capacitor electrode and the other capacitor electrode in the other of the two levels. (Paragraph

[0007] )

[0010] In another aspect, the present disclosure relates to an array comprising the memory cell indicated in paragraph

[0007] as one of a plurality of memory cells having similar construction relative to one another, wherein one of the capacitor electrodes is one of the ferroelectric capacitors of the plurality of memory cells and is common to the ferroelectric capacitors.

[0011] In another aspect, the present disclosure relates to an array comprising the memory cell indicated in paragraph

[0007] as one of a plurality of memory cells having similar construction relative to each other, wherein one capacitor electrode of the first and second ferroelectric capacitors in the individual memory cells is electrically isolated from each other; and the other capacitor electrode of the first and second ferroelectric capacitors in the individual memory cells is electrically isolated from each other.

[0012] In yet another aspect, the present disclosure relates to a memory cell comprising: first, second, third, and fourth transistors, each including a transistor gate; and first and second ferroelectric capacitors, each having a capacitor electrode vertically interposed between the transistor gates of the first, second, third, and fourth transistors. (Paragraph

[0010] )

[0013] In another aspect, the present disclosure relates to an array comprising the memory cell indicated in paragraph

[0010] as one of a plurality of memory cells having similar construction relative to each other, wherein one capacitor electrode is one of the capacitor electrodes of all ferroelectric capacitors of the plurality of memory cells and is common to all of the ferroelectric capacitors.

[0014] In another aspect, the present disclosure relates to an array comprising the memory cell indicated in paragraph

[0010] as one of a plurality of memory cells having similar structures relative to each other, wherein the first and second ferroelectric capacitors individually have another capacitor electrode; one capacitor electrode in the first and second ferroelectric capacitors in the individual memory cells is electrically isolated from each other; and the other capacitor electrodes in the first and second ferroelectric capacitors in the individual memory cells are electrically isolated from each other.

[0015] In another aspect, the present disclosure relates to a memory cell comprising: first, second, third and fourth transistors; and first and second ferroelectric capacitors, each comprising a first and second capacitor electrode, the first and second capacitor electrodes having a ferroelectric capacitor insulator therebetween, the first capacitor electrode comprising a vertically extending post, the ferroelectric capacitor insulator comprising a ring extending radially outward from the first capacitor electrode, and the second capacitor electrode comprising a portion extending radially outward from the ferroelectric-capacitor-insulator ring.

[0016] In another aspect, the present disclosure relates to a memory cell comprising: first and second laterally spaced and vertically extending pillars; first and second ferroelectric capacitors, each comprising a first and second capacitor electrode, the first and second capacitor electrodes having a ferroelectric capacitor insulator therebetween; first, second, third and fourth vertically extending transistors, each comprising a source / drain region, a vertically extending channel region between the source / drain regions and a transistor gate operably proximate to the channel region, the channel regions of the first and second transistors being laterally adjacent to each other above the second capacitor electrode; the channel regions of the third and fourth transistors being laterally adjacent to each other below the second capacitor electrode; a first pillar comprising the source / drain regions and the channel regions of the first and third transistors, the first pillar comprising the first capacitor electrode of the first ferroelectric capacitor; and a second pillar comprising the source / drain regions and the channel regions of the second and fourth transistors, the second pillar comprising the first capacitor electrode of the second ferroelectric capacitor.In another aspect, the present disclosure relates to a memory cell array comprising rows and columns of a plurality of ferroelectric capacitors, wherein pairs of adjacent ferroelectric capacitors within two rows of the ferroelectric capacitors comprise the two ferroelectric capacitors of an individual memory cell, the two ferroelectric capacitors individually comprising first and second capacitor electrodes, the first and second capacitor electrodes having a ferroelectric capacitor insulator therebetween, the ferroelectric capacitor insulator comprising a ring extending radially outward from the first capacitor electrode, the second capacitor electrode comprising a portion extending radially outward from the ferroelectric capacitor insulator ring and being the second capacitor electrode in all of the plurality of ferroelectric capacitors and being common to all of the plurality of ferroelectric capacitors; the columns comprising pairs of first and second comparative digital lines within the columns; the rows and columns comprising short-circuit transistors, the short-circuit transistors individually comprising a transistor gate, the transistor gate comprising a portion of an individual short-circuit control line interconnecting a plurality of the short-circuit transistors along the individual rows, the pairs of adjacent short-circuit transistors within two rows comprising the first and second transistors of the individual memory cell, the individual memory cells The first two short-circuit transistors are individually directly electrically coupled to different capacitor electrodes in the respective first capacitor electrodes and the common second capacitor electrode and are directly electrically coupled between the different capacitor electrodes; the rows and columns of selection transistors are included, the selection transistors individually including a transistor gate, the transistor gate including a portion of an individual word line that interconnects multiple selection transistors along the individual rows, the pairs of selection transistors adjacent to each other in the two rows including the second two transistors of the individual memory cells, the second two selection transistors in the individual memory cells are individually directly electrically coupled to different first capacitor electrodes in the respective first capacitor electrodes and different comparative digit lines in the first or second comparative digit lines in the pairs of the individual first and second comparative digit lines and are directly electrically coupled between the different first capacitor electrodes and the different comparative digit lines; and one of (a) the word line or (b) the short-circuit control line, which is above all of the multiple ferroelectric capacitors, and the other of (a) or (b) is below all of the multiple ferroelectric capacitors.

[0017] In another aspect, the present disclosure relates to a memory cell array comprising: rows and columns comprising ferroelectric capacitors, the ferroelectric capacitors individually comprising first and second capacitor electrodes, the first and second capacitor electrodes having a ferroelectric capacitor insulator therebetween, the ferroelectric capacitor insulator comprising a ring extending radially outward from the first capacitor electrode, the second capacitor electrode comprising a portion extending radially outward from the ferroelectric-capacitor-insulator ring, the first capacitor electrodes in the two ferroelectric capacitors of the individual memory cells being electrically isolated from each other, and the second capacitor electrodes in the two ferroelectric capacitors of the individual memory cells being electrically isolated from each other; the columns comprising a pair of first comparative digit lines within the columns and a pair of second comparative digit lines within the columns, the individual memory cells comprising one of the first comparative digit lines and one of the second comparative digit lines; the rows and columns comprising shorting transistors, the shorting transistors individually comprising a transistor gate comprising a portion of an individual shorting control line interconnecting a plurality of the shorting transistors along the individual rows, each other pair of the shorting transistors in the individual rows comprising the individual memory cells. said first two transistors of said individual memory cells, said first two shorting transistors in said individual memory cells being individually directly electrically coupled to and between different first capacitor electrodes of said respective first capacitor electrodes and different second capacitor electrodes of said respective second capacitor electrodes; said rows and columns comprising select transistors, said select transistors individually comprising a transistor gate comprising a portion of an individual word line interconnecting a plurality of said select transistors along said individual rows, each other pair of said select transistors in said individual rows comprising said second two transistors of said individual memory cells, said second two select transistors in said individual memory cells being individually directly electrically coupled to and between different first capacitor electrodes of said respective first capacitor electrodes and different comparative digit lines of said respective first or second comparative digit lines; and one of (a) said word line or (b) said shorting control line being above all of said ferroelectric capacitors, the other of (a) or (b) being below all of said ferroelectric capacitors. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a non-structural diagrammatic representation of a single 4T-2FC memory cell according to one embodiment of the present invention.

[0019] Figure 2 According to an embodiment of the present invention Figure 1A diagrammatic mixed schematic and structural perspective view of a portion of an array of multiple 4T-2FC memory cells.

[0020] Figure 3 is through Figure 4 and 5 A cross-sectional view taken along line 3-3 in FIG.

[0021] Figure 4 is through Figure 3 and 5 A cross-sectional view taken along line 4-4 in FIG.

[0022] Figure 5 is through Figure 3 and 4 A cross-sectional view taken along line 5-5 in FIG.

[0023] Figure 6 According to an embodiment of the present invention Figure 1 A diagrammatic mixed schematic and structural cross-sectional view of a portion of another array of a plurality of 4T-2FC memory cells of the schematic diagram, and corresponding to Figure 3 A cross-sectional view of the structure shown.

[0024] Figure 7 Is the basis of display Figures 1 to 6 Voltage versus time graphs of some possible operating characteristics of an embodiment of a 4T-2FC memory cell.

[0025] Figure 8 is a non-structural diagrammatic representation of a single 4T-2FC memory cell according to an embodiment of the present invention.

[0026] Figure 9 According to an embodiment of the present invention Figure 8 A diagrammatic mixed schematic and structural perspective view of a portion of an array of multiple 4T-2FC memory cells.

[0027] Figure 10 is through Figure 11 and 12 A cross-sectional view taken along line 10-10 in FIG.

[0028] Figure 11 is through Figure 10 and 12 A cross-sectional view taken along line 11-11 in FIG.

[0029] Figure 12 is through Figure 10 and 11 A cross-sectional view taken along line 12-12 in FIG.

[0030] Figure 13According to an embodiment of the present invention Figure 8 A diagrammatic mixed schematic and structural cross-sectional view of a portion of another array of a plurality of 4T-2FC memory cells of the schematic diagram, and corresponding to Figure 10 A cross-sectional view of the structure shown.

[0031] Figure 14 Is the basis of display Figures 8 to 13 Voltage versus time graphs of some possible operating characteristics of an embodiment of a 4T-2FC memory cell.

[0032] Figure 15 is a graph of the hysteresis loop of a ferroelectric capacitor. DETAILED DESCRIPTION

[0033] Embodiments of the present invention include single memory cells that individually have four transistors and two ferroelectric capacitors (e.g., in some embodiments, the same total number of transistors and capacitors in a single memory cell regardless of its schematic, and hereinafter referred to as a 4T-2FC memory cell), as well as arrays of such memory cells. Referring first to Figures 1 to 6 A first embodiment thereof is described, wherein Figure 1 is a schematic diagram of a single 4T-2FC memory cell MC0 according to some embodiments.

[0034] refer to Figures 2 to 5 , the substrate construction 10 includes a base substrate 11, which may include any one or more of conductive / conductor / conductive (i.e., electrically herein), semiconductive / semiconductor / semiconductive or insulating / insulator / insulating (i.e., electrically herein) materials. Various materials have been vertically formed above the base substrate 11. The materials may be Figures 2 to 5 Beside the material depicted, Figures 2 to 5 The material depicted is directed vertically inward or from Figures 2 to 5 The depicted material is oriented vertically outward. For example, other partially or fully fabricated components of the integrated circuit may be disposed somewhere above, around, or within base substrate 11. Control and / or other peripheral circuitry for operating components within the memory cell array may also be fabricated and may or may not be entirely or partially within the memory array or sub-array. Furthermore, multiple memory sub-arrays may be constructed and operated independently, in tandem, or in other ways relative to one another. As used in this document, "sub-array" may also be considered an array.

[0035] The construction 10 includes an array 13 of 4T-2FC memory cells (eg, MC0, MC1). Figures 2 to 5 Only six ( Figure 5) portions of memory cells MC0 and MC1, where an array may have thousands, hundreds of thousands, millions, etc. of similarly constructed memory cells MC* (the symbol "*" is used herein as a generic substitute for any specific numbered component). Array 13 includes rows 12 and columns 14, including a plurality of ferroelectric capacitors (e.g., FC0T, FC0B, FC1T, FC1B). Immediately adjacent pairs of ferroelectric capacitors within two rows (e.g., pairs FC0T, FC0B and pairs FC1T, FC1B) include two ferroelectric capacitors of respective 4T-2FC memory cells MC*. The two ferroelectric capacitors individually include a first capacitor electrode (e.g., CBT0, CBB0, CBT1, CBB1) and a second capacitor electrode (e.g., CP) with a ferroelectric capacitor insulator 16 therebetween. The ferroelectric capacitor insulator 16 includes a ring 18 radially outward from its first capacitor electrode CBT* or CBB*. The second capacitor electrode CP includes a portion 20 ( Figure 5 ). Furthermore, in this example embodiment, the second capacitor electrode CP is the second capacitor electrode of all the plurality of ferroelectric capacitors FC*T, FC*B and is common to all the plurality of ferroelectric capacitors FC*T, FC*B.

[0036] Column 14 includes pairs of first comparative digital lines (e.g., DLT0, DLT1) and second comparative digital lines (e.g., DLB0, DLB1) that are immediately adjacent to each other within the column (e.g., pair DLT0, DLB0 and pair DLT1, DLB1). Such pairs can be individually connected to read / sense amplifiers SA ( Figure 1 , which may be constructed at the edge of the array 13), the read / sense amplifier SA may be used to amplify the difference signal generated on the digital line pair when the memory cell MC* is read.

[0037] The rows 12 and columns 14 include shorting transistors (eg, MCBRT0, MCBRB0, MCBRT1, MCBRB2) that individually include transistor gates 28 ( Figure 4 ), the transistor gate 28 comprises a portion of an individual shorting control line (e.g., CBR0, CBR1, CBR2) that interconnects a plurality of the shorting transistors along an individual row 12. Two immediately adjacent pairs of intra-row shorting transistors (e.g., pair MCBRT0, MCBRB0 and pair MCBRT1, MCBRB1) comprise the first two transistors of an individual 4T-2FC memory cell MC*. Such first two shorting transistors in an individual 4T-2FC memory cell MC* are individually directly electrically coupled to and between different ones of the respective first capacitor electrodes CBT*, CBB* and the common second capacitor electrode CP.

[0038] The rows 12 and columns 14 include select transistors (eg, MWL0T, MWL0B, MWL1T, MWL1B, and which may alternatively be considered access transistors) that individually include transistor gates 40 ( Figure 4 ), the transistor gate 40 comprises a portion of a respective word line (e.g., WL0, WL1, WL2) interconnecting a plurality of the select transistors along a respective row 12. Two immediately adjacent pairs of select transistors within a row (e.g., pairs MWL0T, MWL0B and MWL1T, MWL1B) comprise the second two transistors of a respective 4T-2FC memory cell MC*. Such second two select transistors in a respective 4T-2FC memory cell MC* are individually directly electrically coupled to, and between, a different first capacitor electrode of the respective first capacitor electrodes CBT*, CBB* and a different first comparative digit line DLT* or second comparative digit line DLB* of a respective pair of first and second comparative digit lines (e.g., DLT0 / DLB0, DLT1 / DLB1).

[0039] One of (a) the word line or (b) the short-circuit control line is above all of the plurality of ferroelectric capacitors, and the other of (a) or (b) is below all of the plurality of ferroelectric capacitors. Figures 2 to 5 Depicts an embodiment where (b): shorting control lines are placed over all of the plurality of ferroelectric capacitors. An alternative embodiment of array 13a is constructed 10a in Figure 6 (Similar to Figure 3 ), wherein (a): the word line is above all multiple ferroelectric capacitors. The same reference numerals of the embodiments described above have been used where appropriate, with the suffix "a" indicating certain construction differences. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used Figure 6 Example.

[0040] In one embodiment, all first and second comparative digit lines are above or below all ferroelectric capacitors with word lines. In other words, in this embodiment, all first and second comparative digit lines are above or below all ferroelectric capacitors on either the upper or lower side of the word lines, and by way of example only, relative to Figures 2 to 5 Examples and Figure 6 In one such embodiment, the word lines are below all ferroelectric capacitors and all first and second comparative digit lines are below all word lines (e.g., Figures 2 to 5 In an alternative such embodiment, the word lines are above all ferroelectric capacitors and all first and second comparative digit lines are above all word lines (e.g., Figure 6 Example).

[0041] In one embodiment and as shown, the shorting transistor and the select transistor are vertically extending transistors, and in one such embodiment are vertical or within 10° of vertical. In one embodiment, the 4T-2FC memory cells MC* individually include a first vertically extending pillar (e.g., 24) and a second vertically extending pillar (e.g., 26) that are spaced apart within a row relative to each other. In this embodiment, the shorting transistor and the select transistor of an individual 4T-2FC memory cell MC* can be considered to individually include source / drain regions and a vertically extending channel region therebetween. For example, Figure 3 and 4 Short-circuit transistors MCBRT*, MCBRB* are shown, each comprising a source / drain region 35, source / drain regions CBT0, CBB0 CBT1, CBB1, and a vertically extending channel region 32 therebetween. The source / drain region 35 and the second capacitor electrode CP may be considered a single or collective electrode, with the two vertically spaced CP portions thereof depicted being in the same direction. Figures 2 to 6 In one embodiment, the memory cells 10 and 11 are directly electrically coupled to each other (e.g., via a schematic interconnect line 25, which may be configured at the edge of the array 13). Furthermore, for example, the select transistors MWL*T, MWL*B of each 4T-2FC memory cell MC* each include a source / drain region 37, source / drain regions CBT0, CBB0, CBT1, CBB1, and a vertically extending channel region 33 therebetween. The channel regions 32 of the short-circuit transistors MCBRT, MCBRB are spaced apart from each other in a row at one level 36, and the channel regions 33 of the select transistors MWL*T, MWL*B are spaced apart from each other in a row at another level 34 that is vertically spaced apart from the level 36.

[0042] The first pillar 24 individually includes the respective channel regions 32, 33 of one of the short-circuit transistors MCBRT*, MCBRB* and one of the select transistors MWL*T, MWL*B of the respective 4T-2FC memory cell MC*. The first pillar 24 also individually includes the source / drain regions of the respective short-circuit transistor and the respective select transistor of the respective 4T-2FC memory cell MC*. The first pillar 24 also individually includes the first capacitor electrode CBBT*, CBBB* of one of the two ferroelectric capacitors of the respective 4T-2FC memory cell MC*. The second pillar 26 individually includes the respective channel regions 32, 33 of the other short-circuit transistor and the other select transistor of the respective 4T-2FC memory cell MC*. The second pillar 26 also individually includes the source / drain regions of the respective other short-circuit transistor and the respective other select transistor of the respective 4T-2FC memory cell MC*. The second pillar 26 also individually includes the first capacitor electrode of the other of the two ferroelectric capacitors of the respective 4T-2FC memory cell MC*.

[0043] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used Figures 1 to 5 Example.

[0044] Next reference Figures 8 to 12 An alternative example embodiment, configuration 10b, of an array 13b of 4T-2FC memory cells MC* is described. Like reference numerals from the embodiments described above have been used where appropriate, with certain configuration differences indicated by a suffix "b" or by different reference numerals. Configuration 10b differs from configuration 10 in part in that the second capacitor electrodes of the ferroelectric capacitors are not common to all of the plurality of ferroelectric capacitors. Instead, array 13b has the second capacitor electrodes (e.g., CP1, CP2) of the two ferroelectric capacitors (e.g., FC*T, FC*B) of the individual 4T-2FC memory cells MC* electrically isolated from one another (i.e., CP1 and CP2 are not directly electrically coupled to one another). The first capacitor electrodes CBT*, CBB* of the two ferroelectric capacitors of the individual 4T-2FC memory cells MC* are also electrically isolated from one another, and are, for example, as shown in the first-described embodiment. As with the depicted two vertically spaced CP1 portions, the depicted two vertically spaced CP1 portions are electrically coupled directly to each other (e.g., by schematic interconnect line 25 for the CP1 portion and by schematic interconnect line 27 for the CP2 portion, which may be constructed at the edge of array 13b).

[0045] Additionally, in configuration 10b, column 14 includes a pair (e.g., pair DLT0, DLT1) immediately adjacent to a first comparative digit line (DLT0, DLT1) within the column and a pair (e.g., pair DLB0, DLB1) immediately adjacent to a second comparative digit line (DLB0, DLB1) within the column. Individual memory cell MC* includes one of the first comparative digit lines DLT0 or DLT1 and one of the second comparative digit lines DLB0 or ​​DLB1. Thus, not all components of individual memory cell MC* are immediately adjacent to one another within a row, as shown, for example, in configuration 10 / 10a of the first-described embodiment.

[0046] The rows 12 and columns 14 likewise include shorting transistors MCBRT*, MCBRB*, each of which includes a transistor gate 28 that comprises a portion of a respective shorting control line CBR* that interconnects a plurality of the shorting transistors along the respective row 12. However, each other pair of shorting transistors in the respective row 12 (e.g., pair MCBRT0, MCBRB0 and pair MCBRT1, MCBRB1) comprises the first two transistors of the respective 4T-2FC memory cell MC*. The first two shorting transistors in the respective 4T-2FC memory cell MC* are individually directly electrically coupled to and between a different first capacitor electrode of the respective first capacitor electrodes CBT*, CBB* and a different second capacitor electrode of the respective second capacitor electrodes CP*, CP*.

[0047] Rows 12 and columns 14 similarly include select transistors MWL*T, MWL*B, each of which includes a transistor gate 40 comprising a portion of a respective word line WL* interconnecting multiple of the select transistors along the respective row 12. However, each other pair of select transistors in the respective row 12 (e.g., pairs MWL0T, MWL0B and MWL1T, MWL1B) includes the second two select transistors of the respective 4T-2FC memory cell MC*. The second two select transistors in the respective 4T-2FC memory cell MC* are individually directly electrically coupled to and between a different first capacitor electrode of the respective first capacitor electrodes CBT*, CBB* and a comparative digit line of the respective first or second comparison digit line DLT*, DLB*. One of (a) the word line or (b) the shorting control line is above all ferroelectric capacitors, while the other of (a) or (b) is below all ferroelectric capacitors. Figures 9 to 12 An example embodiment is depicted in which (b): a shorting control line is over all ferroelectric capacitors. Figure 13 An alternative example embodiment is shown in which (a): the word lines are above all ferroelectric capacitors. Like reference numerals from the above-described embodiments have been used where appropriate, with the suffix "c" indicating certain construction differences. Any other attributes or aspects as shown and / or described herein may be used with respect to Figures 8 to 12 Examples and Figure 13 Used together with the embodiments of

[0048] Some embodiments of the present invention include 4T-2FC memory cells, regardless of whether Figure 1 Schematic diagram, Figure 8 Schematic diagram or some other schematic diagram, and may include an array of such 4T-2FC memory cells. In one such embodiment, the 4T-2FC memory cell includes first, second, third, and fourth transistors (e.g., MCBRTO, MCBRBO, MWL0T, MWL0B, respectively). The 4T-2FC memory cell includes first and second ferroelectric capacitors (e.g., FC0T, FC0B, respectively), the first and second ferroelectric capacitors individually having one capacitor electrode (e.g., FC0T, FC0B) at two vertically spaced-apart levels (e.g., level 44, level 46). Figure 1 CP in the diagram, Figure 8 CP* in the schematic). A ferroelectric capacitor insulator (e.g., 16) is interposed between one capacitor electrode and the other capacitor electrode (e.g., CBT*, CBB*) at two levels (e.g., 44 in construction 10), and no ferroelectric capacitor insulator is interposed between one capacitor electrode and the other capacitor electrode in the other of the two levels (e.g., 46 in construction 10, at least because neither CBT* nor CBB* is located anywhere within level 46).

[0049] In one embodiment, the first, second, third, and fourth transistors each include a transistor gate (e.g., 28, 40), wherein one of the gates (e.g., 28 in configuration 10) is vertically interposed between two vertically spaced levels. In one such embodiment, another of the gates (e.g., 40 in configuration 10) is not vertically interposed between two vertically spaced levels. In one embodiment, multiple of the transistor gates (e.g., 28 in configuration 10) are vertically interposed between two vertically spaced levels. In one such embodiment, only two of the transistor gates are vertically interposed between two vertically spaced levels. In one embodiment, two of the first, second, third, and fourth transistors are short-circuit transistors (e.g., MCBR0T, MCBR0B) that are directly electrically coupled to a different capacitor electrode in a respective one of the capacitor electrodes and a different capacitor electrode in the other capacitor electrode, and are directly electrically coupled between a different capacitor electrode in a respective one of the capacitor electrodes and a different capacitor electrode in the other capacitor electrode.

[0050] In one embodiment, an array (e.g., 13, 13a) includes a 4T-2FC memory cell as one of a plurality of 4T-2FC memory cells having similar configurations relative to one another, and one capacitor electrode is common to all ferroelectric capacitors of the plurality of 4T-2FC memory cells. In another embodiment, an array (e.g., 13b, 13c) includes a 4T-2FC memory cell as one of a plurality of 4T-2FC memory cells having similar configurations relative to one another. In this embodiment, one capacitor electrode of the first and second ferroelectric capacitors in each 4T-2FC memory cell is electrically isolated from one another. In this embodiment, the other capacitor electrode of the first and second ferroelectric capacitors in each 4T-2FC memory cell is electrically isolated from one another.

[0051] Any other attributes or aspects as shown and / or described herein may be used.

[0052] Additional embodiments of the present invention include 4T-2FC memory cells, whether or not Figure 1 Schematic diagram, Figure 8Schematic diagram or some other schematic diagram, and may include an array of such 4T-2FC memory cells. In one such embodiment, the 4T-2FC memory cell includes first, second, third, and fourth transistors (e.g., MCBRTO, MCBRBO, MWL0T, MWL0B, respectively), each of which includes a transistor gate (e.g., 28, 40). The 4T-2FC memory cell includes first and second ferroelectric capacitors (e.g., FC0T, FC0B, respectively), each of which has a capacitor electrode (e.g., CBT0, CBB0) vertically interposed between the transistor gates of the first, second, third, and fourth transistors. In one embodiment, the first and second ferroelectric capacitors each have another capacitor electrode (e.g., CP, CP1, CP2), a portion of which (e.g., within level 44 in construction 10) is vertically interposed between the transistor gates of the first, second, third, and fourth transistors. In one embodiment, the first and second ferroelectric capacitors each have another capacitor electrode (e.g., CP, CP1, CP2) with only a portion of the other capacitor electrode (e.g., within level 44 in configuration 10) vertically interposed between the transistor gates of the first, second, third, and fourth transistors. In one embodiment, the array (e.g., 13, 13a, 13b, 13c) includes a 4T-2FC memory cell as one memory cell of a plurality of 4T-2FC memory cells having similar configurations relative to one another. Any other attributes or aspects as shown and / or described herein may be used.

[0053] Additional embodiments of the present invention include 4T-2FC memory cells, whether or not Figure 1 Schematic diagram, Figure 8Schematic diagram or some other schematic diagram, and may include an array of such 4T-2FC memory cells. In one such embodiment, the 4T-2FC memory cell includes first, second, third, and fourth transistors (e.g., MCBRTO, MCBRBO, MWL0T, MWL0B, respectively). The 4T-2FC memory cell includes first and second ferroelectric capacitors (e.g., FC0T, FC0B, respectively), each of which includes first and second capacitor electrodes (e.g., CBT0, CBB0 and CP, CP1, CP2, respectively), with a ferroelectric capacitor insulator (e.g., 16) therebetween. The first capacitor electrode includes a vertically extending pillar (e.g., 24, 26). The ferroelectric capacitor insulator includes a ring (e.g., 18) extending radially outward from the first capacitor electrode. The second capacitor electrode includes a portion (e.g., 20) extending radially outward from the ferroelectric-capacitor-insulator ring. In one embodiment, the conductive material of the pillars (e.g., the material of CBT*, CBB*) extends completely across all pillars in diameter.

[0054] In one embodiment, the first, second, third, and fourth transistors each include a transistor gate (e.g., 28, 40). The gates (e.g., 28 in configuration 10) of two of the first, second, third, and fourth transistors (e.g., MCBRTO, MCBRBO in configuration 10) are located above a portion of the second capacitor electrode that is radially outward from the ferroelectric-capacitor-insulator ring. The gates (e.g., 40 in configuration 10) of the other two of the first, second, third, and fourth transistors (e.g., MWL0T, MWL0B in configuration 10) are located below a portion of the second capacitor electrode that is radially outward from the ferroelectric-capacitor-insulator ring.

[0055] Any other attributes or aspects as shown and / or described herein may be used.

[0056] Additional embodiments of the present invention include 4T-2FC memory cells, whether or not Figure 1 Schematic diagram, Figure 8Schematic diagram or some other schematic diagram, and may include an array of such 4T-2FC memory cells. In one such embodiment, the 4T-2FC memory cell includes first and second laterally spaced-apart and vertically extending pillars (e.g., 24, 26, respectively). The 4T-2FC memory cell includes first and second ferroelectric capacitors (e.g., FC0T, FC0B, respectively), the first and second ferroelectric capacitors individually including first and second capacitor electrodes (e.g., CBT0, CBB0 and CP, CP1, CP2, respectively), the first and second capacitor electrodes having a ferroelectric capacitor insulator (e.g., 16) therebetween. The 4T-2FC memory cell includes first, second, third, and fourth vertically extending transistors (e.g., MCBRT0, MCBRB0, MWL0T, and MWL0B, respectively), each of which includes source / drain regions (e.g., 35, CBT0, CBB0, and 37), vertically extending channel regions (e.g., 32 and 33) interposed between the source / drain regions, and transistor gates (e.g., 28 and 40) operatively adjacent to the channel regions (e.g., with gate insulator 17 interposed between the channel and the gate). The channel regions (e.g., 32 in construction 10) of the first and second transistors (e.g., MCBRT0 and MCBRB0 in construction 10) are laterally adjacent to each other above the second capacitor electrode. The channel regions (e.g., 33 in construction 10) of the third and fourth transistors (e.g., MWL0T and MWL0B in construction 10) are laterally adjacent to each other below the second capacitor electrode. The first column includes the source / drain regions and channel regions of the first and third transistors. The first column includes the first capacitor electrode of the first ferroelectric capacitor. The second column includes the source / drain regions and channel regions of the second and fourth transistors. The second column includes the first capacitor electrode of the second ferroelectric capacitor. Any other attributes or aspects as shown and / or described herein may be used.

[0057] In some embodiments, any one or more of the vertically extending features are formed to be vertical or within 10° of vertical.

[0058] Figure 7 Is the basis of display Figures 1 to 6 4T-2FC memory cell of an embodiment of some possible operating characteristics of the voltage versus time curve. More specifically, Figure 7 yes Figures 1 to 6Timing diagram of the read and write cycle of memory cell MC0. Since the voltage difference across ferroelectric capacitors FC0T and FC0B may not be allowed, the balance signal CBR0 is at VCCP during the standby period. At the beginning of the cycle, the balance CBR0 is turned off to disconnect the cell plate CP from the other node of the ferroelectric capacitors FC0T, CBT0, which is at the same potential as the cell plate CP. The digital lines DLT0 and DLB0 are precharged to ground during the standby period. Once CBR0 is turned off, the digital lines are disconnected from the ground and become voltage floating, and the cell plate CP is raised to VMSA, while both CBT0 and CBB0 are pulled to a level similar to the level of the cell plate CP due to the capacitance of the ferroelectric capacitors being sufficiently greater than the parasitic capacitance value of CBT0 or CBB0. Then, in order to access the ferroelectric capacitors FC0T and FC0B, the word line WL0 is raised to a level as high as VCCP. Once WL0 reaches the threshold voltage of the select transistors MWL0T and MWL0B, charge transfer occurs between the digital lines DLT0 and DLB0 and the ferroelectric capacitors FC0T and FC0B, respectively. The voltage on the digital lines is formed according to their relative capacitances. The two capacitances of the ferroelectric capacitors, 0 or 1, can be determined by Figure 15 The voltage developed on the digit lines DLT0 and DLB0 can therefore be one of two values, V0 or V1:

[0059] V 数字线 =V0={C0 / (C0+C 数字线 )}x VMSA (if the cell data is 0)

[0060] V 数字线 =V1={C1 / (C1+C 数字线 )}x VMSA (if the cell data is 1)

[0061] The data on capacitors FC0T and FC0B complement each other. Therefore, if FC0T is 1, then FC0B is 0, and vice versa. Once the voltage difference formed between DLT0 and DLB0 stabilizes, the read / sense amplifier SA drives the voltage difference formed to the full-scale voltage VMSA and the ground level and the read data will eventually be written back to the capacitor as follows: when the cell plate CP is high, DLT0 is fixed to the ground level and the cell plate CP is VMSA, then data 0 is written to capacitor FC0T. On the other hand, when the cell plate CP is grounded and the digital line DLB0 is in VMSA, complementary data 1 is written to capacitor FC0B. After the data is written back to the capacitor, the digital line and the cell plate CP are driven to ground and the balance signal CBR0 is turned on to ensure that there is no voltage difference between the top and bottom nodes across the ferroelectric capacitors FC0T and FC0B. No voltage difference may be required to avoid the capacitor losing the signal in the capacitor due to imprinting or interference or retention problems. At the end of the cycle, the word line WL0 is closed to the ground level.

[0062] Figure 14 Is the basis of display Figures 8 to 13 FIG. 1 is a voltage versus time graph of some possible operating characteristics of an embodiment of a 4T-2FC memory cell MC0. Figure 14 The top graph of φ represents the potential curve of the electrode of the capacitor FC0B connected to the transistor MWL0B. Figure 14 The middle graph of shows a potential curve of the electrode of the capacitor FC0T connected to the transistor MWL0T. Figure 14 The bottom graph shows the potential curves of word line WL0 and two consecutive read-accesses, whereby a logic "0" is stored in capacitors FC0T and FC0B. Before a read-access is performed on the memory cell, the two digit lines DLT0 and DLB0 are precharged to a common bias potential VMSA = 1.6V. This corresponds to the average of the two plate potentials CP1 = 0V and CP = approximately 3.2V. Word line WL0 then becomes active with a positive edge. Transistors MWL0T and MWL0B are thereby switched "on" to conduct electricity, thereby causing charge equalization between digit lines DLT0 and DLB0 and capacitors FC0T and FC0B. For the stored logic "0," the potential of digit line DLT0 decreases slightly, while the potential of digit line DLB0 increases slightly. Next, the read / sense amplifier SA is activated, thereby amplifying the difference signal on the digit line pair DLT0 and DLB0. The read-access ends with a negative edge in the potential on word line WL0.

[0063] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "above", "bottom", "above", "below", "below...", "under...", "upward", and "downward" generally refer to a vertical direction. "Horizontal" refers to a general direction along the surface of a main substrate (i.e., within 10 degrees) and may be relative to a substrate being processed during manufacturing, and vertical is a direction generally orthogonal to horizontal. Reference to "exactly horizontal" is a direction along the surface of a main substrate (i.e., no degrees from the main substrate surface) and may be relative to a substrate being processed during manufacturing. Furthermore, as used herein, "vertical" and "horizontal" are generally perpendicular directions relative to each other and have nothing to do with the orientation of the substrate in three-dimensional space. Additionally, "vertically extending" and "vertically extending" refer to a direction that deviates from exactly horizontal by at least 45°. Furthermore, "vertically extending" and "vertically extending" with respect to a field effect transistor are referenced to the orientation of the channel length of the transistor along which current flows when operating between the source / drain regions. For bipolar junction transistors, "vertically extending" and "vertically extending" refer to the orientation of the base length along which current flows when operating between the emitter and the collector.

[0064] Furthermore, the terms "directly above," "directly below," and "directly beneath" require that the two regions / materials / components in question have at least some lateral overlap relative to one another (i.e., horizontally). Furthermore, the use of "above" without preceding "directly" merely requires that some portion of the region / material / component in question that is above another region / material / component in question is vertically outward of the other region / material / component in question (i.e., regardless of whether there is any lateral overlap between the two regions / materials / components in question). Similarly, the use of "below" without preceding "directly" merely requires that some portion of the region / material / component in question that is below / below another region / material / component in question is vertically inboard of the other region / material / component in question (i.e., regardless of whether there is any lateral overlap between the two regions / materials / components in question).

[0065] Any of the materials, regions, and structures described herein may be uniform or non-uniform, and in any case may be continuous or discontinuous over any overlying material. Furthermore, unless otherwise indicated, each material may be formed using any suitable or yet-to-be-developed technique, examples of which are atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation.

[0066] In addition, "thickness" (preceded by a non-directional adjective) used alone is defined as the average straight-line distance perpendicular to the closest surface of a given material or region having different components. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If having a variable thickness, then unless otherwise specified, the thickness refers to the average thickness, and the material or region will have a minimum thickness and a maximum thickness due to the variable thickness. As used herein, "different components" only require that those parts of the two materials or regions discussed that can directly abut each other are chemically and / or physically different, such as when the materials or regions are not uniform. If the two materials or regions discussed are not directly abutting each other, then when the materials or regions are not uniform, "different components" only require that those parts of the two materials or regions discussed that are closest to each other are chemically and / or physically different. In this document, a material, region or structure is "directly abutting" another material, region or structure when the materials, regions or structures discussed are in at least some physical contact with each other. In contrast, "over," "on," "adjacent," "along," and "against" without being preceded by "directly" encompass "directly against" as well as configurations in which intervening materials, regions, or structures are such that the materials, regions, or structures in question are not in physical contact with each other.

[0067] As used herein, regions / materials / components are "electrically coupled" relative to one another if, during normal operation, electrical current can flow continuously from one region / material / component to another region / material / component, primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between and electrically coupled to the regions / materials / components. In contrast, when regions / materials / components are referred to as "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled regions / materials / components.

[0068] In addition, the "metal material" is any one or combination of an elemental metal, a mixture or alloy of two or more elemental metals, and any conductive metal compound.

[0069] The terms "row" and "column" are used in this document for convenience in distinguishing one series or orientation of features from another series or orientation of features and along which components have been or will be formed. "Row" and "column" are used synonymously with respect to any series of regions, components, and / or features, regardless of function. Regardless, rows can be straight and / or curved and / or parallel and / or non-parallel relative to each other, and the same can be true for columns. Furthermore, rows and columns can intersect at 90° or at one or more other angles relative to each other.

[0070] As specified, the subject matter disclosed herein has been described in language more or less specific with respect to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes example embodiments. Accordingly, the claims are to be given the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A memory cell comprising: a first transistor and a second transistor disposed at a first height above the substrate; a third transistor and a fourth transistor disposed at a second height above the substrate; a first pillar vertically extending through the first transistor and the third transistor, wherein the channel region of the first transistor and the channel region of the third transistor are disposed within the first pillar; a second pillar vertically extending through the second transistor and the fourth transistor, wherein the channel region of the second transistor and the channel region of the fourth transistor are disposed within the second pillar; First and second ferroelectric capacitors, the capacitor electrode of the first ferroelectric capacitor extending vertically within the first column and between the first transistor and the third transistor, and the capacitor electrode of the second ferroelectric capacitor extending vertically within the second column and between the second transistor and the fourth transistor.

2. A memory cell according to claim 1, wherein the first ferroelectric capacitor has another capacitor electrode, a portion of which is vertically interposed between the transistor gates of the first transistor and the third transistor, and wherein the second ferroelectric capacitor has another capacitor electrode, a portion of which is vertically interposed between the transistor gates of the second transistor and the fourth transistor.

3. A memory cell according to claim 1, wherein the first ferroelectric capacitor has another capacitor electrode, only a portion of which is vertically interposed between the transistor gates of the first transistor and the third transistor, and wherein the second ferroelectric capacitor has another capacitor electrode, only a portion of which is vertically interposed between the transistor gates of the first transistor, the second transistor, the third transistor and the fourth transistor. The memory cell of claim 1 , wherein the memory cell is a 4T-2FC.

5. An array comprising the memory cell according to claim 1 as one of a plurality of memory cells having similar structures relative to each other, wherein the array comprises one capacitor electrode, the one capacitor electrode being one capacitor electrode in all of the ferroelectric capacitors of the plurality of memory cells and being common to all of the ferroelectric capacitors.

6. An array comprising the memory cell of claim 1 as one of a plurality of memory cells having similar configurations relative to one another, wherein The first and second ferroelectric capacitors each have another capacitor electrode; the capacitor electrodes in the first and second ferroelectric capacitors in respective ones of the memory cells being electrically isolated from each other; and The other capacitor electrodes of the first and second ferroelectric capacitors in the individual memory cells are electrically isolated from each other.

7. The array of claim 6, wherein the first, second, third, and fourth transistors individually extend vertically to be vertical or within 10° of vertical.

8. A memory cell comprising: first, second, third, and fourth transistors; and First and second ferroelectric capacitors, each comprising a first and second capacitor electrode, the first and second capacitor electrodes having a ferroelectric capacitor insulator therebetween, the first capacitor electrode comprising a vertically extending column, the ferroelectric capacitor insulator comprising an annulus extending radially outward from the first capacitor electrode, the second capacitor electrode comprising a portion extending radially outward from the annulus, wherein the first, second, third and fourth transistors each comprise a transistor gate; the gates of two of the first, second, third and fourth transistors are above the portion of the second capacitor electrode extending radially outward from the annulus; and the gates of the other two of the first, second, third and fourth transistors are below the portion of the second capacitor electrode extending radially outward from the annulus.

9. The memory cell of claim 8 wherein the conductive material of the pillars extends completely across all of the pillars in diameter.

10. The memory cell of claim 8, wherein the first, second, third, and fourth transistors individually extend vertically to be vertical or within 10° of vertical.

11. The memory cell of claim 8, wherein the memory cell is a 4T-2FC.

12. A memory cell comprising: first and second laterally spaced and vertically extending posts; first and second ferroelectric capacitors, respectively comprising first and second capacitor electrodes having a ferroelectric capacitor insulator therebetween; first, second, third, and fourth vertically extending transistors, each comprising a source / drain region, a vertically extending channel region interposed between the source / drain regions, and a transistor gate operatively proximate to the channel region, the channel regions of the first and second transistors being laterally adjacent to each other above the second capacitor electrode; the channel regions of the third and fourth transistors being laterally adjacent to each other below the second capacitor electrode; a first column; comprising the source / drain regions and the channel regions of the first and third transistors, the a first column comprising said first capacitor electrode of said first ferroelectric capacitor; and a second column comprising the source / drain regions and the channel region of the second and fourth transistors, the second column comprising the first capacitor electrode of the second ferroelectric capacitor.

13. The memory cell of claim 12, wherein the first, second, third, and fourth transistors are individually vertically extending vertically or within 10° of vertical.

14. A memory cell array comprising: comprising rows and columns of a plurality of ferroelectric capacitors, wherein pairs of two immediately adjacent ferroelectric capacitors within a row of the ferroelectric capacitors comprise two ferroelectric capacitors of an individual memory cell, the two ferroelectric capacitors individually comprising first and second capacitor electrodes, the first and second capacitor electrodes having a ferroelectric capacitor insulator therebetween, the ferroelectric capacitor insulator comprising a band extending radially outward from the first capacitor electrode, the second capacitor electrode comprising a portion extending radially outward from the ferroelectric capacitor insulator band and being the second capacitor electrode in and common to all of the plurality of ferroelectric capacitors; said column including an inner column immediately adjacent a pair of first and second comparative digit lines; the rows and columns comprising shorting transistors, the shorting transistors individually comprising a transistor gate comprising a portion of a respective shorting control line interconnecting a plurality of the shorting transistors along the respective rows, the pairs of two immediately adjacent shorting transistors within the row comprising first two transistors of the respective memory cells, the first two shorting transistors in the respective memory cells individually being directly electrically coupled to and between different ones of the respective first and second capacitor electrodes; the rows and columns comprising select transistors, the select transistors individually comprising a transistor gate comprising a portion of a respective word line interconnecting a plurality of the select transistors along the respective row, the pairs of two immediately adjacent select transistors within the row comprising second two select transistors of the respective memory cells, the second two select transistors in the respective memory cells individually being directly electrically coupled to and between a different one of the respective first capacitor electrodes and a different one of the first or second comparative digit lines in the respective pair of first and second comparative digit lines; and One of (a) the word line or (b) the short-circuit control line is above all of the plurality of ferroelectric capacitors, and the other of (a) or (b) is below all of the plurality of ferroelectric capacitors.

15. The array of claim 14, wherein (a): the word line is over all of the plurality of ferroelectric capacitors.

16. The array of claim 14, wherein (b): the shorting control line is over all of the plurality of ferroelectric capacitors.

17. The array of claim 14 wherein all of the first and second comparative digit lines are above or below all of the ferroelectric capacitors with the word lines.

18. The array of claim 17 wherein the word line is below all of the ferroelectric capacitors and all of the first and second comparative digit lines are below all of the word lines.

19. The array of claim 17 wherein the word line is above all of the ferroelectric capacitors and all of the first and second comparative digit lines are above all of the word lines.

20. The array of claim 14, wherein the shorting transistor and the selection transistor are vertically extending transistors.

21. The array of claim 20 wherein the memory cells individually comprise first and second pillars spaced apart and extending vertically within a row; the shorting transistor and the select transistor of the individual memory cells individually including source / drain regions and a vertically extending channel region therebetween, the channel regions of the shorting transistors being spaced apart from each other in a row at one level, and the channel regions of the select transistors being spaced apart from each other in a row at another level vertically spaced apart from the one level; the first column including the channel region and the source / drain region of one of the shorting transistors and one of the select transistors of the individual memory cell, the first column including the first capacitor electrode of one of the two ferroelectric capacitors of the individual memory cell; and The second column includes the channel region and the source / drain regions of the other of the shorting transistors and the other of the select transistors of the individual memory cell, and the second column includes the first capacitor electrode of the other of the two ferroelectric capacitors of the individual memory cell.

22. A memory cell array comprising: comprising rows and columns of ferroelectric capacitors, the ferroelectric capacitors individually comprising first and second capacitor electrodes, the first and second capacitor electrodes having a ferroelectric capacitor insulator therebetween, the ferroelectric capacitor insulator comprising a band extending radially outward from the first capacitor electrode, the second capacitor electrode comprising a portion extending radially outward from the band, the first capacitor electrodes in two ferroelectric capacitors of an individual memory cell being electrically isolated from one another, and the second capacitor electrodes in the two ferroelectric capacitors of the individual memory cell being electrically isolated from one another; the column including a pair of first comparative digit lines immediately adjacent to the column and a pair of second comparative digit lines immediately adjacent to the column, the individual memory cells including one of the first comparative digit lines and one of the second comparative digit lines; the rows and columns comprising shorting transistors, the shorting transistors individually comprising a transistor gate comprising a portion of an individual shorting control line interconnecting a plurality of the shorting transistors along the individual row, each other pair of the shorting transistors in the individual row comprising first two shorting transistors of the individual memory cell, the first two shorting transistors in the individual memory cell individually being directly electrically coupled to and between a different first one of the respective first capacitor electrodes and a different second one of the respective second capacitor electrodes; the rows and columns comprising select transistors, the select transistors individually comprising a transistor gate comprising a portion of a respective word line interconnecting a plurality of the select transistors along the respective row, each other pair of the select transistors in the respective row comprising a second two select transistors of the respective memory cell, the second two select transistors in the respective memory cell individually being directly electrically coupled to and between a different one of the respective first capacitor electrodes and a different one of the respective first or second comparison digit lines; and One of (a) the word line or (b) the short-circuit control line is above all of the ferroelectric capacitors, and the other of (a) or (b) is below all of the ferroelectric capacitors.

23. The array of claim 22, wherein (a): the word line is over all of the ferroelectric capacitors.

24. The array of claim 22, wherein (b): the shorting control line is over all of the ferroelectric capacitors.

25. The array of claim 22 wherein all of the first and second comparative digit lines are above or below all of the ferroelectric capacitors with the word lines.

26. The array of claim 22, wherein the shorting transistor and the selection transistor are vertically extending transistors.

27. The array of claim 26 wherein the memory cells individually comprise first and second pillars spaced apart and extending vertically within a row; the shorting transistor and the select transistor of the individual memory cell, each comprising a source / drain region and a vertically extending channel region therebetween, the channel regions of the shorting transistor being spaced apart from each other in a row at one level, and the channel regions of the select transistor being spaced apart from each other in a row at another level vertically spaced apart from the one level; the first pillar including the channel region and the source / drain region of one of the shorting transistors and one of the select transistors of the individual memory cell, the first pillar including the first capacitor electrode of one of the two ferroelectric capacitors of the individual memory cell; and The second column includes the channel region and the source / drain region of the other of the shorting transistors and the other of the selection transistors of the individual memory cell, the second column including the first capacitor electrode of the other of the two ferroelectric capacitors of the individual memory cell.

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