Adjustable programmable pulses of multi-level units

Abstract

This application relates to adjustable programming pulses for multi-level cells. A memory device can modify the characteristics of programming pulses for intermediate logic states based on reliability metrics of associated memory cells. The modified characteristics can increase the read window and reverse the shift of a shifted threshold voltage distribution (e.g., by shifting the threshold voltage distribution further away from one or more other voltage distributions). The reliability metrics can be determined by performing test writes and may be the number of cycles used by the memory cell, the bit error rate, and / or the number of reads of the first state. Information associated with the modified second pulse can be stored in a fuse or memory cell, or can be implemented by the memory device controller or circuitry of the memory device.

Description

[0001] Cross-referencing

[0002] This patent application claims the benefit of U.S. Patent Application No. 17 / 337,195, filed June 2, 2021, entitled “Adjustable Programming Pulls for a Multi-Level Cell,” which is assigned to the assignee and is expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to tunable programmable pulses for multi-level units. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write to or program the states in the memory device.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, chalcogenide memory technology, etc. Memory cells can be volatile or non-volatile. Summary of the Invention

[0006] Describe a method. The method may include: receiving an access command at a memory device comprising a plurality of memory cells, each of the plurality of memory cells being configured to store a state from a set of states, the set of states including a first state, a second state, and a third state, wherein writing a memory cell to the third state includes applying a first pulse of a first polarity and a second pulse of a second polarity. The method may further include modifying a characteristic of the second pulse based on a reliability metric of the third state associated with the set of memory cells in the plurality of memory cells, and performing a write operation on the first memory cell in the plurality of memory cells based on the access command, wherein performing the write operation includes applying the first pulse and the second pulse having the modified characteristic.

[0007] Describe a device. The device may include a plurality of memory cells, each memory cell being writable to a logic state from a set of logic states, the set of logic states including a first logic state, a second logic state, and a third logic state, wherein writing a memory cell to the third logic state includes applying a first voltage pulse of a first polarity and a second voltage pulse of a second polarity. The device may further include: a circuit system for modifying characteristics of the second voltage pulse based on a reliability metric of the third logic state associated with a set of memory cells from the plurality of memory cells; a word line coupled to a first memory cell from the plurality of memory cells; a bit line coupled to the first memory cell; and a driver. The driver is configured to drive the word line and the bit line to apply the first voltage pulse to the first memory cell and to apply the second voltage pulse having modified characteristics to the first memory cell.

[0008] Describe another device. The device may include: a plurality of memory cells, each memory cell being writable to a logic state from a set of logic states, the set of logic states including a first logic state, a second logic state, and a third logic state, wherein writing a memory cell to the third logic state includes applying a first voltage pulse of a first polarity and a second voltage pulse of a second polarity. The device may further include a word line coupled to a first memory cell from the plurality of memory cells, a bit line coupled to the first memory cell, and a controller coupled to the word line and the digital line. The controller may be configured to set characteristics of the second voltage pulse based on a reliability metric of the third logic state associated with the set of memory cells from the plurality of memory cells, apply the first voltage pulse to the first memory cell via the word line and the digital line, and apply the second voltage pulse having the characteristics to the first memory cell via the word line and the digital line. Attached Figure Description

[0009] Figure 1 Examples of systems supporting tunable pulses of multilevel cell (MLC) are shown, according to the examples disclosed herein.

[0010] Figure 2 An example of a memory die with an adjustable programmable pulse supporting MLC is shown, according to the examples disclosed herein.

[0011] Figure 3 An example of a memory cell supporting an adjustable programmable pulse for MLC is shown, according to the examples disclosed herein.

[0012] Figure 4A , 4B Figures 4C and 4C illustrate examples of programmable pulses that support MLC, according to the examples disclosed herein.

[0013] Figure 5A and 5B An example of a voltage diagram of an adjustable programmable pulse supporting MLC is shown, according to the examples disclosed herein.

[0014] Figure 6 A block diagram of a memory controller supporting an adjustable programmable pulse for MLC, according to an example disclosed herein, is shown.

[0015] Figure 7 The flowcharts shown below illustrate one or more methods for supporting tunable programmable pulses for MLC, based on examples disclosed herein. Detailed Implementation

[0016] Memory cells in a memory device (e.g., multilevel cell (MLC)) can be used to store one of three or more states (e.g., logical states). For example, an MLC can be used to store one of three possible states, which may be referred to as storing 1.5 bits per cell. The three or more states of the MLC may include a first state (e.g., a SET state), a second state (e.g., a RESET state), and a number of one or more intermediate states. A write operation to an intermediate state of the MLC may include applying a first pulse of a first polarity to program the cell into one of the first or second states, and applying a second pulse of a second opposite polarity to realize one of the intermediate states. With 1.5 bits (or more) stored per cell, the read window between the corresponding voltage threshold distributions of the possible states can be reduced, such that the cyclic memory cell can cause one or more collapses in the read window (e.g., shifting one voltage threshold distribution associated with the first state toward another voltage threshold distribution associated with the second state), which can lead to read errors.

[0017] This disclosure provides techniques for modifying characteristics (e.g., magnitude, width, or time between the first and second pulses) of a second pulse based on a reliability metric of the memory cell. The modified characteristics may, for example, increase the collapsed read window by reversing the shift of a shifted threshold voltage distribution (e.g., by shifting the threshold voltage distribution further away from one or more other voltage distributions). In some cases, the reliability metric can be determined by performing a test write to an unused cell and identifying the condition of said cell. Alternatively or additionally, the reliability metric may be the number of cycles used by the memory cell, the bit error rate, and / or the number of reads of the first state (e.g., where decoding is used to maintain the consistency of the cells in a given set of cells in the first state). Information associated with the modified second pulse may be stored in a fuse or memory cell, or may be implemented by a memory device controller or circuitry of the memory device.

[0018] The features of this disclosure are firstly in reference to Figure 1-3 The memory systems, dies, and arrays described herein are described in the context of the memory systems, dies, and arrays described herein. Features of this disclosure are described in the references to... Figure 4A-5B The programming pulses and voltage diagrams described herein are presented in the context of the present disclosure. These and other features of this disclosure are further supported by references. Figure 6 and 7 The device diagram and flowchart describing the adjustable programmable pulses involving multi-level units are shown and described with reference to the device diagram and flowchart.

[0019] Figure 1 An example of a system 100 supporting an adjustable programmable pulse for MLC is shown, according to the examples disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 and the memory device 110. System 100 may include one or more memory devices, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0020] System 100 may include electronic device components, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may represent aspects of a computer, laptop computer, tablet computer, smartphone, mobile phone, wearable device, internet-connected device, vehicle controller, etc. Memory device 110 may be a component in the system that can be used to store data from one or more other components of system 100.

[0021] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of other circuitry within a processor or device that uses memory to perform processes (e.g., a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop, tablet, smartphone, mobile phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or some other fixed or portable electronic device, and other examples). In some instances, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0022] Memory device 110 may be a separate device or component that can provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configured to work in conjunction with one or more different types of host devices 105. Signaling between host device 105 and memory device 110 may be used to support one or more of the following: modulation schemes for modulated signals, various pin configurations for transmitting signals, various physical package dimensions for host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0023] Memory device 110 may be used to store data for components of host device 105. In some instances, memory device 110 may act as an auxiliary or subordinate device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of the following: write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0024] The host device 105 may include one or more of the following: an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. The components of the host device 105 may be coupled to each other via bus 135.

[0025] Processor 125 may be used to provide control or other functionality to at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, as well as other instances. In some instances, external memory controller 120 may be implemented by processor 125 or may be part of the processor.

[0026] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0027] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a required or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more tiles, one or more segments), wherein each memory cell can be used to store at least one data bit. Memory device 110 including two or more memory dies 160 may be referred to as a multi-die memory, a multi-die package, a multi-chip memory, or a multi-chip package.

[0028] The device memory controller 155 may include circuitry, logic, or components for controlling the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be used to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of the external memory controller 120, the one or more memory dies 160, or the processor 125. In some instances, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with a local memory controller 165 of the memory die 160.

[0029] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data for host device 105 or a read command instructing memory device 110 to provide data stored in memory die 160 to host device.

[0030] A local memory controller 165 (e.g., local to memory die 160) may include circuitry, logic, or components for controlling the operation of memory die 160. In some instances, the local memory controller 165 may be used to communicate with a device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include a device memory controller 155, and either the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be used to communicate with the device memory controller 155, other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or combinations thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165 or both may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers that may be used to support the described operation of device memory controller 155 or local memory controller 165 or both.

[0031] External memory controller 120 can be used to enable the communication of one or more of the following between system 100 or a component of host device 105 (e.g., processor 125) and memory device 110: information, data, or commands. External memory controller 120 can translate or convert communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120 or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as being external to memory device 110, in some instances, external memory controller 120 or the functionality described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0032] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be used to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may contain one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths that can be used to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be used to act as portions of a channel.

[0033] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be conveyed through channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol of the signal (e.g., signal level) may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, both modulation symbols of the signal (e.g., signal level) may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0034] The memory device can modify the characteristics of the programming pulses for intermediate logic states of memory cells based on reliability metrics associated with the memory cells. The modified characteristics can increase the read window and reverse the shift of the shifted threshold voltage distribution (e.g., by shifting the threshold voltage distribution further away from one or more other voltage distributions). The reliability metrics can be determined by performing a test write and can be the number of cycles used by the memory cell, the bit error rate, and / or the number of reads from the first state. Information associated with the modified second pulse can be stored in a fuse or memory cell, or can be implemented by the memory device controller or circuitry of the memory device.

[0035] Figure 2 An example of a memory die 200 supporting an adjustable programmable pulse for MLC is shown, according to the examples disclosed herein. The memory die 200 may be a reference. Figure 1 Examples of the described memory die 160. In some instances, the memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 200 may include one or more memory cells 205, each of which may be programmed to store different logical states (e.g., a programmed state from a set of two or more possible states). For example, memory cell 205 may be used to store one information bit at a time (e.g., logic 0 or logic 1). In some instances, memory cell 205 (e.g., multi-level memory cell 205) may be used to store more than one information bit at a time (e.g., logic 00, logic 01, logic 10, logic 11). For example, memory cell 205 may be used to store 1.5 information bits at a time (e.g., based on the ability of memory cell 205 to store one of three logical states). In some instances, memory cells 205 may be arranged in an array, such as referenced in [reference]. Figure 1 The memory array 170 is described.

[0036] Memory cell 205 can use configurable materials to store logical states. These configurable materials can be referred to as memory elements, memory storage elements, material elements, material memory elements, material portions, or polarity write material portions, etc. The configurable material of memory cell 205 can refer to chalcogenide-based storage components, such as those mentioned above. Figure 3 For more detailed description, chalcogenide memory elements can be used in phase-change memory (PCM) cells, threshold memory cells, or self-selection memory cells.

[0037] The memory die 200 may include access lines (e.g., row lines 210 and column lines 215) arranged in a pattern such as a grid pattern. The access lines may be formed of one or more conductive materials. In some instances, row lines 210 may be referred to as word lines. In some instances, column lines 215 may be referred to as digital lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, or bit lines, or the like, are interchangeable and do not affect understanding or operation. Memory cell 205 may be located at the intersection of row lines 210 and column lines 215.

[0038] For example, read and write operations can be performed on memory cell 205 by activating or selecting access lines (e.g., one or more of row lines 210 or column lines 215). A single memory cell 205 at its intersection can be accessed by biasing row lines 210 and column lines 215 (e.g., applying a corresponding voltage to row lines 210 or column lines 215 or both). The intersection of row lines 210 and column lines 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of memory cell 205. Access lines can be conductive lines coupled to memory cell 205 and can be used to perform access operations on memory cell 205.

[0039] Access to memory cell 205 can be controlled via row decoder 220 or column decoder 225. For example, row decoder 220 can receive row addresses from local memory controller 245 and activate row line 210 based on the received row addresses. Column decoder 225 can receive column addresses from local memory controller 245 and activate column line 215 based on the received column addresses.

[0040] Sensing component 230 can be used to detect the state of memory cell 205 (e.g., material state, resistance, threshold state) and determine the logic state of memory cell 205 based on the stored state. Sensing component 230 may include one or more sensing amplifiers for amplifying or otherwise converting signals generated by accessing memory cell 205. Sensing component 230 can compare the signal detected from memory cell 205 with reference 235 (e.g., reference voltage). The detected logic state of memory cell 205 can be provided as an output of sensing component 230 (e.g., provided to input / output 240) and can indicate the detected logic state to another component of the memory device including memory die 200.

[0041] The local memory controller 245 can control access to the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 230). The local memory controller 245 can be a reference. Figure 1Examples of the described local memory controller 165. In some instances, one or more of the row decoder 220, column decoder 225, and sensing components 230 may be located in the same position as the local memory controller 245. The local memory controller 245 may be used to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with host device 105, another controller associated with memory die 200), convert the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transfer data from memory die 200 to host device 105 based on the execution of said one or more operations. The local memory controller 245 may generate row signals and column address signals to activate target row lines 210 and target column lines 215. The local memory controller 245 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for various operations discussed when operating the memory die 200.

[0042] The local memory controller 245 can be used to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed or otherwise coordinated by the local memory controller 245 in response to various access commands (e.g., from the host device 105). The local memory controller 245 can be used to perform other access operations not listed herein or other operations related to the operation of the memory die 200 (not directly related to accessing memory cells 205).

[0043] The local memory controller 245 can be used to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logical state (e.g., one of three or more logical states). The local memory controller 245 can identify the target memory cell 205 on which the write operation is performed. The local memory controller 245 can identify target row lines 210 and target column lines 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 245 can activate the target row lines 210 and target column lines 215 (e.g., apply a voltage to the row lines 210 or column lines 215) to access the target memory cell 205. The local memory controller 245 can apply a specific signal (e.g., a write pulse) to the column line 215 during a write operation to store a specific state in the memory element of the memory cell 205. The pulse used as part of the write operation can contain one or more voltage levels for a certain duration.

[0044] The local memory controller 245 can be used to perform read operations (e.g., sensing operations) on one or more memory cells 205 of the memory die 200. During the read operation, the logical state stored in the memory cells 205 of the memory die 200 can be determined. The local memory controller 245 can identify the target memory cell 205 on which the read operation is performed. The local memory controller 245 can identify the target row line 210 and target column line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 245 can activate the target row line 210 and target column line 215 (e.g., apply a voltage to the row line 210 or column line 215) to access the target memory cell 205. The sensing component 230 can detect signals received from the memory cell 205 based on pulses applied to the row line 210, pulses applied to the column line, and / or the resistance or threshold characteristics of the memory cell 205. The sensing component 230 can amplify the signals. The local memory controller 245 can activate the sensing component 230 (e.g., a latching sensing component) and thereby compare the signal received from the memory cell 205 with the reference signal 235. Based on the comparison, the sensing component 230 can determine the logic state stored in the memory cell 205. The pulse used for the read operation may contain one or more voltage levels for a certain duration.

[0045] Figure 3 An example of a memory array 300 according to the embodiments disclosed herein is shown. The memory array 300 may be a reference. Figure 1 and 2An example of a portion of a memory array or memory die described. Memory array 300 may include a first memory cell stack 305 positioned above a substrate (not shown) and a second memory cell stack 310 on top of the first array or stack 305. Although an example of memory array 300 includes two stacks 305, 310, memory array 300 may include any number of stacks (e.g., one or more).

[0046] The memory array 300 may also include row lines 210-a, 210-b, 210-c, 210-d, column lines 215-a and 215-b, which may be references. Figure 2 Examples of row lines 210 and column lines 215 are described. One or more memory cells in the first stack group 305 and the second stack group 310 may contain one or more chalcogenide materials in the posts between the access lines. For example, a single stack between access lines may contain one or more of a first electrode, a first chalcogenide material (e.g., a selector assembly), a second electrode, a second chalcogenide material (e.g., a memory element), or a third electrode. Although contained in Figure 3 Some elements are marked with numerical indicators, while other corresponding elements are not marked, but they are the same or should be understood as similar, in order to improve the visibility and clarity of the depicted features.

[0047] One or more memory cells in the first stack 305 may include one or more of electrodes 325-a, memory elements 320-a, or electrodes 325-b. One or more memory cells in the second stack 310 may include one or more of electrodes 325-c, memory elements 320-b, or electrodes 325-d. The memory element 320 may be an example of a chalcogenide material, such as a phase-change memory element, a threshold memory element, or a self-selecting memory element. In some instances, the memory cells of the first stack 305 and the second stack 310 may have a common conductive line, such that corresponding memory cells in one or more stacks 305 and one or more stacks 310 may share column line 215 or row line 210. For example, the first electrode 325-c of the second stack 310 and the second electrode 325-b of the first stack 305 may be coupled to column line 215-a, such that column line 215-a can be shared by vertically adjacent memory cells.

[0048] In some instances, the architecture of memory array 300 may be referred to as a cross-point architecture, where memory cells are formed at topological intersections between row lines 210 and column lines 215. Compared to other memory architectures, such cross-point architectures offer relatively high-density data storage and lower manufacturing costs. For example, compared to other architectures, cross-point architectures may have memory cells with a smaller area and therefore a higher memory cell density. For example, compared to other architectures with a memory cell area of ​​6F², such as those with three-terminal selector elements, the architecture may have a memory cell area of ​​4F², where F is the minimum feature size. For example, DRAM may use transistors as three-terminal devices as selector elements for each memory cell and may have a larger memory cell area compared to cross-point architectures.

[0049] although Figure 3 The examples illustrate two memory stacks, but other configurations are possible. In some instances, a single memory stack of memory cells can be constructed above the substrate, which can be referred to as a two-dimensional memory. In some instances, two or more memory cell stacks can be configured in a similar manner as a three-dimensional cross-point architecture. Furthermore, in some cases, Figure 3 As shown or referenced Figure 3 The described elements may be electrically coupled to each other as shown or described, but may be physically rearranged (e.g., storage element 320 and possible selection elements or electrodes 325 may be electrically connected in series between row line 210 and column line 215, but do not need to be in a post or stack configuration).

[0050] In some instances, the material of the storage element 320 may comprise a chalcogenide material or other alloys comprising selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some instances, chalcogenide materials primarily comprising selenium (Se), arsenic (As), and germanium (Ge) may be referred to as SAG alloys. In some instances, SAG alloys may also comprise silicon (Si), and such chalcogenide materials may be referred to as SiSAG alloys. In some instances, SAG alloys may comprise silicon (Si) or indium (In), or combinations thereof, and such chalcogenide materials may be referred to as SiSAG alloys or InSAG alloys, or combinations thereof. In some instances, the chalcogenide glass may contain additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form.

[0051] In some instances, storage element 320 may be an example of a phase-change memory cell. In such instances, the material used for storage element 320 may be based on an alloy (e.g., the alloys listed above) and may be used to undergo a phase transition or change to a different physical state during normal operation of the memory cell. For example, a phase-change memory cell may have an amorphous state (e.g., a relatively disordered atomic configuration) and a crystalline state (e.g., a relatively ordered atomic configuration).

[0052] Phase change memory cells can exhibit an observable difference in resistance between the crystalline and amorphous states of phase change materials, which can be chalcogenide materials. Crystalline materials allow atoms to be arranged in a periodic structure, resulting in relatively low resistance. In contrast, amorphous materials may have little or no periodic atomic structure, leading to relatively high resistance.

[0053] The difference in resistance between the amorphous and crystalline states of a material can be significant. For example, the resistance of an amorphous material can be one or more orders of magnitude greater than that of a crystalline material. In some instances, the material can be partially amorphous and partially crystalline (e.g., in an intermediate state), and the resistance can have a value between that of a fully crystalline or fully amorphous material. In such instances, the material can be used to store more than two logic states (e.g., three or more logic states).

[0054] During programming (writing) operations of a phase-change memory cell (e.g., electrode 325-a, memory element 320-a, electrode 325-b), various parameters of the programming pulse can affect (e.g., determine, set, program) specific properties or characteristics of the material of the memory element 320, such as the threshold voltage or resistance of the material. To program a low-resistance state (e.g., a relatively crystalline state) in the phase-change memory cell, a programming pulse that heats or melts the material of the memory element 320 can be applied, which may be associated with at least temporarily forming a relatively disordered (e.g., amorphous) atomic arrangement. The amplitude of the programming pulse can be reduced (e.g., reduced relatively slowly) over a duration to allow the material to form a crystalline structure as it cools, thereby forming a stable crystalline material state.

[0055] To program a high-resistance state (e.g., a relatively amorphous state) in a phase-change memory cell, a programming pulse that heats and / or melts the material of memory element 320 can be applied. The amplitude of the programming pulse can decrease faster than that of a programming pulse for a low-resistance state. In such cases, the material can be cooled, where the atoms are arranged in a more disordered atomic configuration because the atoms cannot form a crystalline structure before the material reaches a stable state, thus forming a stable amorphous material state. The threshold voltage or resistance difference of the material of memory element 320, depending on the logic state stored by the material of memory element 320, can correspond to the read window of memory element 320. In some cases, a portion of the memory element may undergo a material change associated with the logic state.

[0056] In some instances, such as for threshold memory cells or selectable memory cells, some or all of the set of logic states supported by the memory cell may be associated with an amorphous state of a chalcogenide material (e.g., a single-state material may be used to store different logic states). In some instances, memory element 320 may be an example of a selectable memory cell. In such instances, the material used for memory element 320 may be based on an alloy (e.g., alloys listed above) and may be operable to change to different physical states during normal operation of the memory cell. For example, a selectable memory cell may have a high threshold voltage state and a low threshold voltage state. In some cases, a selectable memory cell may additionally have an intermediate threshold voltage state (e.g., between and as a complement to the high and low threshold voltage states). The high threshold voltage state may correspond to a first logic state (e.g., a RESET state), and the low threshold voltage state may correspond to a second logic state (e.g., a SET state). The intermediate threshold voltage state may correspond to a third logic state (e.g., a SET-RESET state or an intermediate state).

[0057] During a programming (writing) operation of a self-selected memory cell (e.g., including electrode 325-a, memory element 320-a, and electrode 325-b), the polarity of the write operation can affect (determine, set, program) a specific property or characteristic of the material of memory element 320, such as the threshold voltage of the material. For example, a first write operation may write a first logic state (e.g., a SET state) to the self-selected memory cell by applying a first pulse of a first polarity to the memory cell. Similarly, a second (e.g., a different) write operation may write a second logic state (e.g., a RESET state) to the self-selected memory cell by applying a second pulse of a second polarity to the memory cell. A third write operation may write a third logic state (e.g., an intermediate state) to the self-selected memory cell by applying a first pulse followed by a second pulse (e.g., after a time interval). In some cases, if the self-selected memory cell can be used to store more than three states, then other write operations may be used to write one of the other states to the memory cell by applying one or more pulses, each pulse having a corresponding polarity.

[0058] A memory cell that can be used to store three or more states, as described herein, may be referred to as an MLC. An MLC that can be used to store three states (e.g., storing one of a set of three logical states at a time) may be represented, for example, a memory cell that stores 1.5 bits based on the ability to store one of the three logical states.

[0059] The threshold voltage difference of the material of storage element 320, depending on the logic state stored by the material of storage element 320 (e.g., the difference between the threshold voltage when the material stores logic state '0' and when it stores logic state '1'), can correspond to a read window of storage element 320. In some cases (e.g., for MLC), a memory cell can be associated with three or more threshold voltages (e.g., for reading the logic state stored by the cell), wherein each threshold voltage can be associated with a corresponding read window used to determine the associated logic state.

[0060] In some cases, the memory array 300 of the memory device may include MLCs, wherein the threshold voltages of the MLCs of the memory array 300 may be grouped into different distributions. For example, a first subset of memory cells may each be programmed with a first state (e.g., a SET state) associated with a first threshold voltage distribution across the first subset of memory cells. Similarly, a second subset of memory cells may be programmed with a second state (e.g., a RESET state) associated with a second threshold voltage distribution, and a third subset of memory cells may be programmed with a third state (e.g., an intermediate state) associated with a third threshold voltage distribution. Each distribution may contain corresponding threshold voltage values ​​that are relatively close to each other (e.g., representing the same logical state associated with the distribution).

[0061] Based on one or more conditions of the MLCs in memory array 300, some threshold voltage distributions may begin to drift or change. For example, a subset of memory cells may begin to experience a change in its threshold voltage distribution (e.g., an increase or decrease) (e.g., each memory cell in the subset may experience a corresponding change in its memory cell threshold voltage). In these cases, the threshold voltage distribution associated with a subset of memory cells (e.g., as a whole, based on individual changes in memory cells) may drift to a different threshold voltage distribution closer to another subset of memory cells. In these cases, the read window for the logic state associated with the two subsets of memory cells (e.g., between the two) may begin to collapse or shrink. In some cases, a collapsed window may result in an increase in the number of errors read from the logic state of one or both subsets of memory cells (e.g., based on a smaller window or margin between the corresponding threshold voltage distributions).

[0062] For example, as the number of usage cycles of the MLC increases, the third threshold voltage distribution (e.g., associated with the third intermediate state) may begin to drift closer to the first threshold voltage distribution (e.g., associated with the first SET state). As the usage of the memory device (e.g., the number of cycles) increases, the read window for the first and third logic states (e.g., in between) may begin to collapse or shrink, potentially leading to an increase in the number of read errors for the first and / or third logic states. The threshold voltage distribution and its associated drift are referenced herein. Figure 5A and 5B Further description.

[0063] Figure 4A , 4B Figures 4C and 4C illustrate examples of programming pulses 401, 402, and 403 supporting adjustable programming pulses according to the examples disclosed herein. Programming pulses 401, 402, and 403 may each represent corresponding examples of pulses (e.g., or a set of pulses) used to program or write logic states to memory cells (e.g., MLCs), as referenced herein. Figure 3 As described herein, each pulse (e.g., or a set of pulses) can program a corresponding logic state into a memory cell. Although the examples herein describe programming one of three logic states into a memory cell, it should be understood that such examples are also applicable to programming one of four or more logic states into a memory cell without departing from the scope of this disclosure. For example, similar pulses or different but similar combinations of pulses can be used to program a fourth or other logic state into a memory cell.

[0064] As referenced in this article Figure 3As described, a memory device (e.g., a controller of the memory device) can apply different pulses (e.g., voltage pulses) to memory cells (e.g., MLCs) to program corresponding logic states into the memory cells. In the context of... Figure 4A In the illustrated example, the first programming pulse 401 can be used to program or write a first logic state to a memory cell. In some instances, applying the first programming pulse 401 may involve driving the bit line associated with the memory cell to a first voltage (e.g., as represented by bit line voltage 405-a) and simultaneously driving the word line associated with the memory cell to a second voltage lower than the first voltage (e.g., as represented by word line voltage 410-a). Applying the first programming pulse 401 to the memory cell can program or write the memory cell to a first logic state (e.g., a SET state).

[0065] In the Figure 4B In the illustrated example, the second programming pulse 402 can be used to program or write a second logic state to a memory cell. In some instances, applying the second programming pulse 402 may involve driving the bit line associated with the memory cell to a third voltage (e.g., as represented by bit line voltage 405-b) and simultaneously driving the word line associated with the memory cell to a fourth voltage higher than the third voltage (e.g., as represented by word line voltage 410-b). Applying the second programming pulse 402 to the memory cell can program or write the memory cell to a second logic state (e.g., a RESET state).

[0066] In the Figure 4C In the illustrated example, a third programming pulse 403 (e.g., a set of programming pulses) can be used to program or write a third logic state to a memory cell. In some instances, applying the third programming pulse 403 may comprise applying a first programming pulse or a programming pulse with the same polarity as the first programming pulse (e.g., a first pulse), followed by applying a second programming pulse or a programming pulse with the same polarity as the second programming pulse (e.g., a second pulse). For example, bit line voltage 405-c may be variable high and word line voltage 410-c may be variable low to apply the first pulse, and bit line voltage 405-c may be variable low while word line voltage 410-c may be variable high to apply the second pulse. Applying the third programming pulse 403 to a memory cell can program or write the memory cell to a third logic state (e.g., an intermediate state).

[0067] The second pulse of the third programming pulse 403 may be associated with one or more features. For example, the second pulse may have a pulse width 415, which may represent the duration for which the second pulse is applied to the memory cell. The second pulse may also have a pulse amplitude 425, which may represent the voltage difference between the word line and the bit line when the second pulse is applied. The second pulse may also be associated with a time period 420 between the first pulse and the second pulse. During the time period 420, the memory device may apply the same or similar voltage to the word line and the digital line such that the voltage difference between the word line and the digital line is less than the voltage used to program the memory cell.

[0068] As referenced in this article Figure 3 As described, each memory cell may be associated with a threshold voltage for reading the corresponding memory cell (e.g., where the threshold voltage may be based on an associated logic state programmed or written to the memory cell). The threshold voltages of memory cells associated with the same logic state may form a corresponding threshold voltage distribution for said logic state (e.g., a first, second, or third threshold voltage distribution). For example, refer to... Figure 5A and 5B The first threshold voltage distribution (e.g., associated with the first SET state) can be represented by distribution 505-a or distribution 505-b, the second threshold voltage distribution (e.g., associated with the second RESET state) can be represented by distribution 515-a or distribution 515-b, and the third threshold voltage distribution (e.g., associated with the third intermediate state) can be represented by distribution 510.

[0069] In some cases, such as when the number of programming cycles for a memory cell increases (e.g., based on one or more physical or other conditions of the memory cell), distribution 510-a may begin to drift toward distribution 505-a. For example, distribution 510-a may drift such that it can be represented as distribution 510-b, which may contain a threshold voltage closer to the threshold voltage value contained in distribution 505-a (e.g., closer than distribution 510-a, with a correspondingly lower threshold voltage value than distribution 510-a). In some cases, drift of distribution 510-a (e.g., toward distribution 510-b or another distribution) can lead to a higher number of errors when reading memory cells and other problems.

[0070] For example, reading a first state (e.g., associated with a cell represented by distribution 505-a) may involve determining whether a memory cell can be read using a first voltage 520. All memory cells that can be read using the first voltage 520 (e.g., memory cells with a threshold voltage less than or equal to the first voltage 520) may be associated with the first state. Thus, memory cells with a threshold voltage associated with distribution 505-a may be determined by the memory device to store the first logic state (e.g., because these cells may have a threshold voltage less than or equal to the first voltage 520). However, in some cases, distribution 510-a may drift toward distribution 505-a, such that distribution 510-a may contain some memory cells with a threshold voltage less than the first voltage 520. Therefore, some memory cells in distribution 510-b (e.g., storing a third state) may be determined by the memory device to store the first state, which may lead to read errors for such cells.

[0071] This disclosure provides techniques for reducing or reversing drift in distribution 510-b (e.g., caused by cycle counting). For example, a memory device (e.g., a circuit system or a component thereof) may determine a reliability metric for a third state (e.g., for all MLCs or for the MLC storing the third state). If the reliability metric meets a certain condition or threshold, the memory device may adjust (e.g., the characteristics of the second pulse of the third programming pulse 403) to program the third state. Adjusting the characteristics of the second pulse may reverse the drift in distribution 510-b and reduce the number of errors associated with the third state. For example, as... Figure 5B The third threshold voltage distribution can be represented as distribution 510-c, which can represent a distribution that has shifted toward distribution 505-b (e.g., the first distribution). Adjusting the characteristics of the second pulse can move distribution 510-c back to the right (e.g., experiencing an increase in the corresponding threshold voltage level), such that distribution 510-c can move to one of distributions 510-d, 510-e, or 510-f.

[0072] Adjusting the characteristics of the second pulse may include adjusting the pulse width 415, time period 420, or pulse amplitude 425 associated with the second pulse of the third programming pulse 403. For example, the memory device may reduce the pulse width 415 of the second pulse, which may shift distribution 510-c to one of distributions 510-d, 510-e, or 510-f. Alternatively, the memory device may adjust the time period 420 between the first and second pulses, or adjust (e.g., reduce) the pulse amplitude 425 of the second pulse, which may shift distribution 510-c to one of distributions 510-d, 510-e, or 510-f. The adjustment of the second pulse may be performed at the level of memory cell die, memory cell page, memory cell library, or memory cell codeword (e.g., a group of memory cells configured, for example, to be accessed simultaneously by the same access line).

[0073] When adjustment is performed at the codeword level, the memory device can adjust the characteristics of the second pulse by programming one or more on-die fuses associated with the codeword, or by programming one or more non-volatile memory cells associated with the codeword. When adjustment is performed at a higher level of the memory device (e.g., a group or die), the memory device can adjust the second pulse using a memory controller or other circuitry associated with a higher level of the memory device (e.g., which may also use one or more on-die fuses or one or more non-volatile memory cells).

[0074] In some cases, the reliability metric used to determine the characteristics of adjusting the second pulse may be a bit error rate associated with the third state (e.g., determined when reading the cell using the first voltage 520), which may represent, for example, the number or percentage of memory cells storing the third state but causing a read operation to read the first state (e.g., or another state). In these cases, if the bit error rate is higher than a threshold error rate, the memory device may determine the characteristics of adjusting the second pulse. For example, the memory device may periodically run a program that triggers a readback pulse to determine the bit error rate and whether the bit error rate is higher than expected (e.g., higher than a threshold calibrated at the initial time).

[0075] In some cases, the reliability metric can be the number of memory cells storing a first state (e.g., the MLC of a memory device) (e.g., determined when using a first voltage 520 and other voltage read cells associated with other states), where a non-uniform distribution among the first, second, and third logic states within the memory cells can indicate a drift in distribution 510 (e.g., distribution 510-a). For example, the memory device can use decoding to maintain the number of cells in the first state within a given set of cells, and a change in said number can indicate a voltage threshold shift for the third state. In these cases, if the number of memory cells storing the first state meets a threshold number (e.g., a threshold percentage), then the memory device can determine to adjust the characteristics of the second pulse. For example, the memory device can monitor the number of SET state reads (e.g., reading the value of the first logic state) detected during operation (e.g., on the memory die). If the number of SET state reads exceeds the threshold number, this can indicate a loss of read margin due to cycling, and the memory device can adjust the characteristics of the second pulse. When using bit error rate or the number of memory cells storing the first state as a reliability metric, the memory device can implement adjustment of the second pulse at a higher level (e.g., a group of cells or a die), for example, using a memory controller or other circuitry.

[0076] In some cases, the reliability metric used to determine the characteristics of adjusting the second pulse can be the number of cycles (e.g., write and / or read cycles) associated with a group of memory cells (e.g., memory cell pages, codewords, groups, or dies). If the number of cycles exceeds a threshold number, the memory device can determine the characteristics of adjusting the second pulse. When using the number of cycles as a reliability metric, the memory device can implement the adjustment of the second pulse at the codeword level or higher.

[0077] In some cases, a reliability metric can be the condition of one or more test memory cells after performing a corresponding test write operation. For example, a memory device may perform multiple test write operations on the one or more test memory cells, where each test write operation may be associated with a different corresponding characteristic (e.g., or a set of characteristics) of a second pulse (e.g., each test write operation may use a set of characteristics selected from a series of the second pulse). The memory device may determine one or more desired conditions (e.g., bit error rate, read accuracy) for the test memory cells and identify whether the conditions of the memory cells meet the desired conditions for each test write operation. The memory device may select a test write operation from one of the test write operations that meets the desired conditions or is within the desired condition threshold (e.g., and a set of associated characteristics of the second pulse), and may adjust the characteristics of the second pulse to match the set of characteristics of the selected test operation. When test operations and associated memory cell conditions are used as a reliability metric, the memory device may implement adjustments to the second pulse at a higher level (e.g., a group of cells or a die), for example, using a memory controller or other circuitry.

[0078] Figure 5A and 5B Examples of voltage diagrams 501 and 502 for an adjustable programmable pulse supporting MLC are shown according to the examples disclosed herein. Figure 5A The diagram illustrates example voltage threshold distributions for memory cells programmed into the first, second, and third logic states, respectively. (See reference...) Figures 4A-4C As described, a unit programmed with a first logical state may correspond to distribution 505-a, a unit programmed with a second logical state may correspond to distribution 515-a, and a unit programmed with a third logical state may correspond to distribution 510-a, which may drift to or become distribution 510-b.

[0079] Figure 5B Example voltage threshold distributions for memory cells programmed to a first logic state, a second logic state, and a third logic state are also shown. See further reference. Figures 4A-4C As described, a cell programmed with a third logic state may correspond to distribution 510-c (e.g., after a drift). A cell programmed with a first logic state may correspond to distribution 505-b, and a cell programmed with a second logic state may correspond to distribution 515-b. As a result of the characteristics of the second pulse of the programming pulse that adjusts the third logic state, distribution 510-c may be modified to one of distributions 510-d, 510-e, or 510-f (e.g., and other instances). For example, distributions 510-d, 510-e, or 510-f may be generated by reducing the width of the second pulse, wherein distribution 510-f may represent the result of a maximum reduction in the width of the second pulse, and distribution 510-d may represent the result of a minimum reduction in the width of the second pulse.

[0080] Based on the characteristics of the adjusted second pulse, as described herein, distribution 510-c can be moved further away from distribution 505-b, which can increase the read window associated with the first logic state, the third logic state, or both (e.g., increase margin). Increasing the read window can reduce read errors and improve device performance, among other advantages.

[0081] Figure 6 A block diagram 600 illustrates a memory controller 620 supporting an adjustable programmable pulse for MLC, according to an example disclosed herein. The memory controller 620 may be a reference... Figure 1 Examples of the aspects of the memory controller described in section 5. The memory controller 620 or its various components may be examples of components for performing various aspects of the adjustable programming pulses of the MLC as described herein. For example, the memory controller 620 may include an access component 625, a pulse modification component 630, a write operation component 635, a measurement identification component 640, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0082] Access component 625 may be configured or otherwise support means for receiving access commands at a memory device comprising a set of multiple memory cells, each of the multiple memory cells being configured to store one of a set of states, the set of states including a first state, a second state, and a third state, wherein writing a memory cell to the third state includes applying a first pulse of a first polarity and a second pulse of a second polarity. Pulse modification component 630 may be configured or otherwise support means for modifying the characteristics of the second pulse based on a reliability metric of the third state associated with the set of memory cells in the multiple memory cells. Write operation component 635 may be configured or otherwise support means for performing a write operation on a first memory cell in the multiple memory cells based on an access command, wherein performing the write operation includes applying a first pulse and a second pulse having modified characteristics.

[0083] In some instances, the pulse modification component 630 may be configured or otherwise support means for performing a set of multiple test write operations on a test memory cell of the set of multiple memory cells, each of the multiple test write operations being associated with a corresponding feature of a second pulse. In some instances, the pulse modification component 630 may be configured or otherwise support means for identifying a corresponding condition of the test memory cell based on the execution of the set of multiple test write operations for each of the multiple test write operations. In some instances, the pulse modification component 630 may be configured or otherwise support means for determining modified features of a second pulse based on a corresponding condition of the test memory cell for the set of multiple test write operations and a corresponding feature of the second pulse, wherein the modified features are determined based on the determined modified features.

[0084] In some instances, the metric identification component 640 may be configured or otherwise supported to support means for identifying the number of memory cells storing a first state within at least a subset of the set of memory cells, the number of memory cells including a reliability metric. In some instances, the metric identification component 640 may be configured or otherwise supported to support means for determining that the number of memory cells meets a threshold, wherein the characteristics of the modified second pulse are based on the determination.

[0085] In some instances, the metric identification component 640 may be configured or otherwise support means for identifying a bit error rate of at least a subset of the set of memory cells, the bit error rate comprising a reliability metric and associated with read operations on the set of memory cells. In some instances, the metric identification component 640 may be configured or otherwise support means for determining whether the bit error rate meets a threshold, wherein the characteristics of the modified second pulse are based on the determination.

[0086] In some instances, the metric identification component 640 may be configured or otherwise supported to support means for identifying the number of write cycles associated with the set of memory cells, the number of write cycles including a reliability metric. In some instances, the metric identification component 640 may be configured or otherwise supported to support means for determining whether the number of write cycles meets a threshold, wherein the characteristics of the modified second pulse are based on the determination.

[0087] In some instances, to support modified features, the pulse modification component 630 may be configured or otherwise support means for programming one or more fuses of the memory device to the modified features configured with the second pulse. In some instances, to support modified features, the pulse modification component 630 may be configured or otherwise support means for programming one or more non-volatile memory cells of the memory device to the modified features configured with the second pulse.

[0088] In some instances, the set of memory cells comprises a group of memory cells configured for simultaneous access. In some instances, the set of memory cells comprises memory cell pages, groups, or dies. In some instances, the characteristics of the second pulse include the time between the first and second pulses, the magnitude of the second pulse, the width of the second pulse, or any combination thereof. In some instances, to support modification features, the pulse modification component 630 may be configured or otherwise support means for reducing the width of the second pulse used to write the third state.

[0089] In some instances, to support the application of a first pulse of a first polarity, the write operation component 635 may be configured or otherwise support means for driving bit lines associated with memory cells to a first voltage. In some instances, to support the application of a first pulse of a first polarity, the write operation component 635 may be configured or otherwise support means for driving word lines associated with memory cells to a second voltage, which is lower than the first voltage.

[0090] In some instances, to support a second pulse applying a second polarity, the write operation component 635 may be configured or otherwise support means for driving bit lines to a third voltage. In some instances, to support a second pulse applying a second polarity, the write operation component 635 may be configured or otherwise support means for driving word lines to a fourth voltage, the third voltage being lower than the fourth voltage.

[0091] Figure 7 A flowchart illustrating a method 700 supporting an adjustable programmable pulse for MLC, according to an example disclosed herein, is shown. Operation of method 700 may be implemented by a memory controller or its components described herein. For example, operation of method 700 may be provided by reference to... Figures 1 to 6 The memory controller described is executed. In some instances, the memory controller may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory controller may use dedicated hardware to perform aspects of the described functions.

[0092] At 705, the method may include: receiving an access command at a memory device comprising a plurality of memory cells, each of the plurality of memory cells being configured to store a state from a set of states, the set of states including a first state, a second state, and a third state, wherein writing a memory cell to the third state includes applying a first pulse of a first polarity and a second pulse of a second polarity. Operation 705 may be performed according to the examples disclosed herein. In some examples, aspects of operation 705 may be derived from references... Figure 6 The described access component 625 is executed.

[0093] At 710, the method may include modifying the characteristics of the second pulse based on a reliability metric of a third state associated with a set of memory cells in one of the plurality of memory cells. Operation 710 may be performed according to the examples disclosed herein. In some instances, aspects of operation 710 may be derived from references... Figure 6 The described pulse modification component 630 is executed.

[0094] At 715, the method may include: performing a write operation on a first memory cell of the set of plurality of memory cells based on an access command, wherein performing the write operation includes applying a first pulse and a second pulse having modified characteristics. Operation 715 may be performed according to the examples disclosed herein. In some examples, aspects of operation 715 may be derived from references... Figure 6 The described write operation is performed by component 635.

[0095] In some instances, the device described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving an access command at a memory device comprising a plurality of memory cells, each of the plurality of memory cells configured to store a state from a set of states, the set of states including a first state, a second state, and a third state, wherein writing a memory cell to the third state includes applying a first pulse of a first polarity and a second pulse of a second polarity; modifying the characteristics of the second pulse based on a reliability metric of the third state associated with the set of memory cells in the plurality of memory cells; and performing a write operation on the first memory cell from the plurality of memory cells based on the access command, wherein performing the write operation includes applying the first pulse and the second pulse having the modified characteristics.

[0096] Some examples of the methods 700 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for: performing a set of multiple test write operations on a test memory cell of the set of multiple memory cells, each of the multiple test write operations being associated with a corresponding feature of a second pulse; identifying a corresponding condition of the test memory cell based on the execution of the set of multiple test write operations for each of the multiple test write operations; and determining a modified feature of the second pulse based on the corresponding condition of the test memory cell for the set of multiple test write operations and the corresponding feature of the second pulse, wherein the modified feature may be determined based on the modified feature.

[0097] Some examples of the method 700 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for: identifying the number of memory cells storing a first state within at least a subset of the set of memory cells, the number of memory cells including a reliability metric; and determining that the number of memory cells satisfies a threshold, wherein the feature of modifying the second pulse may be based on the determination.

[0098] Some examples of the methods 700 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for: identifying a bit error rate of at least a subset of the set of memory cells, the bit error rate including a reliability metric and associated with read operations of the set of memory cells; and determining that the bit error rate meets a threshold, wherein a feature of modifying the second pulse may be based on the determination.

[0099] Some examples of the methods 700 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for: identifying a number of write cycles associated with the set of memory cells, the number of write cycles including a reliability metric; and determining that the number of write cycles meets a threshold, wherein a feature of modifying the second pulse may be based on the determination.

[0100] In some instances of the method 700 and device described herein, the modified feature may include operations, features, circuitry, logic, components, or instructions for programming one or more fuses of the memory device to configure a second pulse.

[0101] In some instances of the method 700 and device described herein, the modified feature may include operations, features, circuitry, logic, components, or instructions for programming one or more non-volatile memory cells of the memory device to configure the modified feature for the second pulse.

[0102] In some instances of the methods 700 and devices described herein, the set of memory cells comprises a group of memory cells configured for simultaneous access. In some instances of the methods 700 and devices described herein, the set of memory cells comprises memory cell pages, groups, or dies. In some instances of the methods 700 and devices described herein, the characteristics of the second pulse include the time between the first and second pulses, the magnitude of the second pulse, the width of the second pulse, or any combination thereof.

[0103] In some instances of the method 700 and device described herein, the modification feature may include operations, features, circuitry, logic, components, or instructions for reducing the width of the second pulse used to write the third state.

[0104] In some instances of the method 700 and device described herein, the first pulse applying the first polarity may include operations, features, circuitry, logic, components, or instructions for driving bit lines associated with memory cells to a first voltage and word lines associated with memory cells to a second voltage, the second voltage being lower than the first voltage.

[0105] In some instances of the method 700 and device described herein, the second pulse applying the second polarity may include operations, features, circuitry, logic, components, or instructions for driving bit lines to a third voltage and word lines to a fourth voltage, the third voltage being lower than the fourth voltage.

[0106] It should be noted that the methods described herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0107] Describe another device. The device may include: a plurality of memory cells, each memory cell being writable to a logic state from a set of logic states, the set of logic states including a first logic state, a second logic state, and a third logic state, wherein writing a memory cell to the third logic state includes applying a first voltage pulse of a first polarity and a second voltage pulse of a second polarity; circuitry for modifying characteristics of the second voltage pulse based on a reliability metric of the third logic state associated with a set of memory cells from the plurality of memory cells; a word line coupled to a first memory cell from the plurality of memory cells; a bit line coupled to the first memory cell; and a driver, wherein the driver is configured to drive the word line and the bit line to apply the first voltage pulse to the first memory cell and to apply the second voltage pulse having modified characteristics to the first memory cell.

[0108] In some instances, the device may include one or more fuses that can be programmed to modify the characteristics of the second voltage pulse. In some instances, the device may include one or more non-volatile memory cells that can be programmed to modify the characteristics of the second voltage pulse.

[0109] In some instances, the device may include: performing a set of multiple test write operations on a test memory cell of the set of multiple memory cells, each of the multiple test write operations being associated with a corresponding feature of a second voltage pulse; identifying a corresponding condition of the test memory cell based on the execution of the set of multiple test write operations for each of the multiple test write operations; and determining a modified feature of the second voltage pulse based on the corresponding condition of the test memory cell for the set of multiple test write operations and the corresponding feature of the second voltage pulse, wherein the modified feature may be determined based on the modified feature.

[0110] In some instances, the device may include: identifying the number of memory cells storing a first logic state within at least a subset of the set of memory cells, the number of memory cells including a reliability metric; and determining that the number of memory cells satisfies a threshold, wherein the characteristics of modifying the second voltage pulse may be based on the determination.

[0111] In some instances, the device may include: identifying a bit error rate of at least a subset of the set of memory cells, the bit error rate including a reliability metric and associated with read operations of the set of memory cells; and determining that the bit error rate meets a threshold, wherein the characteristics of the modified second voltage pulse may be based on the determination.

[0112] In some instances, the device may include: identifying a number of write cycles associated with the set of memory cells, the number of write cycles including a reliability metric; and determining that the number of write cycles meets a threshold, wherein the characteristics of the modified second voltage pulse may be based on the determination.

[0113] In some instances of the device, the set of memory cells includes memory cell pages, memory cell groups, memory cell dies, or groups of memory cells configured for simultaneous access. In some instances of the device, the second voltage pulse is characterized by the time between the first and second voltage pulses, the magnitude of the second voltage pulse, the width of the second voltage pulse, or any combination thereof.

[0114] Describe another device. The device may include: a plurality of memory cells, each memory cell being writable to a logic state from a set of logic states, the set of logic states including a first logic state, a second logic state, and a third logic state, wherein writing a memory cell to the third logic state includes applying a first voltage pulse of a first polarity and a second voltage pulse of a second polarity; a word line coupled to the first memory cell from the plurality of memory cells; a bit line coupled to the first memory cell; and a controller coupled to the word line and a digital line, the controller being writable to set characteristics of the second voltage pulse based on a reliability metric of the third logic state associated with the set of memory cells from the plurality of memory cells, applying the first voltage pulse to the first memory cell via the word line and the digital line, and applying the second voltage pulse having the characteristics to the first memory cell via the word line and the digital line.

[0115] In some instances, the device may include: performing a set of multiple test write operations on a test memory cell of the set of multiple memory cells, each of the multiple test write operations being associated with a corresponding feature of a second voltage pulse; identifying a corresponding condition of the test memory cell based on the execution of the set of multiple test write operations for each of the multiple test write operations; and determining a modified feature of the second voltage pulse based on the corresponding condition of the test memory cell for the set of multiple test write operations and the corresponding feature of the second voltage pulse, wherein setting the feature may be based on determining the feature.

[0116] In some instances, the device may include: identifying the number of memory cells storing a first logic state within at least a subset of the set of memory cells; identifying a bit error rate of at least the subset of the set of memory cells, the bit error rate being associated with a read operation of each memory cell in the set of memory cells; identifying the number of write cycles associated with at least the subset of the set of memory cells; and determining that the number of memory cells satisfies a first threshold, the bit error rate satisfies a second threshold, or the number of write cycles satisfies a third threshold, or any combination thereof, wherein the characteristics of the modified second voltage pulse may be based on the determination.

[0117] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0118] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that supports the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0119] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When, for example, one component of a controller couples other components together, that component triggers a change that allows signals to flow through conductive paths between those other components, paths that were previously not permitted to allow signal flow.

[0120] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, they are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0121] As used herein, the term "layer" or "level" refers to a layer or sheet of geometry (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure with two dimensions greater than the third, such as a thin film. Layers or levels may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sublevels.

[0122] As used herein, the term "substantially" means that a modified feature (e.g., a verb or adjective modified by the term "substantially") need not be absolute but must be close enough to obtain the feature's advantage. Similarly, as used herein, the term "substantial" means that a modified feature (e.g., a noun modified by the term "substantial") need not be absolute but must be close enough to obtain the feature's advantage.

[0123] As used herein, the term "electrode" can refer to an electrical conductor and, in some instances, can be used as an electrical contact to a memory cell or other component of a memory array. Electrodes can include traces, wires, conductive lines, conductive layers, etc., that provide conductive paths between elements or components of the memory array.

[0124] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0125] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0126] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0127] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a long dash following the reference numeral and a second numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0128] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that different parts of the functions are implemented in different physical locations.

[0129] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0130] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items ending with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0131] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, and without limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these terms are also included within the scope of computer-readable media.

[0132] The description provided herein enables those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, the invention is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: Receive an access command at a memory device comprising a plurality of memory cells, each of the plurality of memory cells being configured to store one of a set of states, the set of states including a first state, a second state, and a third state, wherein writing a memory cell to the third state includes applying a first pulse of a first polarity and a second pulse of a second polarity. The characteristics of the second pulse are modified at least in part based on a reliability metric of the third state associated with a set of memory cells among the plurality of memory cells; as well as A write operation is performed on a first memory cell among the plurality of memory cells, at least in part based on the access command, wherein performing the write operation includes applying the first pulse and a second pulse having the modified characteristics.

2. The method according to claim 1, further comprising: Perform multiple test write operations on one of the plurality of memory cells in a test memory cell, each of the plurality of test write operations being associated with a corresponding feature of the second pulse; For each of the plurality of test write operations, at least in part based on the execution of the plurality of test write operations, the corresponding conditions of the test memory cell are identified; as well as The modified characteristics of the second pulse are determined at least in part based on the corresponding conditions of the test memory cells for the plurality of test write operations and the corresponding characteristics of the second pulse, wherein the modification of the characteristics is at least in part based on the determination of the modified characteristics.

3. The method according to claim 1, further comprising: Identify the number of memory cells storing the first state within at least a subset of the set of memory cells, the number of memory cells including the reliability metric; as well as The number of memory cells is determined to meet a threshold, wherein the modification of the characteristics of the second pulse is based at least in part on the determination.

4. The method of claim 1, further comprising: Identify the bit error rate of at least a subset of the set of memory cells, the bit error rate including the reliability metric and associated with read operations of the set of memory cells; as well as The bit error rate is determined to meet a threshold, wherein the modification of the characteristics of the second pulse is based at least in part on the determination.

5. The method of claim 1, further comprising: Identify the number of write cycles associated with the set of memory cells, the number of write cycles including the reliability metric; as well as The number of write cycles is determined to satisfy a threshold, wherein the modification of the characteristics of the second pulse is based at least in part on the determination.

6. The method of claim 5, wherein modifying the feature comprises: The memory device is programmed with one or more fuses to configure the modified feature of the second pulse.

7. The method of claim 5, wherein modifying the feature comprises: The memory device is programmed with one or more non-volatile memory cells to configure the modified features of the second pulse.

8. The method of claim 5, wherein the set of memory cells comprises a group of memory cells configured for simultaneous access.

9. The method of claim 1, wherein the set of memory cells comprises memory cell pages, groups, or dies.

10. The method of claim 1, wherein the characteristic of the second pulse includes the time between the first pulse and the second pulse.

11. The method of claim 1, wherein modifying the feature comprises: Reduce the width of the second pulse used to write the third state.

12. The method of claim 1, wherein applying the first pulse of the first polarity comprises: Drive the bit line associated with the memory cell to a first voltage; as well as The word line associated with the memory cell is driven to a second voltage, which is lower than the first voltage.

13. The method of claim 12, wherein applying the second pulse of the second polarity comprises: Drive the bit line to a third voltage; as well as The word line is driven to a fourth voltage, where the third voltage is lower than the fourth voltage.

14. The method of claim 1, wherein the characteristics of the second pulse include the magnitude of the second pulse, the width of the second pulse, or any combination thereof.

15. An apparatus comprising: Multiple memory cells, each memory cell being capable of being written to one of a set of logic states, the set of logic states including a first logic state, a second logic state, and a third logic state, wherein writing a memory cell to the third logic state includes applying a first voltage pulse of a first polarity and a second voltage pulse of a second polarity; A circuit system capable of modifying the characteristics of the second voltage pulse based at least in part on a reliability metric of the third logic state associated with a set of memory cells among the plurality of memory cells; A word line, which is coupled to a first memory cell among the plurality of memory cells; Bit lines, which are coupled to the first memory cell; as well as A driver, wherein the driver is capable of driving the word lines and the bit lines to perform the following operations: Apply the first voltage pulse to the first memory cell; as well as A second voltage pulse having the modified characteristics is applied to the first memory cell.

16. The device according to claim 15, further comprising: One or more fuses that can be programmed to modify the characteristics of the second voltage pulse.

17. The device according to claim 15, further comprising: One or more non-volatile memory cells that can be programmed to modify the characteristics of the second voltage pulse.

18. The device of claim 15, wherein the circuit system is further capable of: Perform multiple test write operations on one of the plurality of memory cells to a test memory cell, each of the plurality of test write operations being associated with a corresponding characteristic of the second voltage pulse; For each of the plurality of test write operations, at least in part based on the execution of the plurality of test write operations, the corresponding conditions of the test memory cell are identified; as well as The modified characteristics of the second voltage pulse are determined at least in part based on the corresponding conditions of the test memory cells for the plurality of test write operations and the corresponding characteristics of the second voltage pulse, wherein the modification of the characteristics is at least in part based on the determination of the modified characteristics.

19. The device of claim 15, wherein the circuit system is further capable of: Identify the number of memory cells storing the first logic state within at least a subset of the set of memory cells, the number of memory cells including the reliability metric; and The number of memory cells is determined to meet a threshold, wherein the modification of the characteristics of the second voltage pulse is based at least in part on the determination.

20. The device of claim 15, wherein the circuit system is further capable of: Identify the bit error rate of at least a subset of the set of memory cells, the bit error rate including the reliability metric associated with read operations on the set of memory cells; and The bit error rate is determined to meet a threshold, wherein the modification of the characteristics of the second voltage pulse is based at least in part on the determination.

21. The device of claim 15, wherein the circuit system is further capable of: Identify the number of write cycles associated with the set of memory cells, the number of write cycles including the reliability metric; and The number of write cycles is determined to satisfy a threshold, wherein the modification of the characteristics of the second voltage pulse is based at least in part on the determination.

22. The device of claim 15, wherein the set of memory cells includes a memory cell page, a memory cell group, a memory cell die, or a group of memory cells configured for simultaneous access.

23. The device of claim 15, wherein the characteristics of the second voltage pulse include the time between the first voltage pulse and the second voltage pulse, the magnitude of the second voltage pulse, the width of the second voltage pulse, or any combination thereof.

24. An apparatus comprising: Multiple memory cells, each memory cell being capable of being written to one of a set of logic states, the set of logic states including a first logic state, a second logic state, and a third logic state, wherein writing a memory cell to the third logic state includes applying a first voltage pulse of a first polarity and a second voltage pulse of a second polarity; A word line, which is coupled to a first memory cell among the plurality of memory cells; Bit lines, which are coupled to the first memory cell; as well as A controller, coupled to the word lines and digital lines, is capable of: The characteristics of the second voltage pulse are set based at least in part on a reliability metric of the third logic state associated with a set of memory cells among the plurality of memory cells; The first voltage pulse is applied to the first memory cell via the word line and the digital line; as well as The second voltage pulse having the aforementioned characteristics is applied to the first memory cell via the word line and the digital line.

25. The device of claim 24, wherein the controller is further configured to: Perform multiple test write operations on one of the plurality of memory cells to a test memory cell, each of the plurality of test write operations being associated with a corresponding characteristic of the second voltage pulse; For each of the plurality of test write operations, at least in part based on the execution of the plurality of test write operations, the corresponding conditions of the test memory cell are identified; as well as The characteristics of the second voltage pulse are determined at least in part based on the corresponding conditions of the test memory cells for the plurality of test write operations and the corresponding characteristics of the second voltage pulse, wherein setting the characteristics is at least in part based on determining the characteristics.

26. The device of claim 24, wherein the controller is further configured to: Identify the number of memory cells storing the first logical state within at least a subset of the set of memory cells; Identify the bit error rate of at least a subset of the set of memory cells, the bit error rate being associated with a read operation of each memory cell in the set of memory cells; Identify the number of write cycles associated with at least a subset of the set of memory cells; as well as The number of memory cells is determined to meet a first threshold, the bit error rate is determined to meet a second threshold, or the number of write cycles is determined to meet a third threshold, or any combination thereof, wherein the modification of the characteristics of the second voltage pulse is based at least in part on the determination.

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