Chip repairing method and device, electronic equipment and storage medium

Abstract

The present disclosure provides a chip repair method and device, an electronic device and a computer readable storage medium, the method comprising: obtaining a target chip, performing multi-verification unit testing on the target chip to obtain a first test passed chip; performing single-verification unit testing on the first test passed chip to obtain a test failed chip; the test failed chip includes a partial failure chip; obtaining a failure unit address corresponding to a failure unit in the partial failure chip; obtaining a pre-configured redundant unit, and performing repair processing on the partial failure chip based on the adjacent address of the redundant unit and the failure unit address. For the failure unit that passes the multi-verification unit testing and fails the single-verification unit testing, the present disclosure uses the adjacent address of the redundant unit and the failure unit address to repair the failure unit, which can improve the stability of related area data storage and maximize the use of bit resources or die resources.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor production and manufacturing technology, and in particular to a chip repair method, a chip repair device, an electronic device, and a computer-readable storage medium. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

[0003] DRAM has a high production volume among semiconductor products and is highly competitive in the semiconductor industry. DRAM manufacturers are crucial for maximizing the number of chips per wafer, improving yield, and minimizing process complexity and cost. Currently, the primary method for repairing data in DRAM memory blocks caused by production failures is to replace the entire bit line (BL) or word line (WL). However, these repair solutions result in low word line or bit line performance.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] The purpose of the present disclosure is to provide a chip repair method, a chip repair device, an electronic device and a computer-readable storage medium, thereby overcoming, at least to a certain extent, the problem that existing chip repair solutions result in low performance of adjacent word lines or bit lines and poor stability of data storage in related areas.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0007] According to a first aspect of the present disclosure, a chip repair method is provided, comprising: obtaining a target chip, performing a multi-verification unit test on the target chip to obtain a first test-passing chip; performing a single-verification unit test on the first test-passing chip to obtain a test-failed chip; the test-failed chip includes a partially failed chip; obtaining failed unit addresses corresponding to failed units in the partially failed chip; obtaining a pre-configured redundant unit, and repairing the partially failed chip based on adjacent addresses between the redundant unit and the failed unit address.

[0008] In an exemplary embodiment of the present disclosure, performing a multi-verification unit test on the target chip to obtain a first test-passing chip includes: obtaining a pre-configured number of verification units; determining a plurality of address lines contained in the target chip; and performing the multi-verification unit test on the target chip based on the plurality of address lines and the number of verification units to obtain the first test-passing chip.

[0009] In an exemplary embodiment of the present disclosure, the multi-verification unit test is performed on the target chip based on the plurality of address lines and the number of verification units to obtain the first test-passing chip, including: arbitrarily obtaining the number of adjacent verification units from the plurality of address lines as multiple verification units; based on the multiple verification units, the multi-verification unit test is performed on the target chip to obtain a multiple verification unit test result; the first test-passing chip is determined according to the multi-verification unit test result, and the test-passing unit addresses that passed the test in the first test-passing chip are obtained.

[0010] In an exemplary embodiment of the present disclosure, performing a single verification unit test on the first test-passing chip to obtain a test-failed chip includes: performing the single verification unit test on the first test-passing chip to obtain a corresponding single verification unit test result; and determining the failure type of the test-failed chip based on the single verification unit test result.

[0011] In an exemplary embodiment of the present disclosure, performing the single verification unit test on the first test-passing chip to obtain the corresponding single verification unit test result includes: obtaining multiple verification units of the first test-passing chip and determining the verification unit address of each of the verification units; performing the single verification unit test on the multiple verification units one by one, and determining the single verification unit test result according to the verification unit address.

[0012] In an exemplary embodiment of the present disclosure, the verification unit includes any one of a die unit or a bit on an address line in the target chip.

[0013] In an exemplary embodiment of the present disclosure, determining the failure type of the test-failed chip based on the single verification unit test result includes: obtaining the unit address used for the single verification unit test; using the unit address for which the single verification unit test result fails as the failed unit address; determining the failure type of the test failure based on the failed unit address, so as to repair the test-failed chip based on the failure type.

[0014] In an exemplary embodiment of the present disclosure, determining the failure type of the test failure based on the failed unit address includes: obtaining all unit addresses on the address line in the chip that passed the first test; if all unit addresses on the address line are the failed unit addresses, determining the failure type as an overall failure of the address line; if some unit addresses on the address line are the failed unit addresses, determining the failure type as a partial failure of the address line.

[0015] In an exemplary embodiment of the present disclosure, the repairing of the partially failed chip according to the failure type includes: if the failure type is the overall failure of the address line, determining the failed address line of the tested failed chip; obtaining a pre-configured redundant address line, and using the redundant address line to repair the failed address line.

[0016] In an exemplary embodiment of the present disclosure, the patching process for the partially failed chip based on the adjacent addresses of the redundant unit and the failed unit address includes: using the redundant unit to replace the failed unit in the partially failed chip; obtaining the adjacent address of the failed unit address as the patching unit address; and using the patching unit address as the address of the redundant unit after the replacement operation.

[0017] In an exemplary embodiment of the present disclosure, obtaining the adjacent address of the failed unit address includes: obtaining the test passing unit address corresponding to the multi-verification unit test performed on the partially failed chip; and using the test passing unit address as the adjacent address of the failed unit address.

[0018] In an exemplary embodiment of the present disclosure, the multi-verification unit test and the single-verification unit test are applied to chip testing, and the chip testing includes any one of wafer testing and functional testing, or a combination of the two.

[0019] According to a second aspect of the present disclosure, a chip repair device is provided, comprising: a multi-verification unit test module for acquiring a target chip, performing a multi-verification unit test on the target chip, and obtaining a first test-passing chip; a single-verification unit test module for performing a single-verification unit test on the first test-passing chip, and obtaining a test-failed chip; the test-failed chip includes a partially failed chip; an address acquisition module for acquiring failed unit addresses corresponding to failed units in the partially failed chip; and a chip repair module for acquiring a pre-configured redundant unit and repairing the partially failed chip based on adjacent addresses of the redundant unit and the failed unit address.

[0020] In an exemplary embodiment of the present disclosure, the multi-verification unit test module includes a multi-verification unit test unit, which is used to obtain a pre-configured number of verification units; determine a plurality of address lines contained in the target chip; and perform the multi-verification unit test on the target chip based on the plurality of address lines and the number of verification units to obtain the first test-passing chip.

[0021] In an exemplary embodiment of the present disclosure, the multi-verification unit test unit includes a multi-verification unit test sub-unit, which is used to arbitrarily obtain the number of adjacent verification units of the verification unit from the multiple address lines as multi-verification units; based on the multi-verification units, the multi-verification unit test is performed on the target chip to obtain a multi-verification unit test result; the first test-passing chip is determined according to the multi-verification unit test result, and the test-passing unit address that passed the test in the first test-passing chip is obtained.

[0022] In an exemplary embodiment of the present disclosure, the single verification unit test module includes a single verification unit test unit, which is used to perform the single verification unit test on the chip that passed the first test to obtain a corresponding single verification unit test result; and determine the failure type of the test-failed chip based on the single verification unit test result.

[0023] In an exemplary embodiment of the present disclosure, the single verification unit test unit includes a single verification unit test sub-unit, which is used to obtain multiple verification units of the chip that passed the first test and determine the verification unit address of each of the verification units; perform the single verification unit test on the multiple verification units one by one, and determine the single verification unit test result according to the verification unit address.

[0024] In an exemplary embodiment of the present disclosure, the single verification unit test unit includes a first chip repair sub-unit, which is used to obtain the unit address used for the single verification unit test; use the unit address for which the single verification unit test result fails as the failed unit address; determine the failure type of the test failure based on the failed unit address, so as to repair the test failed chip according to the failure type.

[0025] In an exemplary embodiment of the present disclosure, the first chip repair subunit includes a failure type determination subunit, which is used to obtain all unit addresses on the address lines in the first test-passing chip; if all unit addresses on the address lines are the failed unit addresses, the failure type is determined to be an overall failure of the address line; if some unit addresses on the address lines are the failed unit addresses, the failure type is determined to be a partial failure of the address line.

[0026] In an exemplary embodiment of the present disclosure, the first chip repair subunit includes a redundant repair subunit, which is used to determine the failed address line of the test failed chip if the failure type is the overall failure of the address line; obtain a pre-configured redundant address line, and use the redundant address line to repair the failed address line.

[0027] In an exemplary embodiment of the present disclosure, the chip repair module includes a chip repair unit, which is used to replace the failed unit in the partially failed chip with the redundant unit; obtain the adjacent address of the failed unit address as the repair unit address; and use the repair unit address as the address of the redundant unit after the replacement operation.

[0028] In an exemplary embodiment of the present disclosure, the chip repair unit includes an adjacent address determination subunit for obtaining the test passing unit address corresponding to the multi-verification unit test on the partially failed chip; and using the test passing unit address as the adjacent address of the failed unit address.

[0029] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the chip repair method according to any one of the above items is implemented.

[0030] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the chip repair method according to any one of the above items is implemented.

[0031] The technical solution provided by the present disclosure may have the following beneficial effects:

[0032] The chip repair method disclosed in the exemplary embodiments of the present disclosure, on the one hand, uses redundant cells and adjacent addresses of the failed cell address to repair address lines in the target chip that have passed multiple verification unit tests but failed a single verification unit test. This improves the performance of the address lines adjacent to the failed cell address and enhances data storage at adjacent addresses. On the other hand, using adjacent addresses of the failed cell address as the basis for repairing the failed cell address improves the stability of data storage in the relevant area of ​​the chip and maximizes the utilization of bit resources or die resources.

[0033] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0035] Figure 1 Schematically shows a flow chart of a chip repair method according to an exemplary embodiment of the present disclosure;

[0036] Figure 2 Schematically shows a flow chart of performing multi-verification unit test patching according to an exemplary embodiment of the present disclosure;

[0037] Figure 3 Schematically shows an overall flow chart of a chip repair solution using adjacent address lines according to an exemplary embodiment of the present disclosure;

[0038] Figure 4 Schematically shows a structural diagram of adjacent address lines in a target chip according to an exemplary embodiment of the present disclosure;

[0039] Figure 5 Schematically illustrates a schematic diagram of determining a verification unit address according to an exemplary embodiment of the present disclosure;

[0040] Figure 6 Schematically shows a block diagram of a chip repair device according to an exemplary embodiment of the present disclosure;

[0041] Figure 7 A block diagram schematically illustrates an electronic device according to an exemplary embodiment of the present disclosure;

[0042] Figure 8 A schematic diagram schematically illustrates a computer-readable storage medium according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the drawings represent like or similar parts, and thus repetitive description thereof will be omitted.

[0044] In addition, the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known structures, methods, devices, implementations, materials or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0045] The blocks shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. Specifically, these functional entities may be implemented in software, or in one or more software-hardened modules, or in different networks and / or processor devices and / or microcontroller devices.

[0046] Currently, the primary method for repairing data in DRAM memory areas caused by manufacturing errors is to replace an entire bit line (BL) or word line (WL). However, these repair solutions reduce word line or bit line performance and compromise the stability of data storage in the affected area.

[0047] Based on this, in this example embodiment, a chip repair method is first provided. The chip repair method of the present disclosure can be implemented using a server, or the method described in the present disclosure can be implemented using a terminal device. The terminals described in the present disclosure may include mobile terminals such as mobile phones, tablet computers, laptops, PDAs, personal digital assistants (PDAs), and fixed terminals such as desktop computers. Figure 1 The schematic diagram schematically shows the process of the chip repair method according to some embodiments of the present disclosure. Figure 1 , the chip repair method may include the following steps:

[0048] Step S110 , obtaining a target chip, performing a multi-verification unit test on the target chip, and obtaining a first test-passing chip.

[0049] According to some exemplary embodiments of the present disclosure, a target chip may be a chip to be tested and a corresponding chip repair solution determined based on the chip test results. A multi-verification unit test may be a process that tests the target chip as a whole using multiple verification units on address lines within the target chip. The first test-passing chip may be a target chip that passes the multi-verification unit test process.

[0050] During semiconductor manufacturing, data storage areas may experience anomalies. To improve chip yield, DRAM repair is often performed. To address the issues of wasted bit resources or poor performance of adjacent bit lines or word lines caused by replacing an entire bit line or word line, this embodiment combines multi-verification unit testing with single-verification unit testing to perform DRAM repair.

[0051] A target chip is obtained. During chip testing, the target chip is tested using different test methods to identify the verification units in the target chip that can be patched. For example, during the test process, a multi-verification unit test method may be first used to test the target chip and obtain corresponding test results. The multi-verification unit test method may include testing multiple verification units of address lines in the target chip as a single verification unit. If the target chip passes the multi-verification unit test, the target chip is designated as the first tested chip.

[0052] Step S120 , performing a single verification unit test on the chips that passed the first test to obtain test-failed chips; the test-failed chips include some failed chips.

[0053] According to some exemplary embodiments of the present disclosure, a single verification unit test may be a process in which a verification unit on an address line in a target chip is treated as a whole to perform chip testing on the target chip. A test-failed chip may be a chip that passes the multi-verification unit test but fails the single-verification unit test. A partially failed chip may be a target chip in which, after a single-verification unit test, some verification units on the address line are valid and some are invalid.

[0054] Through multi-verification unit testing, target chips that passed the multi-verification unit test, i.e., the first test-passing chips, can be identified. These chips can then be subjected to single-verification unit testing. Single-verification unit testing primarily involves treating the smallest-granularity verification unit on the address lines of the first-test-passing chips as a single verification unit and testing the first-test-passing chips. After the single-verification unit test is completed, test failure chips, i.e., chips that failed the single-verification unit test, can be identified based on the test results.

[0055] After obtaining the test-failed chips, partially failed chips can be determined from the test-failed chips. The partially failed chips are chips in which some verification units on chip address lines are valid and some verification units are invalid.

[0056] Step S130 , obtaining failed cell addresses corresponding to failed cells in some failed chips.

[0057] According to some exemplary embodiments of the present disclosure, the failed unit may be a verification unit that fails on a certain address line in the target chip after a single verification unit test, and the failed unit address may be an address corresponding to the failed unit.

[0058] After identifying some failed chips, the failed unit addresses corresponding to the failed units in the failed chips can be obtained. The address lines in the target chip are all numbered, such as 0, 1, 2, 3, 4, 5, and so on. The addresses of the verification units on these address lines can be determined based on the address line numbers. If a verification unit fails during a single verification unit test, the address of the failed verification unit is obtained and used as the failed unit address.

[0059] Step S140 , obtaining pre-configured redundant units, and repairing some failed chips based on the adjacent addresses of the redundant units and the failed unit addresses.

[0060] According to some exemplary embodiments of the present disclosure, the redundant cells may be pre-configured valid verification cells. The adjacent addresses of the failed cell address may be the addresses of other verification cells adjacent to the failed cell address. The repair process may be a process of repairing some failed chips.

[0061] After obtaining the failed cell address, the failed chips are repaired using pre-configured redundant cells. To perform DRAM repair, some redundant cells can be pre-configured to replace the failed verification cells in the address lines. The adjacent addresses of the failed cell addresses are used as the new addresses of the redundant cells that replace the failed cells, thus completing the DRAM repair process.

[0062] According to the chip repair method of this exemplary embodiment, for address lines in a target chip that pass multiple verification unit tests but fail a single verification unit test, address lines adjacent to the failed unit address are repaired using redundant units. This improves the performance of address lines adjacent to the failed unit and enhances data storage at adjacent addresses. Furthermore, using adjacent addresses of the failed unit address as the basis for repairing the failed unit improves the stability of data storage in the relevant area of ​​the chip and maximizes the utilization of bit resources or die resources.

[0063] Next, the chip repair method in this exemplary embodiment will be further described.

[0064] In an exemplary embodiment of the present disclosure, a multi-verification unit test is performed on a target chip to obtain a first test-passing chip, including: obtaining a pre-configured number of verification units; determining a plurality of address lines included in the target chip; and performing a multi-verification unit test on the target chip based on the plurality of address lines and the number of verification units to obtain a first test-passing chip.

[0065] The number of verification units may be the number of verification units of the minimum granularity included in a total verification unit during a multi-verification unit test, for example, the number of verification units may be 2 (bit, byte). The address lines may be data output lines included in a target chip, for example, the address lines may include word lines and bit lines.

[0066] The chip test process of the target chip can usually be applied to wafer test or functional test. For example, chip test can be used alone in wafer test or functional test, or chip test can be used in a combination of wafer test and functional test. Figure 2 , Figure 2 The flowchart of performing multi-verification unit test and repair according to the exemplary embodiment of the present disclosure is schematically shown. In step S210, wafer test and functional test are performed on the target chip, and normal redundant repair is performed. During the wafer test and functional test process, it can be performed by multi-verification unit test and single verification unit test. After completing the wafer test and functional test, the target chip can be repaired using the normal redundant repair scheme. In step S220, it is checked whether the replacement word line / bit line fails as a whole. In step S230, if the replacement word line / bit line fails as a whole, the subsequent execution steps are canceled. In step S240, if the replacement word line / bit line does not fail as a whole, the target chip can be repaired using the multi-verification unit test and repair scheme.

[0067] Specifically, the multi-verification unit patching method can be carried out through the following steps: Figure 3 , Figure 3 The following schematically illustrates an overall flow chart of a chip repair solution using adjacent address lines according to an exemplary embodiment of the present disclosure. First, a multi-verification unit test is performed on a target chip. During the multi-verification unit test, the number of verification units can be configured to two, meaning that two verification units are used as a single verification unit to test the target chip. In this case, the multi-verification test becomes a double-byte test. This embodiment uses a double-byte test as an example for explanation.

[0068] In step S310, double byte test (twin cell test) is carried out to target chip.In double byte test, can obtain all address lines that comprise in target chip, according to all address lines and verification unit quantity determined, target chip is carried out multi-verification unit test process.In double byte test, two verification units on the address line in target chip can be tested as a whole.After multi-verification unit test finishes, can determine that first test passes through chip according to test result.

[0069] In an exemplary embodiment of the present disclosure, a multi-verification unit test is performed on a target chip based on multiple address lines and the number of verification units to obtain a first test-passing chip, including: arbitrarily obtaining a number of adjacent verification units from the multiple address lines as multiple verification units; based on the multiple verification units, a multi-verification unit test is performed on the target chip to obtain a multiple verification unit test result; the first test-passing chip is determined according to the multiple verification unit test result, and the test-passing unit addresses that passed the test in the first test-passing chip are obtained.

[0070] The adjacent verification units may be verification units located on two adjacent address lines. The multi-verification unit may be a total verification unit composed of multiple verification units during a multi-verification unit test. The multi-verification unit test result may be a test result obtained after performing a multi-verification unit test on a target chip. The test pass unit address is the address of the address line where the verification unit that passed the test is located, determined after performing a multi-verification unit test on the target chip.

[0071] After determining the address lines included in the target chip, any number of adjacent verification units can be obtained from multiple address lines as multiple verification units. Specifically, the verification unit on the address line includes any one of a cell or a bit on the address line; wherein the cell can be the cell corresponding to the address line in the target chip; and the bit can be the bit on the address in the target chip. This disclosure will use a single cell or bit as the smallest verification unit. Figure 4 , Figure 4 Schematically shows a structure diagram of the target chip adjacent to the address line according to an exemplary embodiment of the present disclosure. Figure 4 It can be seen that the target chip includes odd-numbered word lines and bit lines, as well as even-numbered word lines and bit lines.

[0072] During the multi-verification unit test, verification units on any two adjacent address lines can be selected from the target chip's multiple address lines as a multi-verification unit. For example, the bits on address lines 0 and 1 can be selected as a multi-verification unit; or the bits on address lines 5 and 6 can be selected as a multi-verification unit. After the adjacent multi-verification units are obtained, a multi-verification unit test is performed on the target chip based on the adjacent multi-verification units to obtain the corresponding multi-verification unit test results, facilitating subsequent chip repair based on the test results obtained from the adjacent verification units.

[0073] Continue to refer Figure 3, in step S302, the test results are recorded. After completing the multi-verification unit test, the test results of the target chip can be recorded, and the test results can include the addresses of the multi-verification units. For example, the multi-verification unit test results can include a multi-verification unit test failure (i.e., result 301) and a multi-verification unit test pass (i.e., result 302). The target chip that passed the multi-verification unit test is taken as the first test-passing chip. After determining the first test-passing chip, the test pass unit address (passaddress) corresponding to the multi-verification unit that passed the test in the first test-passing chip can be obtained.

[0074] In an exemplary embodiment of the present disclosure, a single verification unit test is performed on a first test-passing chip to obtain a test-failed chip, including: performing a single verification unit test on the first test-passing chip to obtain a corresponding single verification unit test result; and determining the failure type of the test-failed chip based on the single verification unit test result.

[0075] The single verification unit test result may be a test result obtained after a single verification unit test is performed on the target chip. The partially failed chip may be a chip with some failed verification units in the address lines determined after the target chip passes the multi-verification unit test and undergoes a single verification unit test.

[0076] Continue to refer Figure 3 , in step S303, a single verification unit test (single cell test) is performed on the chip that passes the first test. Specifically, the single verification unit test can be a process of testing a crystal cell (CELL) or a bit on an address line. In step S304, the test results are recorded. After the single verification unit test is completed, the corresponding single verification unit test result is obtained, and the test result can also include the address of the single verification unit. For example, the single verification unit test result may include a single verification unit test passing (i.e., result 303) and a single verification unit test failing (i.e., result 304). Since the chips that fail the single verification unit test include many different types, the chips with all address lines failing and the chips with some address lines failing can be determined based on the test results, so as to use the corresponding repair solution to repair the specific type of chip.

[0077] In an exemplary embodiment of the present disclosure, a single verification unit test is performed on the first test-passing chip to obtain a corresponding single verification unit test result, including: obtaining multiple verification units of the first test-passing chip and determining the verification unit address of each verification unit; performing a single verification unit test on the multiple verification units one by one, and determining the single verification unit test result according to the verification unit address.

[0078] The verification unit address may be the address corresponding to each verification unit.

[0079] When performing a single verification unit test on a chip that passes the first test, verification units can be retrieved one by one from multiple verification units on the address line, and all verification units on the address line in the chip can be tested one by one. Since an address line can contain multiple verification units, one verification unit can be retrieved at a time for testing. For example, a cell or bit can be retrieved from the address line as the target verification unit, and the address corresponding to the target verification unit, i.e., the target unit address, can be recorded.

[0080] A single verification unit test is performed on the chip that passed the first test based on the target verification unit. After the test process of the current target verification unit is completed, another verification unit is obtained from the address line and used as the new target verification unit. The single verification unit test is performed again until all verification units on the address lines in the chip that passed the first test are tested. After the single verification unit test is completed, the single verification unit test result can be determined based on the target unit address.

[0081] In an exemplary embodiment of the present disclosure, the failure type of a test-failed chip is determined based on a single-verification unit test result, including: obtaining a unit address used for the single-verification unit test; using a unit address for which the single-verification unit test result fails as a failed unit address; determining the failure type of the test failure based on the failed unit address, so as to repair the test-failed chip based on the failure type.

[0082] The failed cell address may be the address of the failed cell determined after a single verification unit test is performed on the chip that passed the first test. The failure type of the test failure may be the specific type of test failure determined after a single verification unit test is performed on the chip that passed the first test. For example, the test failure may include a partial address line failure and an entire address line failure.

[0083] Since the unit address corresponding to each verification unit is recorded during the single verification unit test of the chip that passed the first test, the test result of the verification unit can be determined based on each unit address after the single verification unit test is completed. For example, when the single verification unit test result of a certain verification unit is failed, the unit address corresponding to the verification unit can be used as the failed unit address. The above steps are used to determine the test results corresponding to all unit addresses and determine all failed unit addresses. Figure 3 In step S305, the failure type is determined. The failure type of the test failure is determined based on the addresses of all failed cells on the address line, so that different repair schemes are used for repair processing according to different failure types.

[0084] In an exemplary embodiment of the present disclosure, the failure type of a test failure is determined based on the failed unit address, including: obtaining all unit addresses on the address line in the first test-passing chip; if all unit addresses on the address line are failed unit addresses, the failure type is determined as an overall failure of the address line; if some unit addresses on the address line are failed unit addresses, the failure type is determined as a partial failure of the address line.

[0085] The "all unit addresses" may be the addresses of all verification units on a certain address line in the first test-passing chip. The "full address line failure" may be a failure type in which all address lines in the first test-passing chip fail. The "partial unit addresses" may be the addresses corresponding to a portion of verification units on a certain address line in the first test-passing chip. The "partial address line failure" may be a failure type in which a portion of verification units on a certain address line in the first test-passing chip fail.

[0086] After the single verification unit test is completed, all unit addresses on the address line in the chip that passed the first test can be obtained, and the failure type of the chip can be determined based on the test results of all unit addresses. If all unit addresses on the address line are failed unit addresses, it means that all verification unit tests on the address line have failed. Therefore, the failure type can be determined as the overall failure of the address line (i.e., failure type 305). If some unit addresses on the address line are failed unit addresses, it means that some verification unit tests on the address line have passed, and other verification unit tests have failed. The failure type of this type of address line is determined as partial failure of the address line (i.e., failure type 306). Through the above-mentioned method of determining the failed unit address, different failure types of the address line can be determined so that the corresponding repair scheme can be used for subsequent repair.

[0087] In an exemplary embodiment of the present disclosure, a test failed chip is repaired according to the failure type, including: if the failure type is an overall failure of the address line, determining the failed address line of the test failed chip; obtaining a pre-configured redundant address line, and using the redundant address line to repair the failed address line.

[0088] The failed address line may be an address line whose entire address line is failed. The redundant address line may be an address line pre-configured to replace the failed address line.

[0089] Continue to refer Figure 3In step S306, the failed word line / bit line is replaced with a redundant one. If the failure type is a complete address line failure, the failed address line in the failed chip can be identified as the failed address line. Specifically, the entire failed address line in a twin cell pass and single cell fail state can be identified as the failed address line. For the failed address line, a pre-configured redundant address line can be retrieved and used to completely replace the failed address line for chip repair.

[0090] In an exemplary embodiment of the present disclosure, a partial failed chip is repaired based on the adjacent addresses of the redundant unit and the failed unit address, including: using the redundant unit to replace the failed unit in the partial failed chip; obtaining the adjacent address of the failed unit address as the repair unit address; and using the repair unit address as the address of the redundant unit after the replacement operation.

[0091] The adjacent address of the failed cell address may be the address of the verification unit on the adjacent address line used to replace the failed cell address. The repair cell address may be the verification unit address combined with the redundant unit to repair part of the failed chip.

[0092] When the failure type is partial address line failure, continue to refer to Figure 3 , in step S307, redundantly replace the failed cell. Obtain pre-configured redundant cells, and use the redundant cells to replace the failed cells in some failed chips. In addition, in order to improve the performance of adjacent word lines / bit lines, in step S308, the failed bit line / word line and the adjacent bit line / word line addresses are rewritten to the address locations recorded during the double-byte test. Obtain the adjacent address of the failed cell address, use the address as the repair cell address, and point the repair cell address to the address of the redundant cell used to replace the failed cell. Through the above-mentioned repair method, the original twin cell can be converted into a single cell pass under this fail BL / WL reinforcement, thereby improving the performance of the adjacent bit line or word line and maximizing the utilization of bit resources or chip resources.

[0093] In an exemplary embodiment of the present disclosure, obtaining adjacent addresses of a failed cell address includes: obtaining test-passed cell addresses corresponding to multi-verification unit tests performed on some failed chips; and using the test-passed cell addresses as adjacent addresses of the failed cell address.

[0094] refer to Figure 5 , Figure 5The schematic diagram of determining the verification unit address according to the exemplary embodiment of the present disclosure is schematically shown. When determining the verification unit address, the corresponding test passing unit address after the multi-verification unit test on the partially failed chip is obtained, and the test passing address can be used as the adjacent address of the failed unit address. Since the address of the verification unit is passed in the multi-verification unit test, after the single verification unit test, the adjacent address of the failed unit address is pointed to the redundant unit, and the repair processing of the failed unit can be completed. The above-mentioned repair processing scheme adopts a pre-configured redundant unit to replace the failed unit, and the adjacent address of the failed unit address is the address that has passed the multi-verification unit test. Using this address as the new address of the redundant unit can improve the performance of the verification unit, improve the stability of data storage in the relevant area, and maximize the use of bit resources or grain resources.

[0095] In summary, a target chip is obtained, a multi-verification unit test is performed on the target chip to obtain a first test-passing chip; a single-verification unit test is performed on the first test-passing chip to obtain a test-failed chip; the test-failed chip includes a partially failed chip; the failed cell addresses corresponding to the failed cells in the partially failed chips are obtained; a pre-configured redundant cell is obtained, and the partially failed chips are repaired based on the redundant cell and the adjacent addresses of the failed cell addresses. On the one hand, for address lines in the target chip that pass the multi-verification unit test but fail the single-verification unit test, repairing them using the redundant cell and the adjacent addresses of the failed cell address can improve the performance of the adjacent address lines of the failed cell and enhance the data storage effect of the adjacent addresses. On the other hand, using the adjacent addresses of the failed cell address as the basis for repairing the failed cell can improve the stability of data storage in the relevant area of ​​the chip. On the other hand, repairing the adjacent addresses of the redundant cell and the failed cell address can enhance the capacitance of the verification unit (such as the die) and maximize the utilization of bit resources or die resources.

[0096] It should be noted that although the steps of the method of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0097] In addition, in this exemplary embodiment, a chip repair device is also provided. Figure 6 The chip repair device 600 may include: a multi-verification unit test module 610 , a single verification unit test module 620 , an address acquisition module 630 and a chip repair module 640 .

[0098] Specifically, the multi-verification unit test module 610 is used to obtain a target chip, perform a multi-verification unit test on the target chip, and obtain a first test-passing chip; the single-verification unit test module 620 is used to perform a single-verification unit test on the first test-passing chip to obtain a test-failed chip; the test-failed chip includes a partially failed chip; the address acquisition module 630 is used to obtain the failed unit address corresponding to the failed unit in the partially failed chip; the chip repair module 640 is used to obtain a pre-configured redundant unit and repair the partially failed chip based on the adjacent address of the redundant unit and the failed unit address.

[0099] In an exemplary embodiment of the present disclosure, the chip repair device 600 also includes a target chip acquisition module for acquiring an initial chip; performing chip testing on the initial chip to obtain a chip test result; the chip test includes any one of wafer testing and functional testing or a combination of two; performing redundant repair processing on the failed chip in the chip test to obtain a first repair chip; acquiring the failure status of the address line in the first repair chip; if the failure status is a partial failure of the address line, the first repair chip is used as the target chip.

[0100] In an exemplary embodiment of the present disclosure, the multi-verification unit test module 610 includes a multi-verification unit test unit, which is used to obtain a pre-configured number of verification units; determine the multiple address lines contained in the target chip; and perform a multi-verification unit test on the target chip based on the multiple address lines and the number of verification units to obtain a first test-passing chip.

[0101] In an exemplary embodiment of the present disclosure, a multi-verification unit test unit includes a multi-verification unit test sub-unit, which is used to obtain any number of adjacent verification units from multiple address lines as multiple verification units; based on the multiple verification units, a multi-verification unit test is performed on a target chip to obtain a multi-verification unit test result; a first test-passing chip is determined according to the multi-verification unit test result, and the test-passing unit address that passed the test in the first test-passing chip is obtained.

[0102] In an exemplary embodiment of the present disclosure, the single verification unit test module 620 includes a single verification unit test unit, which is used to perform a single verification unit test on the chip that passed the first test to obtain a corresponding single verification unit test result; and determine the failure type of the test failed chip based on the single verification unit test result.

[0103] In an exemplary embodiment of the present disclosure, the single verification unit test unit includes a single verification unit test sub-unit, which is used to obtain multiple verification units of the chip that passed the first test and determine the verification unit address of each verification unit; perform single verification unit tests on the multiple verification units one by one, and determine the single verification unit test results according to the verification unit addresses.

[0104] In an exemplary embodiment of the present disclosure, the single verification unit test unit includes a first chip repair sub-unit, which is used to obtain the unit address used for the single verification unit test; use the unit address for which the single verification unit test result fails as the failed unit address; determine the failure type of the test failure based on the failed unit address, so as to repair the test failed chip based on the failure type.

[0105] In an exemplary embodiment of the present disclosure, the first chip repair subunit includes a failure type determination subunit, which is used to obtain all unit addresses on the address lines in the first test-passing chip; if all unit addresses on the address lines are failed unit addresses, the failure type is determined as an overall failure of the address line; if some unit addresses on the address lines are failed unit addresses, the failure type is determined as a partial failure of the address line.

[0106] In an exemplary embodiment of the present disclosure, the first chip repair subunit includes a redundant repair subunit, which is used to determine the failed address line of the failed chip to be tested if the failure type is the overall failure of the address line; obtain a pre-configured redundant address line, and use the redundant address line to repair the failed address line.

[0107] In an exemplary embodiment of the present disclosure, the chip repair module 640 includes a chip repair unit for replacing failed units in a portion of failed chips with redundant units; obtaining an adjacent address of the failed unit address as a repair unit address; and using the repair unit address as the address of the redundant unit after the replacement operation.

[0108] In an exemplary embodiment of the present disclosure, the chip repair unit includes an adjacent address determination subunit for obtaining the test passing unit addresses corresponding to the multi-verification unit tests on some failed chips; and using the test passing unit addresses as the adjacent addresses of the failed unit addresses.

[0109] The specific details of the virtual modules of the aforementioned chip repair devices have been described in detail in the corresponding chip repair methods, and thus will not be repeated here.

[0110] It should be noted that while the detailed description above mentions several modules or units of the chip repair apparatus, this division is not mandatory. In fact, according to embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in a single module or unit. Conversely, the features and functions of a single module or unit described above may be further divided and embodied by multiple modules or units.

[0111] In addition, in an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

[0112] Those skilled in the art will appreciate that various aspects of the present invention may be implemented as systems, methods, or program products. Accordingly, various aspects of the present invention may be implemented as a complete hardware embodiment, a complete software embodiment (including firmware, microcode, etc.), or a combination of hardware and software embodiments, which may be collectively referred to herein as "circuits," "modules," or "systems."

[0113] Reference below Figure 7 7 to describe an electronic device 700 according to such an embodiment of the present disclosure. Figure 7 The electronic device 700 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0114] like Figure 7 As shown, electronic device 700 is implemented as a general-purpose computing device. Components of electronic device 700 may include, but are not limited to, the aforementioned at least one processing unit 710, the aforementioned at least one storage unit 720, a bus 730 connecting various system components (including storage unit 720 and processing unit 710), and a display unit 740.

[0115] The storage unit stores program codes, which can be executed by the processing unit 710, so that the processing unit 710 performs the steps according to various exemplary embodiments of the present disclosure described in the above “Exemplary Method” section of this specification.

[0116] The storage unit 720 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 721 and / or a cache memory unit 722 , and may further include a read-only memory unit (ROM) 723 .

[0117] The storage unit 720 may include a program / utility 724 having a set (at least one) of program modules 725, such program modules 725 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0118] Bus 730 may represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0119] The electronic device 700 can also communicate with one or more external devices 770 (e.g., a keyboard, a pointing device, a Bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 700, and / or any device that enables the electronic device 700 to communicate with one or more other computing devices (e.g., a router, a modem, etc.). Such communication can occur via an input / output (I / O) interface 750. Furthermore, the electronic device 700 can also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network such as the Internet) via a network adapter 760. As shown, the network adapter 760 communicates with other modules of the electronic device 700 via a bus 730. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with the electronic device 700, including but not limited to microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0120] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes a number of instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

[0121] In exemplary embodiments of the present disclosure, a computer-readable storage medium is also provided, storing a program product capable of implementing the aforementioned methods of this specification. In some possible embodiments, various aspects of the present invention may also be implemented in the form of a program product comprising program code. When the program product is executed on a terminal device, the program code is configured to cause the terminal device to perform the steps according to various exemplary embodiments of the present invention described in the "Exemplary Methods" section of this specification.

[0122] refer to Figure 8 , a program product 800 for implementing the above method according to an embodiment of the present invention is described. The program product 800 may be a portable compact disc read-only memory (CD-ROM) and include program code, and may be run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0123] The program product may be implemented in any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0124] A computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0125] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0126] The program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and the like, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0127] Furthermore, the above-described figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention and are not intended to be limiting. It is readily understood that the processes illustrated in the above-described figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0128] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow from the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0129] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A chip repair method, characterized in that: include: Obtaining a target chip, performing a multi-verification unit test on the target chip, and obtaining a first test-passing chip; Performing a single verification unit test on the chip that passed the first test to obtain a test-failed chip; The test failed chips include some failed chips; Obtaining failed unit addresses corresponding to failed units in the partially failed chips; Obtaining a pre-configured redundant unit, and repairing the partially failed chips based on adjacent addresses of the redundant unit and the failed unit; The step of performing a multi-verification unit test on the target chip to obtain a first test-passing chip includes: Get the pre-configured number of verification units; Determining a plurality of address lines included in the target chip; Based on the multiple address lines and the number of verification units, the target chip is subjected to the multi-verification unit test to obtain the first test-passing chip; the number of verification units is the number of verification units with the minimum granularity contained in a total verification unit during the multi-verification unit test.

2. The method according to claim 1, characterized in that The step of performing the multi-verification unit test on the target chip based on the plurality of address lines and the number of verification units to obtain the first test-passing chip includes: Randomly obtain adjacent verification units of the number of verification units from the plurality of address lines as multiple verification units; Based on the multi-verification unit, performing the multi-verification unit test on the target chip to obtain a multi-verification unit test result; The first test-passing chip is determined according to the test results of the multiple verification units, and the addresses of the test-passing units in the first test-passing chip that have passed the test are obtained.

3. The method according to claim 1, characterized in that The step of performing a single verification unit test on the chip that passed the first test to obtain a test-failed chip includes: Performing the single verification unit test on the first test-passing chip to obtain a corresponding single verification unit test result; The failure type of the test-failed chip is determined according to the test result of the single verification unit.

4. The method according to claim 3, characterized in that The performing the single verification unit test on the first test-passing chip to obtain a corresponding single verification unit test result includes: Acquire multiple verification units of the chip that passed the first test, and determine a verification unit address of each verification unit; The single verification unit test is performed on the plurality of verification units one by one, and the single verification unit test result is determined according to the verification unit address.

5. The method according to claim 2 or 4, characterized in that The verification unit includes any one of a die unit or a bit on an address line in the target chip.

6. The method according to claim 3, characterized in that The determining the failure type of the test-failed chip according to the test result of the single verification unit includes: Obtain the unit address used by the single verification unit test; The unit address for which the single verification unit test result fails is used as the failed unit address; The failure type of the test failure is determined according to the failed unit address, so as to repair the test failed chip according to the failure type.

7. The method according to claim 6, characterized in that The determining the failure type of the test failure according to the failed unit address includes: Obtaining all unit addresses on address lines in the chip that passed the first test; If all unit addresses on the address line are the failed unit addresses, the failure type is determined to be an overall failure of the address line; If some of the unit addresses on the address line are the failed unit addresses, the failure type is determined to be a partial address line failure.

8. The method according to claim 7, characterized in that The repairing of the test failed chip according to the failure type includes: If the failure type is an overall address line failure, determining the failed address line of the tested failed chip; A pre-configured redundant address line is obtained, and the failed address line is repaired using the redundant address line.

9. The method according to claim 1, characterized in that The repairing of the partially failed chips based on the adjacent addresses of the redundant unit and the failed unit address includes: Replacing the failed units in the partially failed chips with the redundant units; Obtaining an adjacent address of the failed unit address as a repair unit address; The repair unit address is used as the address of the redundant unit after the replacement operation.

10. The method according to claim 9, characterized in that The obtaining of the adjacent address of the failed unit address includes: Obtaining test passing unit addresses corresponding to the partially failed chips after the multi-verification unit test is performed on the partially failed chips; The test-passed unit address is used as an adjacent address of the failed unit address.

11. The method according to claim 1, wherein The multi-verification unit test and the single-verification unit test are applied to chip testing, and the chip testing includes any one of wafer testing and functional testing or a combination of the two.

12. A chip repair device, characterized in that: include: A multi-verification unit test module is used to obtain a target chip, perform a multi-verification unit test on the target chip, and obtain a first test-passing chip; A single verification unit test module, configured to perform a single verification unit test on the chips that passed the first test to obtain test-failed chips; the test-failed chips include partially failed chips; An address acquisition module, configured to acquire failed unit addresses corresponding to failed units in the partially failed chips; A chip repair module is used to obtain pre-configured redundant units and repair the partially failed chips based on adjacent addresses of the redundant units and the failed unit addresses; The step of performing a multi-verification unit test on the target chip to obtain a first test-passing chip includes: Get the pre-configured number of verification units; Determining a plurality of address lines included in the target chip; Based on the multiple address lines and the number of verification units, the target chip is subjected to the multi-verification unit test to obtain the first test-passing chip; the number of verification units is the number of verification units with the minimum granularity contained in a total verification unit during the multi-verification unit test.

13. An electronic device, characterized in that: include: processor; as well as A memory having computer-readable instructions stored thereon, wherein the computer-readable instructions are executed by the processor to implement the chip repair method according to any one of claims 1 to 11.

14. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the chip repair method according to any one of claims 1 to 11 is implemented.

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