Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate, a GaN layer and a barrier layer sequentially formed on the substrate, a first groove formed by etching the GaN layer and the barrier layer, and an n-type heavily doped GaN material formed in the first groove and on the upper surface of the barrier layer adjacent to the first groove. The present invention improves the ohmic contact between the n-type heavily doped GaN material and the sidewalls of the GaN heterojunction by filling the first groove with the n-type heavily doped GaN material and extending it to the upper surface of the barrier layer, thereby reducing the contact resistance between the n-type heavily doped GaN material and the sidewalls of the GaN heterojunction. After the secondary epitaxial n-type heavily doped GaN material grows in the first groove, it continues to grow laterally on the barrier layer, which helps to improve the surface roughness of the n-type heavily doped GaN material and further reduces the contact resistance between the n-type heavily doped GaN material and the metal.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the semiconductor device. Background Art

[0002] The enhanced high electron mobility transistor structure and implementation method use metal organic chemical vapor deposition technology to secondary grow n-type heavily doped GaN in the source and drain ohmic contact areas to form ohmic contacts. It is mainly used to manufacture high-performance electronic devices in the fields of high-voltage power switches and digital circuits.

[0003] AlGaN / GaN-based high electron mobility transistors (HEMTs) have attracted widespread attention due to their outstanding material properties, including a large bandgap, high critical breakdown field strength, high electron saturation drift velocity, and a two-dimensional electron gas (2DEG) with superior transport properties generated by strong spontaneous and piezoelectric polarization effects. They have unique advantages in the application of high-temperature, high-voltage, high-frequency, and high-power microwave electronic devices.

[0004] In the manufacturing process of GaN-based HEMT devices, the source-drain ohmic contact process is a key technology, directly impacting the device's frequency and power performance. In recent years, epitaxially growing n-type heavily doped GaN in the ohmic contact region to reduce ohmic contact resistivity and improve surface morphology has become a new international process. This process enables a non-alloy ohmic contact, significantly improves the ohmic contact surface and edge morphology, and allows for self-alignment of the source, drain, and gate. This epitaxial growth of n-type heavily doped GaN is typically achieved using molecular beam epitaxy (MBE), although metal-organic chemical vapor deposition (MOCVD) has also been used. The ohmic contact resistance achieved using this method primarily includes the contact resistance between the metal and the n-type heavily doped GaN, the bulk resistance of the n-type heavily doped GaN, and the contact resistance between the n-type heavily doped GaN and the GaN heterojunction sidewalls. The quality of the contact between the n-type heavily doped GaN and the GaN heterojunction sidewalls directly affects the contact resistance between the n-type heavily doped GaN and the GaN heterojunction sidewalls, which has the greatest impact on the overall ohmic contact. Figures 1a to 1c The following is a schematic diagram of the process of preparing heavily doped GaN materials by secondary epitaxial growth in the prior art. Figures 1a to 1c As shown, the patterned SiO2 layer is used as a mask to etch the exposed GaN channel layer 3 and barrier layer 4 to a depth below the GaN heterojunction interface. Figure 1b As shown in FIG, in actual operation, due to the problem of etching accuracy, the GaN heterojunction is easily over-etched. The side position of the GaN heterojunction is retracted a distance relative to the mask layer SiO2 layer above it, as shown in FIG. Figure 1cAs shown, during the secondary epitaxial growth of heavily doped GaN material, due to the existence of excessive etching, the side of the heavily doped GaN material has poor contact with the GaN heterojunction, resulting in a significant increase in the contact resistance between the n-type heavily doped GaN and the side wall of the GaN heterojunction.

[0005] Therefore, effectively reducing the contact resistance between n-type heavily doped GaN and the sidewall of the GaN heterojunction is of great significance to reducing the overall ohmic contact.

[0006] In summary, current existing technologies cannot effectively reduce the ohmic contact resistance of the source and drain regions. In addition, the device manufacturing process is complex, the process precision control is difficult, and the equipment is expensive, which cannot meet the requirements of market-oriented commodity production. Summary of the Invention

[0007] The purpose of the present invention is to provide a semiconductor device with simple process and low ohmic contact resistance and a method for preparing the semiconductor device, thereby reducing the contact resistance between n-type heavily doped GaN and the sidewall of the GaN heterojunction, reducing the difficulty of device manufacturing, and improving the repeatability and controllability of the device manufacturing process, so that the device can be better used in high-voltage power switches and digital circuits.

[0008] To achieve the above object, the present invention provides a method for preparing a semiconductor light-emitting device, comprising the following steps:

[0009] sequentially forming a GaN layer and a barrier layer on a substrate;

[0010] Spin-coating photoresist on the upper surface of the barrier layer and developing the source and drain ohmic contact regions to form a patterned photoresist layer;

[0011] Etching downward from the upper surface of the barrier layer exposed by the photoresist layer to below the heterojunction interface between the GaN layer and the barrier layer to form a first groove, and then performing annealing in a high-temperature annealing furnace;

[0012] Cleaning the patterned photoresist layer, and performing secondary epitaxial growth of an n-type heavily doped GaN material in the first groove, wherein the n-type heavily doped GaN material continues to grow out of the first groove to heal on the upper surface of the barrier layer;

[0013] patterning the n-type heavily doped GaN material on the barrier layer to expose an upper surface of the barrier layer;

[0014] A gate electrode in Schottky contact with the barrier layer is provided on the upper surface of the barrier layer, and a source electrode and a drain electrode are respectively provided on the n-type heavily doped GaN material.

[0015] As an optional technical solution, after patterning the n-type heavily doped GaN material, a passivation layer is deposited on the surface of the n-type heavily doped GaN material and the barrier layer, and the passivation layer is selectively etched to expose the barrier layer and the n-type heavily doped GaN material.

[0016] As an optional technical solution, the source electrode is formed on the n-type heavily doped GaN material and the passivation layer to form a source field plate, and the drain electrode is formed on the n-type heavily doped GaN material and the passivation layer to form a drain field plate.

[0017] As an optional technical solution, after patterning the n-type heavily doped GaN material, a portion of the n-type heavily doped GaN material is retained between the gate electrode and the source electrode and the drain electrode, and the passivation layer is an isolation material between the gate electrode and the n-type heavily doped GaN material.

[0018] As an optional technical solution, the n-type heavily doped GaN material is formed on the first groove and an upper surface of the barrier layer connected to the first groove.

[0019] As an optional technical solution, a horizontal distance from an edge position of the first groove to an edge position of the adjacent n-type heavily doped GaN material located on the barrier layer is 0-100 nm.

[0020] As an optional technical solution, the barrier layer is AlN / AlInN or AlN / AlGaN, and the n-type heavily doped GaN material on the patterned barrier layer to expose the upper surface of the barrier layer is first selectively etched by dry etching to expose the upper surface of the AlN layer of the barrier layer, and then wet etching the AlN layer until the AlInN layer or AlGaN layer is exposed.

[0021] As an optional technical solution, patterning the n-type heavily doped GaN material on the barrier layer to expose the upper surface of the barrier layer includes patterning the n-type heavily doped GaN material for a first time and patterning the n-type heavily doped GaN material for a second time; the first patterning of the n-type heavily doped GaN material to form a gate electrode contact area, forming the gate electrode in the gate electrode contact area; the second patterning of the n-type heavily doped GaN material to isolate the gate electrode from the n-type heavily doped GaN material in the source and drain contact area.

[0022] As an optional technical solution, after the first patterning of the n-type heavily doped GaN material, the n-type heavily doped GaN material has an inclined side surface, and both sides of the gate electrode are sloped.

[0023] In another aspect, the present invention provides a semiconductor device, which is prepared by any one of the above-mentioned preparation methods, comprising:

[0024] substrate;

[0025] A GaN layer and a barrier layer are sequentially formed on a substrate;

[0026] a first groove, wherein the first groove is formed by etching the GaN layer and the barrier layer, and a bottom surface of the first groove is located below a heterojunction interface between the GaN layer and the barrier layer;

[0027] n-type heavily doped GaN material, wherein the n-type heavily doped GaN material is formed on the first groove and an upper surface of the barrier layer connected to the first groove;

[0028] a gate electrode formed on the barrier layer;

[0029] A source electrode and a drain electrode are formed on the n-type heavily doped GaN material.

[0030] As an optional technical solution, the semiconductor device further includes a passivation layer, which is deposited on the surface of the n-type heavily doped GaN material. The passivation layer is an isolation material between the gate electrode and the n-type heavily doped GaN material.

[0031] As an optional technical solution, the semiconductor device retains a portion of the n-type heavily doped GaN material between the gate electrode and the source electrode and the drain electrode, and the passivation layer is an isolation material between the gate electrode and the n-type heavily doped GaN material.

[0032] As an optional technical solution, the source electrode is formed on the n-type heavily doped GaN material and the passivation layer to form a source field plate, and the drain electrode is formed on the n-type heavily doped GaN material and the passivation layer to form a drain field plate.

[0033] As an optional technical solution, a horizontal distance from an edge position of the first groove to an edge position of the adjacent n-type heavily doped GaN material located on the barrier layer is 0-100 nm.

[0034] In summary, the semiconductor device preparation method of the first embodiment of the present invention etches the GaN layer and the barrier layer heterojunction in the source-drain contact area to form a first groove T, then corrodes the photoresist layer, and then performs secondary epitaxy of the entire n-type heavily doped GaN material. The n-type heavily doped GaN material on the barrier layer is patterned by dry etching to expose the upper surface of the barrier layer, and then the electrode is produced. The semiconductor device preparation method of the present invention prevents the presence of the mask layer from causing poor contact between the n-type heavily doped GaN material and the sidewall of the GaN heterojunction during the secondary epitaxy of the n-type heavily doped GaN material. On the other hand, the secondary epitaxy of the n-type heavily doped GaN material on the entire wafer is beneficial to improving the problem of rough surface of the n-type heavily doped GaN material, reducing growth defects of the n-type heavily doped GaN material, improving the crystal quality of the n-type heavily doped GaN material, and further reducing the contact resistance between the n-type heavily doped GaN material and the metal.

[0035] The semiconductor device provided by the present invention includes a substrate, GaN and a barrier layer formed in sequence on the substrate, a first groove formed by etching the GaN layer and the barrier layer, and an n-type heavily doped GaN material formed on the first groove and the upper surface of the barrier layer connected to the first groove. The present invention improves the ohmic contact between the n-type heavily doped GaN material and the side wall of the GaN heterojunction by filling the first groove with the n-type heavily doped GaN material and extending it to the upper surface of the barrier layer, thereby reducing the contact resistance between the n-type heavily doped GaN material and the side wall of the GaN heterojunction.

[0036] On the other hand, the secondary epitaxial n-type heavily doped GaN material continues to grow laterally on the barrier layer after growing in the first groove, which is beneficial to improving the surface roughness problem of the n-type heavily doped GaN material and further reducing the contact resistance between the n-type heavily doped GaN material and the metal.

[0037] On the other hand, in the semiconductor device, because a passivation layer 10 is provided in this embodiment, on the one hand, the passivation layer 10 can serve as an isolation material between the gate electrode 9 and the n-type heavily doped GaN material 6; on the other hand, the passivation layer is etched in the source-drain contact region, exposing the n-type heavily doped GaN material 6 to form the source electrode contact region and the drain electrode contact region. Because of the presence of the passivation layer 10, the source electrode 7 is formed on the n-type heavily doped GaN material 6 and the passivation layer 10 to form a source field plate, and the drain electrode 8 is formed on the n-type heavily doped GaN material 6 and the passivation layer 10 to form a drain field plate. The semiconductor device of this third embodiment utilizes the provision of the passivation layer 10 to improve device performance and solve the current collapse and breakdown voltage problems of GaN-HEMT semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] Figure 1a-Figure 1c This is a schematic diagram of the process for preparing heavily doped GaN materials by secondary epitaxial growth in the prior art;

[0040] Figure 2a-2f 1 is a schematic structural diagram of an intermediate process and a final device in a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

[0041] Figure 3a-3d It is a structural schematic diagram of an intermediate process of a method for manufacturing a semiconductor device according to a second embodiment of the present invention;

[0042] Figure 4a-4c 1 is a schematic diagram of the intermediate process of the method for preparing a semiconductor device and the structure of the final device according to the third embodiment of the present invention;

[0043] Figure 5 It is a schematic structural diagram of a semiconductor device according to a fourth embodiment of the present invention.

[0044] Explanation of the accompanying drawings: 1. Substrate; 2. Buffer layer; 3. GaN layer; 4. Barrier layer; 41. AlN layer; 42. AlInN layer or AlGaN layer; 5. SiO2 layer; 6. n-type heavily doped GaN material; 7. Source electrode; 8. Drain electrode; 9. Gate electrode; 10. Passivation layer; T, first groove; d, horizontal distance from the edge of the second window region to the edge of the first window region; t, the thickness of the n-type heavily doped GaN material exceeds the thickness of the upper surface of the barrier layer. DETAILED DESCRIPTION

[0045] Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present invention. Rather, they are merely examples of devices consistent with certain aspects of the present invention, as detailed in the appended claims.

[0046] Example 1

[0047] Figure 2a-2f 1 is a schematic structural diagram of an intermediate process of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Figure 2f FIG. 1 is a schematic structural diagram of a semiconductor device according to a first embodiment of the present invention, Figure 2a-2fAs shown, a semiconductor device 100 according to a first embodiment of the present invention includes: a substrate 1, a buffer layer 2, a GaN layer 3 and a barrier layer 4, a first recess T, an n-type heavily doped GaN material 6, a source electrode 7, a drain electrode 8, and a gate electrode 9. The GaN layer 3 and the barrier layer 4 are sequentially formed on the substrate 1. Specifically, the GaN layer 3 and the barrier layer 4 are sequentially formed on the buffer layer 2, and the GaN layer 3 and the barrier layer 4 form a GaN heterojunction. The first recess T is formed by etching the GaN layer 3 and the barrier layer 4, and the bottom surface of the first recess T is located below the heterojunction interface between the GaN layer 3 and the barrier layer 4. The n-type heavily doped GaN material is formed on the first recess T and the upper surface of the barrier layer 4 connected to the first recess T. The gate electrode 9 is formed on the upper surface of the barrier layer 4. The source electrode 7 and the drain electrode 8 are formed on the n-type heavily doped GaN material 6. The present invention fills the first groove T with n-type heavily doped GaN material 6 and extends it to the upper surface of the barrier layer 4, thereby improving the ohmic contact between the n-type heavily doped GaN material 6 and the side wall of the GaN heterojunction and reducing the contact resistance between the n-type heavily doped GaN material 6 and the side wall of the GaN heterojunction.

[0048] On the other hand, after the secondary epitaxial n-type heavily doped GaN material 6 grows in the first groove T, it continues to grow laterally epitaxially on the barrier layer 4 until it is healed, which is beneficial to improving the problem of rough surface of the n-type heavily doped GaN material 6, improving the crystal quality of the n-type heavily doped GaN material 6, and further reducing the contact resistance between the n-type heavily doped GaN material 6 and the metal electrode.

[0049] Preferably, in the semiconductor device 100 of the first embodiment, the thickness of the n-type heavily doped GaN material 6 exceeds the upper surface of the barrier layer 4 , and the thickness t of the n-type heavily doped GaN material 6 exceeding the upper surface of the barrier layer 4 is 20-300 nm.

[0050] Preferably, in the semiconductor device 100 of embodiment one, the horizontal distance d from the edge position of the first groove T to the edge position of the adjacent n-type heavily doped GaN material 6 on the barrier layer 4 is between 0-100 nm, that is, the n-type heavily doped GaN material 6 undergoes secondary epitaxial growth in the first groove T, and after filling the first groove T, continues to grow epitaxially outside the first groove T, that is, continues to grow epitaxially laterally on the barrier layer 4 outside the first groove T, and the horizontal distance from the edge position of the extendedly grown n-type heavily doped GaN material 6 on the barrier layer to the first groove T is between 0-100 nm.

[0051] The method for manufacturing the semiconductor device 100 according to the first embodiment of the present invention includes the following steps:

[0052] like Figure 2aAs shown, a buffer layer 2, a GaN layer 3 and a barrier layer 4 are sequentially formed on a substrate 1, and the material used for the barrier layer 4 is AlGaN, InAlN or AlN;

[0053] like Figure 2b As shown, a photoresist is spin-coated on the upper surface of the barrier layer 4 and developed in the source-drain ohmic contact region to form a patterned photoresist layer 10;

[0054] like Figure 2c As shown, etching is performed downward from the upper surface of the barrier layer 4 exposed by the photoresist layer 10 to below the heterojunction interface between the GaN layer and the barrier layer to form a first groove T, and then annealing is performed in a high-temperature annealing furnace;

[0055] like Figure 2d As shown, the patterned photoresist layer 10 is cleaned, and a secondary epitaxial n-type heavily doped GaN material 6 is grown in the first groove T, wherein the n-type heavily doped GaN material 6 continues to grow out of the first groove T to heal on the upper surface of the barrier layer 4;

[0056] like Figure 2e As shown, the n-type heavily doped GaN material 6 on the barrier layer 4 is patterned to expose the upper surface of the barrier layer 4;

[0057] like Figure 2f As shown, a gate electrode 9 in Schottky contact with the barrier layer 4 is provided on the upper surface of the barrier layer 4 , and a source electrode 7 and a drain electrode 8 are provided on the n-type heavily doped GaN material 6 .

[0058] In the semiconductor device fabrication method of the first embodiment of the present invention, after etching the GaN layer and the barrier layer heterojunction in the source-drain contact region to form a first groove T, the photoresist layer 10 is etched away, and then a secondary epitaxial growth of the n-type heavily doped GaN material 6 is performed on the entire wafer. The n-type heavily doped GaN material 6 on the barrier layer 4 is patterned by dry etching to expose the upper surface of the barrier layer 4, and then the electrodes are fabricated. The semiconductor device fabrication method of the present invention, through the secondary epitaxial growth of the n-type heavily doped GaN material 6 on the entire wafer, prevents the presence of a mask layer from causing poor contact between the n-type heavily doped GaN material and the sidewalls of the GaN heterojunction during the secondary epitaxial growth of the n-type heavily doped GaN material. On the other hand, the secondary epitaxial growth of the n-type heavily doped GaN material 6 on the entire wafer is beneficial for improving the problem of surface roughness of the n-type heavily doped GaN material, reducing growth defects of the n-type heavily doped GaN material 6, improving the crystal quality of the n-type heavily doped GaN material 6, and further reducing the contact resistance between the n-type heavily doped GaN material and the metal.

[0059] Example 2

[0060] Figure 3a-3dIt is a structural schematic diagram of the intermediate process of the method for preparing a semiconductor device of Example 2 of the present invention. The method for preparing a semiconductor device of Example 2 of the present invention is roughly the same as the method for preparing a semiconductor device of Example 1 of the present invention, with the only difference being that patterning the n-type heavily doped GaN material 6 on the barrier layer 4 to expose the upper surface of the barrier layer 4 includes patterning the n-type heavily doped GaN material for the first time and patterning the n-type heavily doped GaN material for the second time.

[0061] like Figure 3a As shown, the first patterning of the n-type heavily doped GaN material to form the gate electrode contact region. Preferably, after the first patterning of the n-type heavily doped GaN material 6, the n-type heavily doped GaN material 6 has an inclined side surface. That is, the side surface of the gate electrode contact region formed by the first patterning of the n-type heavily doped GaN material has an inclined side edge. The cross-section of the gate electrode contact region is funnel-shaped, so the gate electrode 9 grown in this region has slopes on both sides. The inclined gate can effectively reduce the gate side drop spike electric field and improve the breakdown electric field strength of the device.

[0062] The semiconductor device manufacturing method of the second embodiment of the present invention reduces the difficulty of device manufacturing and improves the repeatability and controllability of the device manufacturing process by patterning the n-type heavily doped GaN material 6 twice and using the n-type heavily doped GaN material 6 as a template for the gate electrode 9.

[0063] Example 3

[0064] Figure 4a-4c Schematic diagram of the structure of the intermediate process of the method for preparing a semiconductor device according to the third embodiment of the present invention. The method for preparing a semiconductor device according to the third embodiment of the present invention is substantially the same as the method for preparing a semiconductor device according to the first and second embodiments of the present invention, except that: Figure 4a As shown, after patterning the n-type heavily doped GaN material 6 , a passivation layer 10 is deposited on the surfaces of the n-type heavily doped GaN material 6 and the barrier layer 4 .

[0065] like Figure 4b As shown, the passivation layer 10 is selectively etched to expose the barrier layer 4 and the n-type heavily doped GaN material 6 .

[0066] like Figure 4c As shown, the source electrode 7 is formed on the n-type heavily doped GaN material 6 and the passivation layer 10 to form a source field plate, and the drain electrode 8 is formed on the n-type heavily doped GaN material 6 and the passivation layer 10 to form a drain field plate.

[0067] In the semiconductor device of the third embodiment of the present invention, after patterning the n-type heavily doped GaN material 6, a portion of the n-type heavily doped GaN material 6 is retained between the gate electrode 9 and the source electrode 7 and the drain electrode 8. Because a passivation layer 10 is provided in this embodiment, on the one hand, the passivation layer 10 can serve as an isolation material between the gate electrode 9 and the n-type heavily doped GaN material 6; on the other hand, the passivation layer is etched in the source-drain contact region, exposing the n-type heavily doped GaN material 6 to form the source electrode contact region and the drain electrode contact region. Due to the presence of the passivation layer 10, the source electrode 7 is formed on the n-type heavily doped GaN material 6 and the passivation layer 10 to form a source field plate, and the drain electrode 8 is formed on the n-type heavily doped GaN material 6 and the passivation layer 10 to form a drain field plate. The semiconductor device of the third embodiment of the present invention utilizes the provision of the passivation layer 10 to improve device performance and solve the current collapse and breakdown suppression problems of GaN-HEMT semiconductor devices.

[0068] Example 4

[0069] The method for manufacturing the semiconductor device of the fourth embodiment of the present invention is substantially the same as the method for manufacturing the semiconductor device of the first, second and third embodiments of the present invention. Figure 5 For the sake of brevity, the following is a schematic diagram of the structure of a semiconductor device according to a fourth embodiment of the present invention. The only difference is that the barrier layer 4 is a stacked material of AlN / AlInN or AlN / AlGaN. The n-type heavily doped GaN material 6 is first selectively etched using dry etching to expose the upper surface of the AlN layer 41 of the barrier layer 4. The AlN layer is then wet-etched until the AlInN layer or AlGaN layer 42 is exposed. When a passivation layer 10 is present, after patterning the n-type heavily doped GaN material 6, the passivation layer 10 is then deposited. The passivation layer 10 is first selectively etched using dry etching, with the AlN layer 41 of the barrier layer 4 serving as an etch stop layer. The AlN layer is then wet-etched until the AlInN layer or AlGaN layer 42 is exposed.

[0070] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: The following steps are involved: sequentially forming a GaN layer and a barrier layer on a substrate; Spin-coating photoresist on the upper surface of the barrier layer and developing the source and drain ohmic contact regions to form a patterned photoresist layer; Etching downward from the upper surface of the barrier layer exposed by the photoresist layer to below the heterojunction interface between the GaN layer and the barrier layer to form a first groove, and then performing annealing in a high-temperature annealing furnace; Cleaning the patterned photoresist layer, and performing secondary epitaxial growth of an n-type heavily doped GaN material in the first groove, wherein the n-type heavily doped GaN material continues to grow outward of the first groove to heal on the upper surface of the barrier layer, and a thickness of the n-type heavily doped GaN material exceeding the thickness of the upper surface of the barrier layer is 20-300 nm; patterning the n-type heavily doped GaN material on the barrier layer to expose an upper surface of the barrier layer; A gate electrode in Schottky contact with the barrier layer is provided on the upper surface of the barrier layer, and a source electrode and a drain electrode are respectively provided on the n-type heavily doped GaN material.

2. The method for preparing a semiconductor device according to claim 1, wherein: After patterning the n-type heavily doped GaN material, a passivation layer is deposited on surfaces of the n-type heavily doped GaN material and the barrier layer, and the passivation layer is selectively etched to expose the barrier layer and the n-type heavily doped GaN material.

3. The method for preparing a semiconductor device according to claim 2, wherein: The source electrode is formed on the n-type heavily doped GaN material and the passivation layer to form a source field plate, and the drain electrode is formed on the n-type heavily doped GaN material and the passivation layer to form a drain field plate.

4. The method for preparing a semiconductor device according to claim 2, wherein: After the n-type heavily doped GaN material is patterned, a portion of the n-type heavily doped GaN material is retained between the gate electrode and the source electrode and the drain electrode. The passivation layer is an isolation material between the gate electrode and the n-type heavily doped GaN material.

5. The method for preparing a semiconductor device according to claim 1, wherein: The n-type heavily doped GaN material is formed on the first groove and an upper surface of the barrier layer connected to the first groove.

6. The method for preparing a semiconductor device according to claim 5, wherein: A horizontal distance from an edge of the first groove to an edge of the adjacent n-type heavily doped GaN material on the barrier layer is 0-100 nm.

7. The method for preparing a semiconductor device according to claim 1, wherein: The barrier layer is AlN / AlInN or AlN / AlGaN, and the n-type heavily doped GaN material on the patterned barrier layer to expose the upper surface of the barrier layer is first selectively etched by dry etching to expose the upper surface of the AlN layer of the barrier layer, and then wet etching the AlN layer until the AlInN layer or AlGaN layer is exposed.

8. The method for preparing a semiconductor device according to claim 1, wherein: The patterning of the n-type heavily doped GaN material on the barrier layer to expose the upper surface of the barrier layer includes a first patterning of the n-type heavily doped GaN material and a second patterning of the n-type heavily doped GaN material; the first patterning of the n-type heavily doped GaN material to form a gate electrode contact region, forming the gate electrode in the gate electrode contact region; the second patterning of the n-type heavily doped GaN material to isolate the gate electrode from the n-type heavily doped GaN material in the source and drain contact region.

9. The method for preparing a semiconductor device according to claim 8, wherein: After the first patterning of the n-type heavily doped GaN material, the n-type heavily doped GaN material has an inclined side surface, and both sides of the gate electrode are sloped.

10. A semiconductor device, characterized in that: Prepared by the preparation method according to any one of claims 1 to 9, comprising substrate; A GaN layer and a barrier layer are sequentially formed on a substrate; a first groove, wherein the first groove is formed by etching the GaN layer and the barrier layer, and a bottom surface of the first groove is located below a heterojunction interface between the GaN layer and the barrier layer; n-type heavily doped GaN material, the n-type heavily doped GaN material is formed on the first groove and the upper surface of the barrier layer connected to the first groove, and the thickness of the n-type heavily doped GaN material exceeds the thickness of the upper surface of the barrier layer by 20-300 nm; a gate electrode formed on the barrier layer; A source electrode and a drain electrode are formed on the n-type heavily doped GaN material.

11. The semiconductor device according to claim 10, wherein: The invention also includes a passivation layer, which is deposited on the surface of the n-type heavily doped GaN material. The passivation layer is an isolation material between the gate electrode and the n-type heavily doped GaN material.

12. The semiconductor device according to claim 11, wherein A portion of the n-type heavily doped GaN material is retained between the gate electrode and the source electrode and the drain electrode, and the passivation layer is an isolation material between the gate electrode and the n-type heavily doped GaN material.

13. The semiconductor device according to claim 11, wherein The source electrode is formed on the n-type heavily doped GaN material and the passivation layer to form a source field plate, and the drain electrode is formed on the n-type heavily doped GaN material and the passivation layer to form a drain field plate.

14. The semiconductor device according to claim 10, wherein A horizontal distance from an edge of the first groove to an edge of the adjacent n-type heavily doped GaN material on the barrier layer is 0-100 nm.

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