Vertical semiconductor structure with integrated sampling structure and method of fabrication thereof

Abstract

The application provides a vertical semiconductor structure with integrated sampling structure and a manufacturing method thereof. The vertical semiconductor structure with integrated sampling structure comprises a vertical semiconductor structure cell, a sampling cell, a control electrode, a first electrode, a second electrode and a sampling electrode. According to an embodiment of the application, firstly, the sampling electrode can sample the voltage difference between the first electrode and the second electrode in real time; a PN junction is formed between the first / two P-type diffusion regions and the second N-type base region of the sampling cell, and the PN junction forms a potential barrier for blocking the electron emission of the sampling electrode, so that the voltage signal of the sampling electrode is input to a protection circuit, and the protection circuit can safely and quickly detect whether the vertical semiconductor structure is in a desaturation state when judging that the vertical semiconductor structure cell is in an open state. Secondly, a sampling resistor is connected in series between the sampling electrode and the first electrode, and the positive voltage of the sampling electrode can increase the height of the potential barrier, so as to ensure the stable work of the sampling cell.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and particularly relates to a vertical semiconductor structure integrated with a sampling structure and a manufacturing method thereof. BACKGROUND

[0002] A vertical semiconductor structure, such as an IGBT (Insulated Gate Bipolar Transistor), is different from a planar semiconductor structure, and can effectively improve the carrier concentration, reduce the on-state voltage drop and improve the current density through a channel perpendicular to the substrate. At present, the vertical semiconductor structure has gradually become a dominant power device. The IGBT is a composite full-control voltage-driven power semiconductor device composed of a BJT (Bipolar Junction Transistor) and a MOS (Metal-Oxide-Semiconductor), and has the characteristics of high input impedance, small switching loss, high speed and small voltage drive power, and is widely used in power transmission, high-speed train traction, industrial driving, clean energy and many other fields.

[0003] The vertical semiconductor structure has the characteristics of high voltage and large current, and in the application process, the vertical semiconductor structure will face a short circuit situation, that is, the vertical semiconductor structure simultaneously bears high voltage and large current, and the device will be burned out in a microsecond level due to heating.

[0004] The current related short circuit protection schemes include a desaturation detection method and a Hall current sensor detection channel current and implementation protection. For example, the desaturation detection method of the IGBT directly samples the V CE voltage of the IGBT, and detects whether the IGBT is in a short circuit state by using the desaturation characteristics of the IGBT in the short circuit state; the Hall current sensor detects whether the IGBT is in a short circuit state by using the fact that the current of the IGBT in the short circuit state is far more than the normal working current of the IGBT.

[0005] The Hall current sensor has the disadvantages of high delay and large size; and the desaturation detection method needs a high-voltage diode and other protection measures to prevent high voltage from directly entering the drive, and the cost of the peripheral circuit is high. SUMMARY

[0006] The present application aims to provide a vertical semiconductor structure integrated with a sampling structure and a manufacturing method thereof to solve the problems in the related art.

[0007] To achieve the above-mentioned purpose, a vertical semiconductor structure integrated with a sampling structure is provided in the first aspect of the present application, comprising:

[0008] A vertical semiconductor structure cell, comprising: a first N-type base region, a P-type well region extending into the first N-type base region, a control region extending from the P-type well region into the first N-type base region, a P-type ohmic contact region and an N-type source region located on an upper portion of the P-type well region, the N-type source region being located on both sides of the P-type ohmic contact region, and a first N-type buffer layer located below the first N-type base region;

[0009] A sampling cell, comprising: a second N-type base region, a first P-type diffusion region and a second P-type diffusion region extending into the second N-type base region, an electronic channel being formed between the first P-type diffusion region and the second P-type diffusion region, an N-type ohmic contact region located on an upper portion of the electronic channel, and a second N-type buffer layer located below the second N-type base region;

[0010] A control electrode connected to the control region of the vertical semiconductor structure cell;

[0011] A first electrode connected to the P-type ohmic contact region and the N-type source region of the vertical semiconductor structure cell, and the first P-type diffusion region and the second P-type diffusion region of the sampling cell;

[0012] A second electrode connected to the first N-type buffer layer of the vertical semiconductor structure cell and the second N-type buffer layer of the sampling cell;

[0013] A sampling electrode connected to the N-type ohmic contact region of the sampling cell.

[0014] Optionally, the vertical semiconductor structure is an IGBT, and the first electrode is an emitter electrode; the IGBT cell further comprises: a first P-type collector region located below the first N-type buffer layer, and the sampling cell further comprises: a second P-type collector region located below the second N-type buffer layer; the second electrode is a collector electrode connected to the first P-type collector region of the IGBT semiconductor structure cell and the second P-type collector region of the sampling cell.

[0015] Optionally, the vertical semiconductor structure is a VDMOS, and the first electrode is a source electrode, and the second electrode is a drain electrode.

[0016] Optionally, the vertical semiconductor structure of the integrated sampling structure further comprises: a sampling resistor connected between the sampling electrode and the first electrode.

[0017] Optionally, the vertical semiconductor structure cell has a plurality of cells in parallel, and the sampling cell has a plurality of cells in parallel.

[0018] Optionally, the second N-type base region has a first diffusion barrier region and a second diffusion barrier region, the first diffusion barrier region and the second diffusion barrier region are respectively adjacent to the electron channel; the first P-type diffusion region is located on a side of the first diffusion barrier region away from the electron channel, and the second P-type diffusion region is located on a side of the second diffusion barrier region away from the electron channel.

[0019] Optionally, the first diffusion barrier region and the second diffusion barrier region comprise a conductive material region and an insulating material layer located on a sidewall of the conductive material region.

[0020] Optionally, the conductive material region is electrically connected to the first electrode.

[0021] Optionally, the first diffusion barrier region and the second diffusion barrier region comprise an insulating material region and an insulating material layer located on a sidewall of the insulating material region.

[0022] A second aspect of the present application provides a method for manufacturing a vertical semiconductor structure integrated with a sampling structure, comprising:

[0023] A semiconductor substrate is provided, the semiconductor substrate comprises an N-type base region, the N-type base region comprises a first N-type base region and a second N-type base region, the first N-type base region is used to form a vertical semiconductor structure unit cell, and the second N-type base region is used to form a sampling unit cell; a first trench is formed in the first N-type base region, and a control region is formed in the first trench;

[0024] A P-type well region is formed in the first N-type base region, the depth of the P-type well region into the first N-type base region is less than the depth of the first trench; a first P-type diffusion region and a second P-type diffusion region are formed in the second N-type base region, and an electron channel is formed between the first P-type diffusion region and the second P-type diffusion region;

[0025] A P-type ohmic contact region and an N-type source region are formed on an upper portion of the P-type well region, the N-type source region is located on both sides of the P-type ohmic contact region; an N-type ohmic contact region is formed on an upper portion of the electron channel;

[0026] A first N-type buffer layer is formed below the first N-type base region, and a second N-type buffer layer is formed below the second N-type base region;

[0027] A control electrode is formed on the control region; a first electrode is formed on the P-type ohmic contact region, the N-type source region, the first P-type diffusion region, and the second P-type diffusion region; a sampling electrode is formed on the N-type ohmic contact region; and a second electrode is formed on the first N-type buffer layer and the second N-type buffer layer.

[0028] Optionally, forming the N-type source region on the upper portion of the P-type well region and forming the N-type ohmic contact region on the upper portion of the electron channel are performed in the same process; and / or

[0029] Optionally, forming the first N-type buffer layer under the first N-type base region and forming the second N-type buffer layer under the second N-type base region are performed in the same process; and / or

[0030] Optionally, forming the control electrode on the control region, forming the first electrode on the P-type ohmic contact region, the N-type source region, the first P-type diffusion region and the second P-type diffusion region, and forming the sampling electrode on the N-type ohmic contact region are performed in the same process.

[0031] Optionally, the vertical semiconductor structure is an IGBT, and the first electrode is an emitter;

[0032] The manufacturing method further comprises: forming a first P-type collector region under the first N-type buffer layer, and simultaneously forming a second P-type collector region under the second N-type buffer layer.

[0033] The second electrode is a collector electrode connected to the first P-type collector region of the IGBT semiconductor structure unit cell and the second P-type collector region of the sampling unit cell.

[0034] Optionally, the vertical semiconductor structure is a VDMOS, the first electrode is a source electrode, and the second electrode is a drain electrode.

[0035] Optionally, before the steps of forming the first P-type diffusion region and the second P-type diffusion region in the second N-type base region, first diffusion barrier regions and second diffusion barrier regions are respectively formed in the second N-type base region, and the first diffusion barrier regions and the second diffusion barrier regions are respectively adjacent to the electron channel.

[0036] Optionally, forming the first diffusion barrier region and the second diffusion barrier region in the second N-type base region comprises: forming a second trench and a third trench in the second N-type base region, forming the first diffusion barrier region in the second trench, and forming the second diffusion barrier region in the third trench.

[0037] Optionally, forming the first trench in the first N-type base region and forming the second trench and the third trench in the second N-type base region are performed in the same process; forming the control region in the first trench, forming the first diffusion barrier region in the second trench, and forming the second diffusion barrier region in the third trench are performed in the same process.

[0038] Compared with the prior art, the present application has the following beneficial effects:

[0039] First, the sampling electrode can sample the voltage difference between the first electrode and the second electrode in real time; the first P-type diffusion region and the second N-type base region of the sampling cell form a PN junction, and the PN junction forms a potential barrier to block the electron emission of the sampling electrode, so that the voltage signal of the sampling electrode is input to the protection circuit instead of directly sampling the V CE First, the sampling electrode can sample the voltage difference between the first electrode and the second electrode in real time; the first P-type diffusion region and the second N-type base region of the sampling cell form a PN junction, and the PN junction forms a potential barrier to block the electron emission of the sampling electrode, so that the voltage signal of the sampling electrode is input to the protection circuit instead of directly sampling the V BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 is a cross-sectional structure schematic diagram of an IGBT of the integrated sampling structure of the first embodiment of the present application;

[0041] Figure 2 is a circuit diagram of the IGBT of the integrated sampling structure of Figure 1

[0042] Figure 3 is a curve diagram of the sampling current of the control experiment with the voltage difference between the emitter and the collector;

[0043] Figure 4 is a flow chart of the manufacturing method of the IGBT of the integrated sampling structure of Figure 1

[0044] Figures 5 to 8 is a flow chart of the manufacturing method of the IGBT of the integrated sampling structure of Figure 4 is a flow chart of the manufacturing method of the IGBT of the integrated sampling structure of

[0045] Figure 9 is a cross-sectional structure schematic diagram of an IGBT of the integrated sampling structure of the second embodiment of the present application;

[0046] Figure 10 is a cross-sectional structure schematic diagram of a VDMOS of the integrated sampling structure of the third embodiment of the present application. ​​

[0047] For the convenience of understanding the present application, all the reference signs appearing in the present application are listed as follows:

[0048] IGBT 1, 2 of integrated sampling structure IGBT cell 11

[0049] First N-type base region 110 P-type well region 111

[0050] Control region 112 P-type ohmic contact region 113

[0051] N-type source region 114 First N-type buffer layer 115

[0052] First P-type collector region 116 Sampling cell 12

[0053] Second N-type base region 120 First P-type diffusion region 121

[0054] Second P-type diffusion region 122 Electron channel 123

[0055] N-type ohmic contact region 124 Second N-type buffer layer 125

[0056] Second P-type collector region 126 Emitter 13

[0057] Collector 14 Sampling electrode 15

[0058] Semiconductor substrate 10 N-type base region 100

[0059] Interlayer insulating layer 16 First diffusion barrier region 127

[0060] Second diffusion barrier region 128 Source 17

[0061] Drain 18 VDMOS 3 of integrated sampling structure

[0062] VDMOS cell 19 DETAILED DESCRIPTION

[0063] In order to make the above objectives, features and advantages of the present application more apparent and comprehensible, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0064] Figure 1 is a schematic diagram of the cross-sectional structure of the IGBT of the integrated sampling structure according to the first embodiment of the present application.

[0065] Referring to Figure 1 , the IGBT 1 of the integrated sampling structure comprises:

[0066] The IGBT cell 11 comprises a first N-type base region 110, a P-type well region 111 extending into the first N-type base region 110, a control region 112 extending from the P-type well region 111 into the first N-type base region 110, a P-type ohmic contact region 113 and an N-type source region 114 located on the upper portion of the P-type well region 111, the N-type source region 114 being located on both sides of the P-type ohmic contact region 113, a first N-type buffer layer 115 located below the first N-type base region 110, and a first P-type collector region 116 located below the first N-type buffer layer 115;

[0067] The sampling cell 12 comprises a second N-type base region 120, a first P-type diffusion region 121 and a second P-type diffusion region 122 extending into the second N-type base region 120, an electron channel 123 formed between the first P-type diffusion region 121 and the second P-type diffusion region 122, an N-type ohmic contact region 124 located on the upper portion of the electron channel 123, a second N-type buffer layer 125 located below the second N-type base region 120, and a second P-type collector region 126 located below the second N-type buffer layer 125;

[0068] A control electrode (not shown) is connected to the control region 112 of the IGBT cell 11.

[0069] An emitter 13 is connected to the P-type ohmic contact region 113 and the N-type source region 114 of the IGBT cell 11, and the first P-type diffusion region 121 and the second P-type diffusion region 122 of the sampling cell 12.

[0070] A collector 14 is connected to the first P-type collector region 116 of the IGBT cell 11 and the second P-type collector region 126 of the sampling cell 12.

[0071] A sampling electrode 15 is connected to the N-type ohmic contact region 124 of the sampling cell 12.

[0072] In this embodiment, the control region 112 of the IGBT cell 11 can comprise a gate region and a gate insulating layer located on the sidewall of the gate region. The control electrode is a gate electrode connected to the gate region.

[0073] The first N-type base region 110 of the IGBT cell 11 and the second N-type base region 120 of the sampling cell 12 can be connected together. The first N-type buffer layer 115 of the IGBT cell 11 and the second N-type buffer layer 125 of the sampling cell 12 can be connected together. The first P-type collector region 116 of the IGBT cell 11 and the second P-type collector region 126 of the sampling cell 12 can be connected together.

[0074] IGBT cell 11, P-type ohmic contact region 113 and N-type source region 114, and first P-type diffusion region 121 and second P-type diffusion region 122 of sampling cell 12, and N-type ohmic contact region 124 can be provided with interlayer insulation layer 16, emitter 13, collector 14 and sampling electrode 15 are provided on interlayer insulation layer 16, and are respectively connected to P-type ohmic contact region 113 and N-type source region 114, and first P-type diffusion region 121 and second P-type diffusion region 122 through openings in interlayer insulation layer 16; first P-type collector region 116 and second P-type collector region 126; N-type ohmic contact region 124.

[0075] Figure 2 is Figure 1 a circuit diagram of an IGBT with integrated sampling structure. Referring to Figure 2 , the working process of the IGBT is as follows: after the drive circuit applies an opening voltage to the control region 112 of the IGBT cell 11, an electron channel is formed between the N-type source region 114 and the first N-type buffer layer 115 of the IGBT cell 11, and the voltage of the collector 14 is higher than that of the emitter 13, so that the IGBT cell 11 is turned on and is in an open state. The first P-type collector region 116 injects holes into the first N-type buffer layer 115 to conduct modulation to reduce the on-state voltage of the device.

[0076] The working process of the sampling structure is as follows: the potentials of the first P-type diffusion region 121 and the second P-type diffusion region 122 of the sampling cell 12 are the same as that of the emitter 13, the voltage of the collector 14 is higher than that of the emitter 13, and the electron channel 123 is turned on. Since PN junctions are formed between the first P-type diffusion region 121 and the second N-type base region 120, and between the second P-type diffusion region 122 and the second N-type base region 120, the PN junctions form a potential barrier to block the emission of electrons from the sampling electrode 15, so that the current of the electron channel 123 is small and the voltage signal of the sampling electrode 15 is small. The voltage signal of the sampling electrode 15 is input to the protection circuit, and when the protection circuit detects that the voltage signal is greater than a preset voltage and judges that the IGBT cell 11 has a conduction current, it is judged that the IGBT cell 11 is in a desaturation state, at which time the protection circuit can be disconnected.

[0077] In the working process of the above-mentioned sampling structure, referring to Figure 2As shown, the sampling resistor is connected in series between the sampling electrode 15 and the emitter 13, and the current signal can be converted into a voltage signal. When the voltage difference between the sampling electrode 15 and the emitter 13 is large, the voltage difference is positive, the potential barrier in the electron channel 123 is high, the electron emission is hindered, the current of the electron channel 123 is small, and thus the voltage difference between the sampling electrode 15 and the emitter 13 is reduced; after the voltage difference between the sampling electrode 15 and the emitter 13 is reduced, the potential barrier in the electron channel 123 is reduced, the current of the electron channel 123 is large, and thus the voltage difference between the sampling electrode 15 and the emitter 13 is increased, thus forming a negative feedback. Under the action of the above negative feedback, the current of the sampling electrode 15 will not be sharply increased, and the power of the sampling cell 12 will not be too large to burn out, thus the performance reliability of the IGBT integrated structure will not be reduced due to the introduction of the sampling cell 12.

[0078] To verify the above conclusion, the present application carries out a control experiment. Figure 3 The figure is a curve of the sampling current of the control experiment changing with the voltage difference between the emitter and the collector. Sample 1 is that the voltage difference between the sampling electrode 15 and the emitter 13 is always 0V, sample 2 is that the voltage difference between the sampling electrode 15 and the emitter 13 is always negative aV, sample 3 is that the voltage difference between the sampling electrode 15 and the emitter 13 is always negative bV, 0

[0079] Reference Figure 3 It can be seen that the sampling currents of samples 1, 2 and 3 will all be exponentially sharply increased. The sampling current of sample 4 will not be sharply increased.

[0080] Figure 3 In the embodiment, the bus voltage is the rated working voltage of the circuit.

[0081] In an optional solution, the IGBT 1 of the integrated sampling structure can include a sampling resistor, and the sampling resistor is connected between the sampling electrode 15 and the emitter 13. In other optional solutions, the sampling resistor can also be arranged in the peripheral circuit.

[0082] In the embodiment, the IGBT cell 11 and the sampling cell 12 each have one, in other words, the sampling cell 12 detects whether one IGBT cell 11 is in the desaturation state. In other embodiments, the IGBT cell 11 can have multiple in parallel, and the sampling cell 12 can also have multiple in parallel, so as to increase the sampling current when detecting whether the IGBT cell 11 is in the desaturation state, and improve the detection accuracy.

[0083] The embodiment of the present application also provides Figure 1 a manufacturing method of the IGBT with the integrated sampling structure. Figure 4 is a flowchart of the manufacturing method. Figures 5 to 8 isFigure 4 Flow chart corresponding to the intermediate structure.

[0084] First, referring to Figure 4 Step S1 and Figure 5 , a semiconductor substrate 10 is provided, which includes an N-type base region 100, the N-type base region 100 including a first N-type base region 110 for forming an IGBT cell 11 and a second N-type base region 120 for forming a sampling cell 12; a first trench is formed in the first N-type base region 110, and a control region 112 is formed in the first trench.

[0085] The first trench can be formed by dry etching. In this embodiment, the control region 112 can include a gate region and a gate insulating layer on the sidewall of the gate region. The gate insulating layer can be formed by thermal oxidation of the semiconductor substrate 10, and the material of the gate region can be doped polysilicon, which is formed by chemical vapor deposition.

[0086] Next, referring to Figure 4 Step S2 and Figure 6 , a P-type well region 111 is formed in the first N-type base region 110, the depth of the P-type well region 111 into the first N-type base region 110 being less than the depth of the first trench; a first P-type diffusion region 121 and a second P-type diffusion region 122 are formed in the second N-type base region 120, and an electron channel 123 is formed between the first P-type diffusion region 121 and the second P-type diffusion region 122.

[0087] The P-type well region 111, the first P-type diffusion region 121, and the second P-type diffusion region 122 can all be formed by ion implantation. In this embodiment, the depth of the P-type well region 111 is less than the depth of the first P-type diffusion region 121 and the second P-type diffusion region 122, so the first P-type diffusion region 121 and the second P-type diffusion region 122 can be formed first, and then the P-type well region 111 can be formed.

[0088] Then, referring to Figure 4 Step S3 and Figure 7 , a P-type ohmic contact region 113 and an N-type source region 114 are formed on the upper part of the P-type well region 111, the N-type source region 114 being located on both sides of the P-type ohmic contact region 113; and an N-type ohmic contact region 124 is formed on the upper part of the electron channel 123.

[0089] The P-type ohmic contact region 113, the N-type source region 114, and the N-type ohmic contact region 124 can all be formed by ion implantation. The P-type ohmic contact region 113 is heavily doped with P-type ions, and the N-type source region 114 and the N-type ohmic contact region 124 are heavily doped with N-type ions. Thus, the N-type source region 114 and the N-type ohmic contact region 124 can be formed in the same process.

[0090] Next, referring to Figure 4 of step S4 and Figure 8 , a first N-type buffer layer 115 and a first P-type collector region 116 are formed in sequence under the first N-type base region 110; a second N-type buffer layer 125 and a second P-type collector region 126 are formed in sequence under the second N-type base region 120.

[0091] The first N-type buffer layer 115, the second N-type buffer layer 125, the first P-type collector region 116 and the second P-type collector region 126 can be formed by ion implantation. The first N-type buffer layer 115 and the second N-type buffer layer 125 are heavily doped with N-type ions. The first P-type collector region 116 and the second P-type collector region 126 are heavily doped with P-type ions. Thus, the first N-type buffer layer 115 and the second N-type buffer layer 125 can be formed in the same process. The first P-type collector region 116 and the second P-type collector region 126 can be formed in the same process.

[0092] After that, referring to Figure 4 of step S5 and Figure 1 , a control electrode is formed on the control region 112; an emitter 13 is formed on the P-type ohmic contact region 113, the N-type source region 114, the first P-type diffusion region 121 and the second P-type diffusion region 122; a sampling electrode 15 is formed on the N-type ohmic contact region 124; a collector 14 is formed on the first P-type collector region 116 and the second P-type collector region 126.

[0093] Figure 1 On the cross section shown in , the emitter 13 is shown, and the control electrode can be disposed on other cross sections. In other words, the disposition position of the control electrode can be staggered with the disposition position of the emitter 13.

[0094] The control region 112, the P-type ohmic contact region 113 and the N-type source region 114 of the IGBT cell 11, and the first P-type diffusion region 121 and the second P-type diffusion region 122 of the sampling cell 12, the first P-type diffusion region 121, the second P-type diffusion region 122 and the N-type ohmic contact region 124 can be provided with an interlayer insulating layer 16. The interlayer insulating layer 16 has a plurality of openings exposing the areas to be electrically connected.

[0095] The materials of the control electrode, the emitter 13, the collector 14 and the sampling electrode 15 can be metal, such as copper or aluminum. The control electrode, the emitter 13 and the sampling electrode 15 are made on the same side of the semiconductor substrate 10, and thus can be formed in the same process.

[0096] The emitter 13, the collector 14 and the sampling electrode 15 are disposed on the interlayer insulating layer 16

[0097] Figure 9is a cross-sectional structural schematic diagram of an IGBT of an integrated sampling structure of a second embodiment of the present application. Referring to Figure 9 The integrated sampling structure IGBT 2 is substantially the same as the integrated sampling structure IGBT 1 in Figure 1 The difference is that the second N-type base region 120 has a first diffusion barrier region 127 and a second diffusion barrier region 128, which are respectively adjacent to the electron channel 123; the first P-type diffusion region 121 is located on a side of the first diffusion barrier region 127 away from the electron channel 123, and the second P-type diffusion region 122 is located on a side of the second diffusion barrier region 128 away from the electron channel 123.

[0098] The first diffusion barrier region 127 and the second diffusion barrier region 128 can prevent the first P-type diffusion region 121 and the second P-type diffusion region 122 from closing the electron channel 123.

[0099] In this embodiment, the first diffusion barrier region 127 and the second diffusion barrier region 128 can include a conductive material region and an insulating material layer located on the sidewall of the conductive material region.

[0100] Correspondingly, the manufacturing method of the integrated sampling structure IGBT 2 is substantially the same as the manufacturing method of the integrated sampling structure IGBT 1 in Figure 4 The difference is that in step S2, before forming the first P-type diffusion region 121 and the second P-type diffusion region 122 in the second N-type base region 120, the first diffusion barrier region 127 and the second diffusion barrier region 128 are respectively formed in the second N-type base region 120, and the first diffusion barrier region 127 and the second diffusion barrier region 128 are respectively adjacent to the electron channel 123. Specifically, it can include forming a second trench and a third trench in the second N-type base region 120, forming the first diffusion barrier region 127 in the second trench, and forming the second diffusion barrier region 128 in the third trench.

[0101] The second trench and the third trench can be opened in the same process as the first trench in step S1. Filling conductive material in the first trench, the second trench and the third trench is performed in the same process.

[0102] The first diffusion barrier region 127 and the second diffusion barrier region 128 can be connected to a fixed potential, and the above-mentioned fixed potential cannot be too large to prevent breakdown of the interlayer insulating layer 16. For example, the first diffusion barrier region 127 and the second diffusion barrier region 128 are both connected to the emitter 13.

[0103] In other embodiments, the first diffusion barrier region 127 and the second diffusion barrier region 128 can also include an insulating material region and an insulating material layer located on the sidewall of the insulating material region.

[0104] Figure 10is a cross-sectional structural schematic diagram of a VDMOS of the integrated sampling structure of the third embodiment of the present application. Referring to Figure 10 , the integrated sampling structure VDMOS 3 is substantially the same as the integrated sampling structure IGBT 1, 2 in Figure 1 , Figure 9 , the only difference is that the first P-type collector region 116 and the second P-type collector region 126 are omitted; the emitter 13 is replaced by the source 17, the collector 14 is replaced by the drain 18, and the drain 18 is connected to the first N-type buffer layer 115 and the second N-type buffer layer 125. In addition, the IGBT cell 11 is a VDMOS cell 19.

[0105] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the protection scope of the present application should be limited by the scope defined by the claims.

Claims

1. An integrated sampling structure vertical semiconductor structure, characterized by, The vertical semiconductor structure cell comprises a first N-type base region, a P-type well region extending into the first N-type base region, a control region extending from the P-type well region into the first N-type base region, a P-type ohmic contact region and an N-type source region located on the upper part of the P-type well region, the N-type source region being located on both sides of the P-type ohmic contact region, and a first N-type buffer layer located below the first N-type base region; The sampling cell comprises a second N-type base region, a first P-type diffusion region and a second P-type diffusion region extending into the second N-type base region, an electronic channel being formed between the first P-type diffusion region and the second P-type diffusion region, an N-type ohmic contact region located on the upper part of the electronic channel, and a second N-type buffer layer located below the second N-type base region, the upper surfaces of the first P-type diffusion region, the second P-type diffusion region and the second N-type base region being flush with each other; A control electrode is connected to the control region of the vertical semiconductor structure cell; A first electrode is connected to the P-type ohmic contact region and the N-type source region of the vertical semiconductor structure cell, and the first P-type diffusion region and the second P-type diffusion region of the sampling cell; A second electrode is connected to the first N-type buffer layer of the vertical semiconductor structure cell and the second N-type buffer layer of the sampling cell; A sampling electrode is connected to the N-type ohmic contact region of the sampling cell; A sampling resistor is connected between the sampling electrode and the first electrode; The second N-type base region has a first diffusion barrier region and a second diffusion barrier region, the first diffusion barrier region and the second diffusion barrier region being adjacent to the electronic channel respectively, the first P-type diffusion region being located on the side of the first diffusion barrier region away from the electronic channel, and the second P-type diffusion region being located on the side of the second diffusion barrier region away from the electronic channel. The vertical semiconductor structure is an IGBT, and the first electrode is an emitter; 2. The integrated sampling structure vertical semiconductor structure of claim 1, wherein, The vertical semiconductor structure cell further comprises a first P-type collector region located below the first N-type buffer layer, and the sampling cell further comprises a second P-type collector region located below the second N-type buffer layer; the second electrode is a collector electrode connected to the first P-type collector region of the vertical semiconductor structure cell and the second P-type collector region of the sampling cell. The vertical semiconductor structure is a VDMOS, the first electrode is a source electrode, and the second electrode is a drain electrode.

3. The integrated sampling structure vertical semiconductor structure of claim 1, wherein, The vertical semiconductor structure cell has a plurality of parallel cells, and the sampling cell has a plurality of parallel cells.

4. The integrated sampling structure vertical semiconductor structure of claim 1, wherein, The first diffusion barrier region and the second diffusion barrier region comprise a conductive material region and an insulating material layer located on the sidewall of the conductive material region.

5. The integrated sampling structure vertical semiconductor structure of claim 1, wherein, The conductive material region is electrically connected to the first electrode.

6. The integrated sampling structure vertical semiconductor structure of claim 5, wherein, The first diffusion barrier region and the second diffusion barrier region comprise an insulating material region and an insulating material layer located on the sidewall of the insulating material region.

7. The integrated sampling-structure vertical semiconductor structure of claim 1, wherein A method for manufacturing the vertical semiconductor structure of the integrated sampling structure according to claim 1, the manufacturing method comprising:

8. A method of fabricating an integrated sampling vertical semiconductor structure, comprising: ​ A semiconductor substrate is provided, which includes an N-type base region, the N-type base region including a first N-type base region for forming a vertical semiconductor structure cell and a second N-type base region for forming a sampling cell; a first trench is formed in the first N-type base region, and a control region is formed in the first trench; A P-type well region is formed in the first N-type base region, the P-type well region extending into the first N-type base region by a depth less than a depth of the first trench; a first P-type diffusion region and a second P-type diffusion region are formed in the second N-type base region, and an electron channel is formed between the first P-type diffusion region and the second P-type diffusion region; A P-type ohmic contact region and an N-type source region are formed on an upper portion of the P-type well region, and the N-type source region is located on both sides of the P-type ohmic contact region; and an N-type ohmic contact region is formed on an upper portion of the electron channel; A first N-type buffer layer is formed below the first N-type base region, and a second N-type buffer layer is formed below the second N-type base region; A control electrode is formed on the control region, a first electrode is formed on the P-type ohmic contact region, the N-type source region, the first P-type diffusion region, and the second P-type diffusion region, and a sampling electrode is formed on the N-type ohmic contact region; and a second electrode is formed on the first N-type buffer layer and the second N-type buffer layer.

9. The method of producing an integrated sampling structure vertical semiconductor structure according to claim 8, wherein The forming of the N-type source region on the upper portion of the P-type well region and the forming of the N-type ohmic contact region on the upper portion of the electron channel are performed in the same process; and / or The forming of the first N-type buffer layer below the first N-type base region and the forming of the second N-type buffer layer below the second N-type base region are performed in the same process; and / or The forming of the control electrode on the control region, the forming of the first electrode on the P-type ohmic contact region, the N-type source region, the first P-type diffusion region, and the second P-type diffusion region, and the forming of the sampling electrode on the N-type ohmic contact region are performed in the same process.

10. The method of fabricating an integrated sampling structure vertical semiconductor structure of claim 8, wherein, The vertical semiconductor structure is an IGBT, and the first electrode is an emitter; The manufacturing method further includes forming a first P-type collector region below the first N-type buffer layer and simultaneously forming a second P-type collector region below the second N-type buffer layer; The second electrode is a collector electrode connected to the first P-type collector region of the vertical semiconductor structure cell and the second P-type collector region of the sampling cell.

11. The method of fabricating an integrated sampling vertical semiconductor structure of claim 8, wherein, The vertical semiconductor structure is a VDMOS, the first electrode is a source electrode, and the second electrode is a drain electrode.

12. The method of fabricating an integrated sampling structure vertical semiconductor structure of claim 8, wherein, Before the step of forming the first P-type diffusion region and the second P-type diffusion region in the second N-type base region, a first diffusion barrier region and a second diffusion barrier region are respectively formed in the second N-type base region, and the first diffusion barrier region and the second diffusion barrier region are respectively adjacent to the electron channel.

13. The method of fabricating an integrated sampling vertical semiconductor structure of claim 12, wherein, The forming of the first diffusion barrier region and the second diffusion barrier region in the second N-type base region includes forming a second trench and a third trench in the second N-type base region, forming the first diffusion barrier region in the second trench, and forming the second diffusion barrier region in the third trench.

14. The method of fabricating an integrated sampling structure vertical semiconductor structure of claim 13, wherein, The first trench is formed in the first N-type base region, and the second trench and the third trench are formed in the second N-type base region in the same process; the control region is formed in the first trench, the first diffusion barrier region is formed in the second trench, and the second diffusion barrier region is formed in the third trench in the same process.

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