Gate drive circuit, manufacturing method, and display device

Abstract

The present disclosure provides a gate drive circuit and manufacturing method for a display device, belonging to the field of display technology. This circuit addresses the problem of metal oxide thin-film transistors in existing gate drive circuits experiencing a significant negative shift in threshold voltage under NBTIS stress, resulting in leakage. The gate drive circuit includes multiple shift registers, each comprising a plurality of first metal oxide thin-film transistors (MOSTs), each having a negative gate-source voltage difference when operating. The first MOSTs include a substrate and a first metal oxide layer located on the substrate.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a gate drive circuit and a manufacturing method thereof, and a display device. Background Art

[0002] Due to its higher mobility, metal oxide thin-film transistors have gradually increased their share in the high-end display market. Metal oxide technology is also considered the most likely way to replace the existing low-temperature polysilicon technology.

[0003] However, metal oxide thin-film transistors (MOSTs) are light-sensitive and exhibit very poor negative bias temperature illumination stress (NBTIS) characteristics. Especially in gate drive circuits, MOSTs can experience a significant negative shift in threshold voltage under NBTIS stress, leading to leakage. Furthermore, the impact of NBTIS becomes more severe as mobility increases. Summary of the Invention

[0004] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provide a gate drive circuit and a display device.

[0005] In a first aspect, an embodiment of the present disclosure provides a gate drive circuit, which includes: a plurality of cascaded shift registers; the shift register includes: a plurality of first metal oxide thin film transistors; the gate-source voltage difference of the first metal oxide thin film transistors in a working state is a negative value; the first metal oxide thin film transistor includes: a substrate and a first metal oxide layer located on the substrate.

[0006] Optionally, the shift register further comprises: a plurality of second metal oxide thin film transistors; the gate-source voltage difference of the second metal oxide thin film transistors in a working state is a positive value;

[0007] The second metal oxide thin film transistor includes: a substrate, a second metal oxide layer located on the substrate, and a third metal oxide layer located on a side of the second metal oxide layer close to the substrate; the mobility of the second metal oxide layer is less than a preset value, and the mobility of the third metal oxide layer is greater than a preset value;

[0008] The first metal oxide thin film transistor further includes: a first gate and a second gate located on a side of the first metal oxide layer close to the substrate and a side away from the substrate, respectively;

[0009] The orthographic projections of the first gate and the second gate on the substrate at least partially overlap with the orthographic projection of the first metal oxide layer on the substrate.

[0010] Optionally, the second metal oxide thin film transistor further comprises: a third gate located on a side of the third metal oxide layer close to the substrate, and a fourth gate located on a side of the second metal oxide layer away from the substrate;

[0011] The orthographic projection of the third gate on the substrate at least partially overlaps with the orthographic projections of the second metal oxide layer and the third metal oxide layer on the substrate;

[0012] An orthographic projection of the fourth gate on the substrate at least partially overlaps with orthographic projections of the second metal oxide layer and the third metal oxide layer on the substrate.

[0013] Optionally, the second metal oxide thin film transistor further comprises: a fourth metal oxide layer located on a side of the third metal oxide layer close to the substrate; the mobility of the fourth metal oxide layer is 2 cm 2 / Vs to 10cm 2 / Vs.

[0014] Optionally, the metal elements in the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer include at least one of indium, gallium, zinc, and tin.

[0015] Optionally, the third metal oxide layer is doped with rare earth elements.

[0016] Optionally, the rare earth element includes at least one of tantalum, niobium, neodymium and zirconium.

[0017] Optionally, the first metal oxide layer and the second metal oxide layer are provided in the same layer.

[0018] Optionally, the first gate and the third gate are provided in the same layer;

[0019] The second gate and the fourth gate are arranged in the same layer.

[0020] Optionally, the first metal oxide thin film transistor further includes: a first source electrode and a first drain electrode located on a side of the second gate away from the substrate;

[0021] The first source electrode and the first drain electrode are electrically connected to two ends of the first metal oxide layer respectively.

[0022] Optionally, the second metal oxide thin film transistor further includes: a second source electrode and a second drain electrode located on a side of the fourth gate away from the substrate;

[0023] The second source electrode and the second drain electrode are electrically connected to two ends of the second metal oxide layer respectively.

[0024] Optionally, the first source, the first drain, the second source and the second drain are arranged in the same layer.

[0025] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing a gate driving circuit, characterized in that the gate driving circuit comprises: a plurality of shift registers formed in cascade;

[0026] Forming the shift register includes:

[0027] Provide a base;

[0028] A first metal oxide thin film transistor is formed on a substrate, wherein the first metal oxide thin film transistor includes a first metal oxide layer; and a gate-source voltage difference of the first metal oxide thin film transistor is a negative value in a working state.

[0029] Optionally, the shift register further comprises: forming a plurality of second metal oxide thin film transistors; the gate-source voltage difference of the second metal oxide thin film transistors in a working state is a positive value;

[0030] The second metal oxide thin film transistor includes: a substrate, a second metal oxide layer located on the substrate, and a third metal oxide layer located on a side of the second metal oxide layer close to the substrate; the mobility of the second metal oxide layer is less than a preset value, and the mobility of the third metal oxide layer is greater than a preset value;

[0031] The first metal oxide thin film transistor further includes: a first gate and a second gate located on a side of the first metal oxide layer close to the substrate and a side away from the substrate, respectively;

[0032] The orthographic projections of the first gate and the second gate on the substrate at least partially overlap with the orthographic projection of the first metal oxide layer on the substrate.

[0033] In a third aspect, an embodiment of the present disclosure provides a display device, comprising the gate driving circuit provided above. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Schematic diagram of the structure of an exemplary gate drive circuit.

[0035] Figure 2 Schematic diagram of a circuit structure of an exemplary shift register.

[0036] Figure 3 for Figure 2 The timing diagram of the shift register shown.

[0037] Figure 4 A schematic diagram of the cross-sectional structure of some thin film transistors in the gate drive circuit provided in an embodiment of the present disclosure.

[0038] Figure 5 A schematic diagram of the layout of the gate drive circuit provided in an embodiment of the present disclosure.

[0039] Figure 6 Schematic diagram of the fabrication of some thin film transistors of the gate drive circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0041] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0042] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of the poles is called the first pole, the other pole is called the second pole, and the gate is called the control pole. In addition, transistors can be divided into N-type and P-type according to the characteristics of the transistor. The following embodiments are explained with N-type transistors. When an N-type transistor is used, the first pole is the source of the N-type transistor, and the second pole is the drain of the N-type transistor. When the gate input is a high level, the source and drain are turned on, and the P-type transistor is the opposite. It can be imagined that the use of P-type transistors is something that a person skilled in the art can easily think of without creative work, and therefore it is also within the scope of protection of the embodiments of the present disclosure. In the embodiment of the present disclosure, when the transistor used is an N-type transistor, the first level signal is an operating level signal, that is, a high level signal, and the second level signal is a non-operating level signal, that is, a low level signal; the corresponding first level signal terminal is a high level signal terminal, and the second level signal terminal is a low level signal terminal. The first power signal is a high level power signal, and the second power signal is a low level power signal; the corresponding first power signal terminal is a high level power signal terminal, and the second power signal terminal is a low level power signal.

[0043] Typically, a display panel includes a plurality of gate lines and a plurality of data lines, and the gate lines and the data lines are arranged to cross to define a plurality of pixel areas, each of which is provided with a pixel unit. In the example, the structure of the display panel is described by taking the extension direction of each gate line as the row direction and the extension direction of each data line as the column direction. When the display panel is driven to display, a gate scan signal can be written to the gate line row by row according to the image to be displayed, and a data voltage signal can be written to each data line at the same time, so that the pixel units in the display panel are illuminated row by row. In the related art, the gate drive circuit can be integrated into the gate drive chip and the source drive circuit can be integrated into the source drive chip. In order to reduce the number of chips and achieve a narrow frame or no frame, a technology for integrating the gate drive circuit on an array substrate (Gate On Array; GOA) is provided. In the related art, the gate drive circuit includes a plurality of shift registers integrated on the array substrate and cascaded, each shift register being connected to a gate line in a one-to-one correspondence, for providing a gate scan signal to the gate line connected thereto.

[0044] Figure 1 is a schematic structural diagram of an exemplary gate drive circuit, such as Figure 1As shown, the gate drive circuit includes multiple cascaded shift registers; each shift register can be labeled GOA1, GOA2, GOA3, ..., GOAn. The input signal of the shift register at this stage can be the output signal of the shift register at the previous stage. After registering the gate drive signal, it is output to the corresponding gate line according to a specific timing sequence to provide a gate scanning signal. The following will be described in detail in conjunction with the specific shift register circuit structure.

[0045] Figure 2 Schematic diagram of a circuit structure of an exemplary shift register, such as Figure 2 As shown, the shift register includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first storage capacitor C1 and a second storage capacitor C2.

[0046] The gate of the first transistor T1 is connected to the first clock signal terminal CK, the source is connected to the signal input terminal GI, and the drain is connected to the first node N1; wherein the first node N1 is the connection point of the drain of the first transistor T1, the gate of the second transistor T2, the drain of the seventh transistor T7, the gate of the fifth transistor T5, and one end of the second storage capacitor C2.

[0047] The gate of the second transistor T2 is connected to the first node, the source is connected to the first clock signal terminal CK, and the drain is connected to the second node N2; the second node N2 is the connection point of the drain of the second transistor T2, the drain of the third transistor T3, the gate of the sixth transistor T6, and the source of the eighth transistor T8.

[0048] The third transistor T3 has a gate connected to the first clock signal terminal CK, a source connected to the first power signal terminal VH, and a drain connected to the second node N2.

[0049] The gate of the sixth transistor T6 is connected to the second node, the source is connected to the low-level power signal terminal VL, and the drain is connected to the third node N3; the third node N3 is the connection point between the drain of the sixth transistor T6 and the source of the seventh transistor T7.

[0050] The seventh transistor T7 has a gate connected to the second clock signal terminal CB, a source connected to the third node N3, and a drain connected to the first node N1.

[0051] The gate of the eighth transistor T8 is connected to the high level signal terminal VGH, the source is connected to the second node, and the drain is connected to the fourth node N4; the fourth node N4 is the connection point of the gate of the fourth transistor T4, the drain of the eighth transistor T8, and one end of the first storage capacitor C1.

[0052] The fourth transistor T4 has a gate connected to the fourth node N4 , a source connected to the low-level signal terminal VGL, and a drain connected to the signal output terminal GOUT.

[0053] The fifth transistor T5 has a gate connected to the first node N1 , a source connected to the second clock signal terminal CB, and a drain connected to the signal output terminal GOUT.

[0054] One end of the first storage capacitor C1 is connected to the fourth node N4 , and the other end is connected to the low-level signal terminal VGL.

[0055] One end of the second storage capacitor C2 is connected to the first node N1 , and the other end is connected to the drain of the fifth transistor T5 .

[0056] Figure 3 for Figure 2 The timing diagram of the shift register is shown in FIG. 1 . The working principle of the shift register will be further described in detail below in conjunction with the timing diagram.

[0057] In the first stage, the potential of the first node N1 is low, the potential of the second node N2 is low, the potential of the third node N3 is high, and the potential of the fourth node N4 is low.

[0058] In the second phase, the potential of the first node N1 is low, the potential of the second node N2 is high, the potential of the third node N3 is low, and the potential of the fourth node N4 is high.

[0059] In the third phase, the potential of the first node N1 is high, the potential of the second node N2 is low, the potential of the third node N3 is high, and the potential of the fourth node N4 is low.

[0060] In the second phase, the potential of the first node N1 is high, the potential of the second node N2 is low, the potential of the third node N3 is high, and the potential of the fourth node N4 is low.

[0061] The inventors of this application have discovered that the gate-source voltage difference VGS of each transistor in the working state is not exactly the same. For example, the threshold voltages of the second transistor T2 and the third transistor T3 will have a large negative drift, which is likely to cause leakage, and then the gate drive signal output by the gate drive circuit will affect the display effect of the display device.

[0062] In order to solve at least one of the above technical problems, the embodiments of the present disclosure provide a gate driving circuit and a display device. The gate driving circuit and the display device provided by the embodiments of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0063] In a first aspect, the embodiment of the present disclosure provides a gate drive circuit. The specific structure of the gate drive circuit provided by the embodiment of the present disclosure can be as follows: Figure 1 and Figure 2 As shown, the gate driving circuit includes: a plurality of cascaded shift registers. Figure 4 A schematic diagram of the cross-sectional structure of some thin film transistors in the gate drive circuit provided in an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the shift register in the gate drive circuit includes: a plurality of first metal oxide thin film transistors 10; the gate-source voltage difference of the first metal oxide thin film transistors 10 in the working state is negative; the first metal oxide thin film transistors 10 include: a substrate 101, a first metal oxide layer 102 located on the substrate 101; the mobility of the first metal oxide layer 102 is 2cm 2 / Vs to 10cm 2 / Vs; the first metal oxide thin film transistor 10 further includes: a first gate 103 and a second gate 104 respectively located on a side of the first metal oxide layer 102 close to the substrate 101 and a side away from the substrate 101; the orthographic projections of the first gate 103 and the second gate 104 on the substrate 101 at least partially overlap with the orthographic projection of the first metal oxide layer 102 on the substrate 101.

[0064] In the gate drive circuit, in order to improve the mobility of each transistor, each transistor is a metal oxide, wherein the gate-source voltage difference of some metal oxide transistors in the working state is positive, and the gate-source voltage difference of some metal oxide transistors in the working state is negative. For example, the gate-source voltage difference VGS of the first metal oxide thin film transistor 10 in the working state is negative (can be -20V to -30V), and the first metal oxide thin film transistor 10 can be specifically Figure 2 At least one of the second transistor T2 and the third transistor T3 in the shift register shown.

[0065] Optionally, the gate-source voltage difference between the second transistor T2 and the third transistor T3 in the working state is negative, which can reduce the large negative drift caused by the threshold voltage and leakage, affecting the gate drive signal output by the gate drive circuit, and further affecting the display effect of the display device.

[0066] It is understandable that, for example, when the first electrode of the third transistor T3 receives a fixed voltage high potential, when the gate is repeatedly changing, it is easy to cause a large negative drift. Therefore, there are transistors similar to the second transistor T2 and the third transistor T3 in the shift register unit, and the gate-source voltage difference in the working state of the transistor can also be negative. The substrate 101 can be made of a rigid material such as glass, which can improve the bearing capacity of the substrate 101 for other film layers thereon. Of course, the substrate 101 can also be made of a flexible material such as polyimide (PI), which can improve the overall bending and tensile resistance of the metal oxide thin film transistor, and avoid the stress generated during bending, stretching, and twisting that causes the substrate 101 to break, resulting in a short circuit. In practical applications, the material of the substrate 101 can be reasonably selected according to actual needs to ensure that the metal oxide thin film transistor has good performance. Other insulating film layers such as a buffer layer and a barrier layer can also be formed on the substrate 101, which can be formed using processes in related technologies and will not be described in detail here.

[0067] The first metal oxide layer 102 can be made of a metal oxide semiconductor material, and its mobility can be 7-8 cm 2 / Vs, which can ensure that the first metal oxide thin film transistor 10 has good mobility. It should be noted that the preset mobility value here can be set to 10cm 2 / Vs.

[0068] The first gate 103 and the second gate 104 can be a single-layer structure formed of at least one of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo), or chromium (Cr), or a multi-layer structure formed of an alloy such as an aluminum (Al)-neodymium (Nd) alloy or a molybdenum (Mo)-tungsten (W) alloy. A gate insulating layer can also be provided between the first gate 103 and the first metal oxide layer 102, and between the second gate and the first metal oxide layer 102, to prevent short circuits between the first metal oxide layer 102 and the first gate 103 and the second gate 104. Specifically, the gate insulating layer can be a single-layer or multi-layer structure composed of silicon nitride, silicon oxide, or silicon oxynitride.

[0069] In the gate drive circuit provided in this public embodiment, the first metal oxide thin film transistor 10 in a negative bias environment (which can be -20V to -30V) is made of a dual-gate structure, wherein the orthographic projections of the first gate 103 and the second gate 104 on the substrate 101 at least partially overlap with the orthographic projections of the first metal oxide layer 102 on the substrate 101. In this way, the first gate 103 and the second gate 104 can block the first metal oxide layer 102 to prevent light from directly irradiating the first metal oxide layer 102 and affecting the negative bias high-temperature light stability of the first metal oxide thin film transistor 10, thereby avoiding leakage, thereby improving the stability of the gate drive signal provided by the gate drive circuit and improving the display effect of the display device. At the same time, the first metal oxide semiconductor layer 102 can be made of a metal oxide material with relatively low mobility, for example, indium gallium zinc oxide (IGZO), which can reduce the degree to which the first metal oxide layer 102 is affected by the external environment, improve the negative bias high temperature light stability of the first metal oxide thin film transistor 10, thereby avoiding leakage, and further improving the stability of the gate drive signal provided by the gate drive circuit, thereby improving the display effect of the display device.

[0070] In some embodiments, as Figure 4 As shown, the shift register further includes: a plurality of second metal oxide thin film transistors 20; the gate-source voltage difference of the second metal oxide thin film transistors 20 in the working state is positive; the second metal oxide thin film transistors 20 include: a substrate 101, a second metal oxide layer 201 located on the substrate 101, and a third metal oxide layer 202 located on a side of the second metal oxide layer 201 close to the substrate 101; the mobility of the second metal oxide layer 201 is 2cm 2 / Vs to 10cm 2 / Vs, the mobility of the third metal oxide layer 202 is 40cm 2 / Vs to 60cm 2 / Vs.

[0071] The gate-source voltage difference VGS of the second metal oxide thin film transistor 20 in the working state is positive (can be 0V to 30V). The second metal oxide thin film transistor 20 can be specifically Figure 2 At least one of the other transistors in the shift register shown in FIG. 1 , except the second transistor T2 and the third transistor T3. For example, the fourth transistor T4 and the fifth transistor T5 at the signal output end of the gate drive circuit. The second metal oxide transistor 20 has a structure in which a second metal oxide layer 201 and a third metal oxide layer 202 are stacked, wherein the mobility of the second metal oxide layer 201 is 2 cm 2 / Vs to 10cm 2 / Vs, the mobility of the third metal oxide layer 202 is 40cm 2 / Vs to 60cm 2 / Vs, the second metal oxide layer 201 in the dual-layer structure has a relatively low mobility, while the third metal oxide layer 202 has a relatively high mobility. The combination of the two can improve the overall mobility of the second metal oxide thin-film transistor 20, ensuring the stability of the entire gate drive circuit, thereby improving the display effect of the display device. At the same time, the second metal oxide layer 201 with relatively low mobility can cover the third metal oxide layer 202 with relatively high mobility, preventing light from directly reaching the third metal oxide layer 202 with relatively high mobility, thereby ensuring that the second metal oxide thin-film transistor 20 has relatively high mobility.

[0072] In some embodiments, as Figure 4 As shown, the second metal oxide thin film transistor 20 further includes: a third gate 203 located on a side of the third metal oxide layer 202 close to the substrate 101, and a fourth gate 204 located on a side of the second metal oxide layer 201 away from the substrate 101; the orthographic projection of the third gate 203 on the substrate 101 at least partially overlaps with the orthographic projections of the second metal oxide layer 201 and the third metal oxide layer 202 on the substrate 101; the orthographic projection of the fourth gate 204 on the substrate 101 at least partially overlaps with the orthographic projections of the second metal oxide layer 201 and the third metal oxide layer 202 on the substrate 101.

[0073] The third gate 203 and the fourth gate 204 can shield the second metal oxide layer 201 and the third metal oxide layer 202, preventing light from directly irradiating the second metal oxide layer 201 and the third metal oxide layer 202, thereby affecting the stability of the second metal oxide thin film transistor 20, thereby avoiding leakage, and further improving the stability of the gate drive signal provided by the gate drive circuit, thereby improving the display effect of the display device.

[0074] In some embodiments, the second metal oxide thin film transistor 20 further includes: a fourth metal oxide layer 205 located on a side of the third metal oxide layer 201 close to the substrate 101; the mobility of the fourth metal oxide layer 205 is 2 cm 2 / Vs to 10cm 2 / Vs.

[0075] The mobility of the fourth metal oxide layer 205 is relatively small, specifically 2 cm 2 / Vs to 10cm 2 / Vs, which can, together with the second metal oxide 201 with lower mobility, cover the third metal oxide layer 202 with higher mobility, thereby preventing light from directly irradiating the third metal oxide layer 202 with higher mobility, thereby ensuring that the second metal oxide thin film transistor 20 has higher mobility. It will be understood that in the embodiment of the present disclosure, only three metal oxide layers are shown to constitute the second metal oxide thin film transistor 20. Of course, the number of metal oxide layers can also be other numbers, which are not listed here one by one.

[0076] In some embodiments, transistors in the gate driving circuit are all metal oxide transistors.

[0077] It can be understood that, in the gate drive circuit, the mobility of the transistor at the signal output end of the shift register is greater than the mobility of the transistor at the signal input end of the shift register. For example, the mobility of the fourth transistor and the fifth transistor is greater than the mobility of the second transistor and the third transistor. Of course, if the transistor has multiple oxide layers with different mobilities, the overall mobility of the fourth transistor and the fourth and fifth transistors is greater than the overall mobility of the second transistor and the third transistor. Of course, for the sake of convenience of description, it can be said that the mobility of the oxide layer with the maximum mobility in the fourth transistor and the fourth and fifth transistors is greater than the mobility of the oxide layer with the maximum mobility in the second transistor and the third transistor.

[0078] In some embodiments, the metal elements of the first metal oxide layer 102 , the second metal oxide layer 201 , and the third metal oxide layer 202 include at least one of indium, gallium, zinc, and tin.

[0079] The metal oxide in the first metal oxide layer 102, the second metal oxide layer 201, and the third metal oxide layer 202 can specifically be at least one of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc oxide (IZO), indium tin oxide (ITO), and indium tin zinc oxide (ITZO), all of which are metal oxides with high mobility to ensure that the first metal oxide thin film transistor 10 and the second metal oxide thin film transistor 20 have a high mobility as a whole.

[0080] It is understandable that the gate-source voltage difference of each transistor can be made positive or negative, or the mobility of each transistor can be controlled by various methods, for example: the active layer (such as oxide) of each transistor adopts different process methods, or has different metal element contents, or is doped with elements, etc.

[0081] In some embodiments, the mobility of the first metal oxide layer 102, the second metal oxide layer 201, and the third metal oxide layer 202 may be different, and various methods may be used, such as different processing methods, different metal element contents, or doping. For example, the crystallinity of the first metal oxide layer 102 is lower than that of the second metal oxide layer 201, and lower than that of the third metal oxide layer 202.

[0082] In some embodiments, at least one of the first metal oxide layer 102, the second metal oxide layer 201, and the third metal oxide layer 202 is doped with a rare earth element. For example, the third metal oxide layer 202 is doped with a rare earth element. This helps ensure high mobility of the third metal oxide layer 202.

[0083] Specifically, the rare earth element may be at least one of tantalum (Ta), niobium (Nb), neodymium (Nd), and zirconium (Zr). For example, indium gallium zinc oxide (IGZO) is used as the metal oxide, and tantalum (Ta) is used as the rare earth element. The electronegativity of tantalum (Ta) is 1.5, and the electronegativity of oxygen (O) is 3.5. According to the general electronegativity difference of 1.7, the ionic bond formed by two elements with an electronegativity difference greater than 1.7 has a stronger bond energy. Therefore, the ionic bond formed by tantalum (Ta) and oxygen (O) has a stronger bond energy. This can make the structure of the first metal oxide more stable, preventing it from being affected by factors such as light, the manufacturing process, and external water and oxygen. This ensures that the first metal oxide semiconductor layer 102 has a higher mobility, thereby improving the overall mobility of the metal oxide thin film transistor.

[0084] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing a gate driving circuit, characterized in that the gate driving circuit comprises: a plurality of shift registers formed in cascade;

[0085] Forming the shift register includes:

[0086] Provide a base;

[0087] A first metal oxide thin film transistor is formed on a substrate, wherein the first metal oxide thin film transistor includes a first metal oxide layer; and a gate-source voltage difference of the first metal oxide thin film transistor is a negative value in a working state.

[0088] In some embodiments, forming the first metal oxide thin film transistor further includes: a first gate and a second gate located on a side of the first metal oxide layer close to the substrate and away from the substrate, respectively;

[0089] The orthographic projections of the first gate and the second gate on the substrate at least partially overlap with the orthographic projection of the first metal oxide layer on the substrate.

[0090] In some embodiments, the shift register further comprises: a plurality of second metal oxide thin film transistors; the gate-source voltage difference of the second metal oxide thin film transistors in the working state is positive; in some embodiments, such as Figure 4 and Figure 5 As shown, the first metal oxide layer 102 and the second metal oxide layer 201 are provided in the same layer.

[0091] During the preparation process, the first metal oxide layer 102 and the second metal oxide layer 201 can be made of the same material and by the same process, which can reduce the number of process steps and save preparation costs.

[0092] In some embodiments, as Figure 4 As shown, the first gate 103 and the third gate 203 are arranged on the same layer; the second gate 104 and the fourth gate 204 are arranged on the same layer.

[0093] During the preparation process, the first gate 103 and the third gate 203 can be made of the same material and the same process, and the second gate 104 and the fourth gate 204 can be made of the same material and the same process, which can reduce process steps and save preparation costs.

[0094] In some embodiments, as Figure 4 As shown, the first metal oxide thin film transistor 10 further includes: a first source 105 and a first drain 106 located on the side of the second gate 104 away from the substrate; the first source 105 and the first drain 106 are electrically connected to two ends of the first metal oxide layer 102 respectively.

[0095] When a high level signal is input to the first gate 103 and the second gate 104 , the first metal oxide layer 102 is in a conductive state, so that the first source 105 and the first drain 106 are turned on to transmit a corresponding voltage signal.

[0096] In some embodiments, the second metal oxide thin film transistor 20 further includes a second source 206 and a second drain 207 located on the side of the fourth gate 204 away from the substrate 101 ; the second source 206 and the second drain 207 are electrically connected to two ends of the second metal oxide layer 201 , respectively.

[0097] When a high level signal is input to the third gate 203 and the fourth gate 204 , the second metal oxide layer 201 , the third metal oxide layer 202 , and the third metal oxide layer 205 are in a conductive state, so that the second source 206 and the second drain 207 are turned on to transmit the corresponding voltage signal.

[0098] In some embodiments, as Figure 4 and Figure 5The first source 105 , the first drain 106 , the second source 206 and the second drain 207 are arranged in the same layer.

[0099] During the preparation process, the first source electrode 105 , the first drain electrode 106 , the second source electrode 206 and the second drain electrode 207 can be made of the same material and the same process, which can reduce the number of process steps and save preparation costs.

[0100] In some embodiments, as Figure 4 and Figure 5 , Figure 6 As shown, the fabrication of some thin film transistors in the gate drive circuit can refer to Figure 6 , forming metal oxide layers with different mobilities in the first metal oxide thin film transistor and / or the second metal oxide thin film transistor in the shift register. For example: the oxide layer Oxide (such as IGZO) high mobility material (referred to as Oxide-high mobility) and the oxide layer Oxide low mobility material (referred to as Oxide-low mobility) are divided into two layers of mask process, so that a double layer of oxide layer Oxide (such as IGZO) can be achieved in some areas, and a single layer of oxide layer Oxide (such as IGZO) in some areas. It is understandable that Figure 6 Only the gate (Gate 1 and Gate 2) and oxide layer (Oxide-high migration Oxide-low migration) are shown. For other layers, reference can be made to the existing process for manufacturing transistors and will not be described in detail.

[0101] In some embodiments, as Figure 5 The first storage capacitor C1 is arranged along a first direction (e.g., the gate line direction), for example, perpendicular to the high-level signal terminal VGH; the second storage capacitor C2 is arranged along a second direction (e.g., the data line direction), for example, parallel to the second clock signal terminal CB. This helps save layout space in the shift register and avoids the large space occupied by the first storage capacitor C1 and the second storage capacitor C2 being parallel to the second clock signal terminal CB.

[0102] In some embodiments, as Figure 5 The first storage capacitor C1 is arranged along the first direction and located between adjacent shift registers in the first direction. This is beneficial for fully utilizing the space occupied by the cascade signal lines of adjacent shift registers, thereby optimizing the layout.

[0103] In some embodiments, as Figure 5 The second storage capacitor C2 is closer to the display area, and the first storage capacitor C1 is closer to the second clock signal terminal CB, and overlaps with the high-level signal terminal VGH; such a design is conducive to improving the voltage stabilizing effect of the first storage capacitor C1 on the fourth node N4.

[0104] In a third aspect, an embodiment of the present disclosure provides a display panel having a display area and a non-display area surrounding the display area, wherein the display panel includes a gate drive circuit as provided in any of the above embodiments and arranged in the non-display area. The display panel also includes: a plurality of pixel units arranged in the display area; each row of pixel units is electrically connected to the same gate line; the output end of each shift register of the gate drive circuit is electrically connected to the gate line connected to the corresponding row of pixel units. The gate drive circuit can provide a gate scan signal to the gate line connected thereto. Its implementation principle and beneficial effects are the same as those of the above-mentioned gate drive circuit, and will not be repeated here.

[0105] Fourthly, embodiments of the present disclosure provide a display device, comprising a display panel as provided in any of the aforementioned embodiments, and a gate drive circuit as provided in any of the aforementioned embodiments. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. The implementation principles and beneficial effects of the display device are the same as those of the display panel and gate drive circuit described above, and are not further described here.

[0106] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A gate drive circuit, characterized in that: The gate drive circuit includes: a plurality of cascaded shift registers; the shift registers include: a plurality of first metal oxide thin film transistors; the gate-source voltage difference of the first metal oxide thin film transistors is negative in a working state; the first metal oxide thin film transistors include: a substrate and a first metal oxide layer located on the substrate; The first metal oxide thin film transistor further includes: a first gate and a second gate located on a side of the first metal oxide layer close to the substrate and away from the substrate, respectively; the orthographic projections of the first gate and the second gate on the substrate at least partially overlap with the orthographic projection of the first metal oxide layer on the substrate; The shift register further includes: a plurality of second metal oxide thin film transistors; the gate-source voltage difference of the second metal oxide thin film transistors in the working state is a positive value; The second metal oxide thin film transistor includes: a substrate, a second metal oxide layer located on the substrate, and a third metal oxide layer located on a side of the second metal oxide layer close to the substrate; the mobility of the second metal oxide layer is less than a preset value, and the mobility of the third metal oxide layer is greater than a preset value.

2. The gate drive circuit according to claim 1, wherein: The second metal oxide thin film transistor further includes: a third gate located on a side of the third metal oxide layer close to the substrate, and a fourth gate located on a side of the second metal oxide layer away from the substrate; The orthographic projection of the third gate on the substrate at least partially overlaps with the orthographic projections of the second metal oxide layer and the third metal oxide layer on the substrate; An orthographic projection of the fourth gate on the substrate at least partially overlaps with orthographic projections of the second metal oxide layer and the third metal oxide layer on the substrate.

3. The gate drive circuit according to claim 1, wherein: The second metal oxide thin film transistor further includes: a fourth metal oxide layer located on a side of the third metal oxide layer close to the substrate; the mobility of the fourth metal oxide layer is 2cm 2 / Vs to 10cm 2 / Vs.

4. The gate drive circuit according to claim 1, wherein: The metal elements in the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer include at least one of indium, gallium, zinc, and tin.

5. The gate driving circuit according to claim 4, wherein: The third metal oxide layer is doped with rare earth elements.

6. The gate driving circuit according to claim 5, wherein: The rare earth elements include: the rare earth elements include: at least one of tantalum, niobium, neodymium, and zirconium.

7. The gate driving circuit according to claim 1, wherein: The first metal oxide layer and the second metal oxide layer are arranged in the same layer.

8. The gate driving circuit according to claim 2, wherein: The first gate and the third gate are arranged in the same layer; The second gate and the fourth gate are arranged in the same layer.

9. The gate driving circuit according to claim 2, wherein: The first metal oxide thin film transistor further includes: a first source electrode and a first drain electrode located on a side of the second gate away from the substrate; The first source electrode and the first drain electrode are electrically connected to two ends of the first metal oxide layer respectively.

10. The gate driving circuit according to claim 9, wherein: The second metal oxide thin film transistor further includes: a second source electrode and a second drain electrode located on a side of the fourth gate away from the substrate; The second source electrode and the second drain electrode are electrically connected to two ends of the second metal oxide layer respectively.

11. The gate driving circuit according to claim 10, wherein: The first source, the first drain, the second source and the second drain are arranged in the same layer.

12. A method for manufacturing a gate drive circuit, characterized in that: The gate driving circuit includes: a plurality of shift registers formed in cascade; Forming the shift register includes: Provide a base; forming a first metal oxide thin film transistor on a substrate, wherein the first metal oxide thin film transistor comprises a first metal oxide layer; and a gate-source voltage difference of the first metal oxide thin film transistor is a negative value in an operating state; The first metal oxide thin film transistor includes: a substrate, a first metal oxide layer located on the substrate; The first metal oxide thin film transistor further includes: a first gate and a second gate located on a side of the first metal oxide layer close to the substrate and away from the substrate, respectively; The orthographic projections of the first gate and the second gate on the substrate at least partially overlap with the orthographic projection of the first metal oxide layer on the substrate; The shift register further comprises: forming a plurality of second metal oxide thin film transistors; the gate-source voltage difference of the second metal oxide thin film transistors in the working state is a positive value; The second metal oxide thin film transistor includes: a substrate, a second metal oxide layer located on the substrate, and a third metal oxide layer located on a side of the second metal oxide layer close to the substrate; the mobility of the second metal oxide layer is less than a preset value, and the mobility of the third metal oxide layer is greater than a preset value.

13. A display device, characterized in that: The gate drive circuit comprises the gate drive circuit according to any one of claims 1 to 11.

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