A gallium nitride P-MOSFET transistor structure and its fabrication method

Abstract

This invention relates to the field of semiconductor device technology, specifically to a gallium nitride (GaN) P-MOSFET transistor structure and its manufacturing method. The invention employs a double heterojunction epitaxial structure for device fabrication, utilizing grooved gate technology to realize an enhancement-mode GaN P-MOSFET transistor while restoring the two-dimensional electron gas (2DEG) channel in the gate region. Based on this, an electrical connection is established between the 2DEG channel and the device gate, introducing a back gate. Furthermore, by inserting an AlN layer on the upper or lower side of the AlGaN barrier layer, leakage current from the source to the gate is suppressed, ensuring the back gate's control over the P-type conductive channel. This invention fully utilizes the characteristics of the double heterojunction channel, realizing a back gate structure without using back-side processing, providing an effective solution for achieving P-type channel GaN transistor devices with low subthreshold slope and high on-current density.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and specifically to a gallium nitride P-MOSFET transistor structure and its manufacturing method. Background Technology

[0002] Gallium nitride (GaN), as a representative third-generation semiconductor material, boasts advantages such as high voltage withstand capability, high operating frequency, and high current density due to its outstanding characteristics including wide bandgap, high saturation drift velocity, and high thermal conductivity. This significantly reduces conduction losses, enabling GaN power devices to operate at high power and under high temperatures. In recent years, lateral GaN HEMT technology has developed rapidly and matured. Enhancement-mode GaN HEMTs based on P-gates have been commercialized and have found varying degrees of application in fast charging, LiDAR, and other fields.

[0003] All-GaN monolithic integration technology, as one of the important development trends and research hotspots in this field, aims to integrate modules such as logic signal generation, drive control, power conversion, monitoring, and protection to reduce parasitic effects (signal crosstalk, interconnection loss, ESD, etc.) caused by chip interconnects. Compared with discrete GaN power devices, GaN monolithic integration technology can maximize the core performance advantages of GaN, such as high frequency and high efficiency. However, the development of all-GaN monolithic integration technology is still in its early stages, one of the main reasons being the immaturity of P-channel transistor development. Due to the lack of high-performance, high-reliability P-channel transistors, the design of all-GaN monolithic integrated circuits has to rely on two-dimensional electron gas (2DEG) conductive N-channel transistors (N-HEMTs) as a substitute, leading to increased circuit design difficulty, high static power consumption, and incomplete functionality, which seriously limits the development and application of GaN ICs. CMOS-based complementary logic circuits, on the other hand, have more suitable voltage conversion thresholds, higher noise margins, and more flexible circuit topologies. Therefore, achieving high-performance P-channel devices that can be monolithically integrated with current mainstream GaN N-HEMTs can not only simplify GaN IC design but also improve GaN IC performance. This enables GaN power semiconductors to maximize their superior performance of high-speed and high-efficiency operation, thereby enhancing GaN's competitive advantage in power semiconductor applications. Summary of the Invention

[0004] This invention addresses the current problems of P-channel gallium nitride transistors by proposing a P-channel gallium nitride transistor with a back gate, which has the excellent characteristics of low subthreshold slope and high on-current density.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A gallium nitride P-MOSFET transistor structure and its manufacturing method, such as Figure 1 As shown, the structure includes a stress-modulated heteroepitaxial substrate 1 (silicon substrate), a gallium nitride buffer layer 2 disposed on the upper surface of the substrate 1, an unintentionally doped gallium nitride channel layer 3 disposed on the upper surface of the gallium nitride buffer layer 2, a first aluminum nitride insertion layer 51 disposed on the unintentionally doped gallium nitride channel layer 3, an aluminum gallium nitride barrier layer 4 disposed on the first aluminum nitride insertion layer 51, a second aluminum nitride insertion layer 52 disposed on the aluminum gallium nitride barrier layer 4, and a p-type gallium nitride channel layer 6 disposed on the second aluminum nitride insertion layer 52. A dielectric passivation layer 7 and a metal electrode are disposed on a P-type gallium nitride channel layer 6. A two-dimensional hole gas is generated at the interface between the second aluminum nitride insertion layer 52 and the P-type gallium nitride channel layer 6. The metal electrode includes a gate 9, a source 10, and a drain 11, wherein the source 10 and the drain 11 are located at the two ends of the top of the transistor, the gate 9 is located in the middle of the top of the transistor, and the source 10 and the drain 11 penetrate the dielectric passivation layer 7 along the vertical direction of the device and then contact the upper surface of the P-type gallium nitride channel layer 6. After the gate 9 penetrates the dielectric passivation layer 7 in the vertical direction of the device, both ends of the gate 9 completely penetrate the P-type gallium nitride channel layer 6 in the vertical direction of the device, while the middle part of the gate 9 partially penetrates the P-type gallium nitride channel layer 6 in the vertical direction of the device. Furthermore, a protrusion structure is present at the middle of both ends of the gate 9 in the horizontal direction of the device. This protrusion structure sequentially penetrates the second aluminum nitride insertion layer 52, the aluminum gallium nitride barrier layer 4, and the first aluminum nitride insertion layer 51 in the vertical direction of the device, and then contacts the upper surface of the unintentionally doped gallium nitride channel layer 3. The vertical, horizontal, and longitudinal directions of the device constitute a three-dimensional Cartesian coordinate system, with the horizontal direction pointing from the source 10 to the drain 11, and the vertical direction pointing from the top to the bottom of the device. A gate dielectric layer 8 is present between the gate 9 and the upper surface of the second aluminum nitride insertion layer 52, between the gate 9 and the P-type gallium nitride channel layer 6, between the gate 9 and the source 10, and between the gate 9 and the drain 11.

[0007] Furthermore, the portion of the gate 9 located in the P-type gallium nitride channel layer 6 is formed by partially etching the P-type gallium nitride channel layer 6. The portion of the gate 9 located in the P-type gallium nitride channel layer 6 is used to regulate the device threshold voltage and restore the two-dimensional electron gas at the interface between the unintentionally doped gallium nitride channel layer 3 and the first aluminum nitride insertion layer 51.

[0008] Furthermore, the portion of the gate 9 located in the P-type gallium nitride channel layer 6 forms a MIS gate structure through the gate 9, the gate dielectric layer 8, and the P-type gallium nitride channel layer 6; the portion of the gate 9 other than that located in the P-type gallium nitride channel layer 6 forms an N-type ohmic contact with the two-dimensional electron gas, making the gate 9 and the two-dimensional electron gas at the same potential, and this portion of the two-dimensional electron gas is defined as the back gate.

[0009] Furthermore, the first aluminum nitride intercalation layer 51 and the second aluminum nitride intercalation layer 52 are used to suppress leakage current path from the source 10 to the gate 9.

[0010] Furthermore, the gate dielectric layer 8 is one or more combinations of silicon nitride, silicon dioxide, aluminum oxide, magnesium oxide and hafnium dioxide, with a thickness of 1-100 nm.

[0011] Furthermore, the special groove structure of the gate 9, which includes two structural types, can be formed by one or a combination of dry etching and wet etching. The groove depth corresponding to the N-type ohmic contact needs to completely etch the P-type gallium nitride channel layer 6. The etching stop surface can be formed in the aluminum nitride insertion layer 51, the aluminum gallium nitride barrier layer 4, or the aluminum nitride insertion layer 52, through metal infiltration during high-temperature annealing and the two-dimensional electron gas channel to form the N-type ohmic contact.

[0012] A method for manufacturing a P-channel gallium nitride transistor with a back gate according to the present invention includes the following steps:

[0013] Step 1: On the substrate 1, a gallium nitride buffer layer 2, an unintentionally doped gallium nitride channel layer 3, a first aluminum nitride insertion layer 51, an aluminum gallium nitride barrier layer 4, a second aluminum nitride insertion layer 52, and a P-type gallium nitride channel layer 6 are epitaxially grown sequentially.

[0014] Step 2: Deposit dielectric passivation layer 7 to passivate the surface of P-type gallium nitride material;

[0015] Step 3: Use dry or wet etching techniques to perform the first round of etching on the gate 9 position, completely etching the dielectric passivation layer 7 in this area. Then, use dry etching techniques to etch the gate 9 at the middle position along the longitudinal direction of the device, partially etching the P-type gallium nitride channel layer 6 in this area, depleting the two-dimensional hole gas channel under the gate, and restoring the two-dimensional electron gas channel under the gate.

[0016] Step 4: Use dry etching technology to perform a second round of etching on the gate position, completely etching the P-type gallium nitride channel layer 6 in the two ends of the gate 9 along the longitudinal direction of the device;

[0017] Step 5: Deposit gate dielectric layer 8;

[0018] Step 6: Use dry or wet etching techniques to create openings in the portion of the P-type gallium nitride channel layer 6 that was completely etched in Step 4. The openings are located in the middle of the device's lateral direction. Etch the gate dielectric layer 8 in this region and make the etching stop surface in the first aluminum nitride insertion layer 51, the aluminum gallium nitride barrier layer 4, or the second aluminum nitride insertion layer 52.

[0019] Step 7: Grow the gate 9 metal using methods such as vapor deposition or sputtering, and perform high-temperature rapid annealing in a nitrogen atmosphere to form an N-type ohmic contact between a portion of the gate 9 and the recovered two-dimensional electron gas channel below.

[0020] Step 8: Wet etching is used to etch the source 10 and drain 11, completely etching the dielectric passivation layer 7 in this area. Then, metals of the source 10 and drain 11 are grown by evaporation or sputtering, and high-temperature rapid annealing is performed in an oxygen atmosphere or a nitrogen-oxygen mixed atmosphere to form a P-type ohmic contact between the source 10 and drain 11 and the two-dimensional hole channel below.

[0021] This invention, based on a double heterojunction epitaxial structure, describes a P-channel gallium nitride transistor structure with a back gate and its manufacturing method. It utilizes the back gate effect to enhance the gate control capability of the device, achieving the main objectives of reducing the subthreshold slope and increasing the on-state current density. The invention etches a portion of the P-type gallium nitride channel layer 6 using conventional gate trench etching methods and utilizes a metal-insulator-semiconductor structure to regulate the threshold voltage, depleting the two-dimensional hole gas in the under-gate region while simultaneously restoring the two-dimensional electron gas. Further etching of openings on top of the conventional gate trench allows a portion of the gate 9 to form an N-type ohmic contact with the restored two-dimensional electron gas channel below, thus introducing a back gate and enhancing the gate's controllability. The invention increases the barrier height by setting aluminum nitride insertion layers 51 and 52, thereby suppressing leakage current from the source 10 to the gate 9. When the device is turned on, the two-dimensional electron gas channel is further restored, and due to the charge balance principle, the two-dimensional hole gas concentration increases, thereby increasing the on-state current density of the device.

[0022] The beneficial effects of this invention are as follows: as a P-channel gallium nitride transistor, it has excellent characteristics such as enhancement threshold voltage, low subthreshold slope and high on-current density. Furthermore, the substrate and manufacturing process selected are compatible with the current mainstream GaN N-HEMT devices, solving the typical problems of low current, slow turn-on and difficult integration of current P-channel gallium nitride transistors. It can be regarded as a preferred solution for realizing GaN monolithic integration. Attached Figure Description

[0023] Figure 1 This is a three-dimensional structural schematic diagram of the P-channel gallium nitride transistor with a back gate according to the present invention.

[0024] Figure 2This is a cross-sectional view of the p-channel gallium nitride transistor with a back gate of the present invention (along...). Figure 1 Mid-section 1);

[0025] Figure 3 This is a cross-sectional view of the p-channel gallium nitride transistor with a back gate of the present invention (along...). Figure 1 Mid-section 2);

[0026] Figure 4 This is a cross-sectional view of the p-channel gallium nitride transistor with a back gate of the present invention (along...). Figure 1 Mid-section 3);

[0027] Figure 5 This is a schematic diagram of the structure of the P-channel gallium nitride transistor with back gate of the present invention after epitaxial growth is performed sequentially on the upper layer of the substrate 1.

[0028] Figure 6 This is a schematic diagram of the structure after the deposition of the dielectric passivation layer in the process flow of the P-channel gallium nitride transistor with back gate of the present invention.

[0029] Figure 7 This is a schematic diagram of the structure after the first round of gate etching in the process flow of the P-channel gallium nitride transistor with back gate of the present invention.

[0030] Figure 8 This is a schematic diagram of the structure after the second round of gate etching in the process flow of the P-channel gallium nitride transistor with back gate of the present invention.

[0031] Figure 9 This is a schematic diagram of the structure of the P-channel gallium nitride transistor with back gate of the present invention after the gate dielectric is deposited in the process flow.

[0032] Figure 10 This is a schematic diagram of the structure after the N-type ohmic contact opening is completed in the process flow of the P-type channel gallium nitride transistor with back gate of the present invention.

[0033] Figure 11 This is a schematic diagram of the structure of the P-channel gallium nitride transistor with back gate after the gate metal has been grown in the process flow of the present invention.

[0034] Figure 12 This is a schematic diagram of the structure after the source and drain metals are grown in the process flow of the P-type channel gallium nitride transistor with back gate of the present invention.

[0035] Figure 13 This is a schematic diagram of the cell arrangement of a P-channel gallium nitride transistor with a back gate according to the present invention.

[0036] Figure 14The simulation transfer characteristics (linear coordinates) of the P-channel gallium nitride transistor with back gate of the present invention are shown.

[0037] Figure 15 The simulation transfer characteristics (semi-logarithmic coordinates) of the P-channel gallium nitride transistor with back gate of the present invention are shown. Detailed Implementation

[0038] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings:

[0039] This invention proposes a P-channel gallium nitride transistor structure with a back gate and its manufacturing method. Based on the current mainstream grooved gate P-channel gallium nitride transistor structure based on double heterojunction, it utilizes the recovery of the two-dimensional electron gas channel under the gate to introduce the back gate effect, thereby improving the gate control capability of the device and achieving the main objectives of reducing the subthreshold slope and increasing the conduction current density.

[0040] like Figure 1 As shown, the present invention proposes a P-channel gallium nitride transistor with a back gate, such as... Figure 1 As shown, the structure includes a stress-modulated heteroepitaxial substrate 1 (silicon substrate), a gallium nitride buffer layer 2 disposed on the upper surface of the substrate 1, an unintentionally doped gallium nitride channel layer 3 disposed on the upper surface of the gallium nitride buffer layer 2, an aluminum nitride insertion layer 51 disposed on the unintentionally doped gallium nitride channel layer 3, an aluminum gallium nitride barrier layer 4 disposed on the aluminum nitride insertion layer 51, an aluminum nitride insertion layer 52 disposed on the aluminum gallium nitride barrier layer 4, a p-type gallium nitride channel layer 6 disposed on the aluminum nitride insertion layer 52, and a p-type gallium nitride channel layer 6 disposed on the aluminum nitride insertion layer 52. The dielectric passivation layer 7 on the gallium channel layer 6, the heterostructure described above can generate two-dimensional hole gas at the interface between the aluminum nitride insertion layer 52 and the P-type gallium nitride channel layer 6; the metal electrode includes a gate 9, a source 10, and a drain 11, wherein the gate 9 contains two structural types along the horizontal plane and vertically along the current conduction direction, one of which is a metal-dielectric-semiconductor (MIS) structure formed after partially etching the P-type gallium nitride channel layer 6, from top to bottom being the gate 9, the gate dielectric layer 8, and the P-type gallium nitride channel layer 6 (e.g., Figure 3 As shown), another type is the N-type ohmic contact between the gate 9 formed after completely etching the P-type gallium nitride channel layer 6 and the two-dimensional electron gas (as shown). Figure 2 As shown), the two contact types of the gate 9 are formed separately after the pattern is defined in a multi-step process. The source 10 and drain 11 are P-type ohmic metals and are implemented in the same process step. Figure 1 The device structure shown is a single-cell structure. In practice, this single cell can be expanded along the horizontal plane and perpendicular to the current conduction direction to form an array structure of multiple cells, thus creating a larger-size device with a larger total gate width (e.g., ...). Figure 13 ).

[0041] Working principle:

[0042] A portion of the P-type gallium nitride channel layer 6 is etched using conventional gate trench etching methods. The threshold voltage is controlled using a metal-insulator-semiconductor structure to deplete the two-dimensional hole gas in the under-gate region while simultaneously restoring the two-dimensional electron gas. Further etching of openings on top of the conventional gate trench allows a portion of the gate 9 to form an N-type ohmic contact with the restored two-dimensional electron gas channel below, thus introducing a back gate and enhancing the gate's controllability. The barrier height is increased by incorporating aluminum nitride insertion layers 51 and 52, thereby suppressing leakage current from the source 10 to the gate 9. As the negative voltage bias on the gate increases, the two-dimensional electron gas channel is further restored. Due to the charge balance principle, the two-dimensional hole gas concentration increases, thereby increasing the device's on-current density. Based on these reasons, as... Figure 4 As shown, the device simultaneously possesses a top metal-insulating dielectric-semiconductor gate control structure and a back two-dimensional electron gas-barrier layer-two-dimensional hole gas (P-channel) gate control structure. The two are electrically connected and at the same potential through a partial N-type ohmic contact of the gate 9, jointly controlling the turn-off and turn-on of the two-dimensional hole gas channel under the gate. In addition, the introduction of aluminum nitride insertion layers 51 and 52 blocks the leakage path from the source 10 to the gate 9, suppresses the static leakage caused by the back gate structure, and ensures the gate control capability of the device while improving the overall on-current density.

[0043] Implementation example:

[0044] Figures 5-12 This is a schematic diagram of the manufacturing process steps for a P-channel gallium nitride transistor with a back gate according to the present invention. The process flow is as follows:

[0045] Step 1: On the substrate 1, a gallium nitride buffer layer 2, an unintentionally doped gallium nitride channel layer 3, an aluminum nitride insertion layer 51, an aluminum gallium nitride barrier layer 4, an aluminum nitride insertion layer 52, and a p-type gallium nitride channel layer 6 are epitaxially grown sequentially. Only one of the aluminum nitride insertion layers 51 and 52 can be grown.

[0046] Step 2: Deposit dielectric passivation layer 7 to passivate the surface of P-type gallium nitride material;

[0047] Step 3: Use photolithography to define the pattern, use dry or wet etching to etch the gate 9 position, completely etch the dielectric passivation layer 7 in this area, and then use dry etching to perform the first round of etching on the gate position, partially etch the P-type gallium nitride channel layer 6 in this area, deplete the two-dimensional hole gas channel under the gate, and restore the two-dimensional electron gas channel under the gate.

[0048] Step 4: Use photolithography (preferably electron beam exposure) to define the pattern, and use dry etching to perform a second round of etching on the gate position, completely etching part of the P-type gallium nitride channel layer 6 in this area. The etched area is within the gate trench area obtained in the first round (third step) of etching.

[0049] Step 5: Deposit gate dielectric layer 8, preferably using dielectric materials with good high-temperature resistance such as silicon nitride and silicon dioxide as gate dielectric materials;

[0050] Step 6: Define the pattern using photolithography (preferably electron beam exposure), and use dry or wet etching techniques to create openings in the area of ​​the P-type gallium nitride channel layer 6 that was completely etched in Step 4 (etch the gate dielectric layer 8 in the opening area). The opening area is within the area etched in the second round (Step 4), and as an option, it can be further etched so that the etching stop surface is in the aluminum nitride insertion layer 51, the aluminum gallium nitride barrier layer 4, or the aluminum nitride insertion layer 52.

[0051] Step 7: Use photolithography to define the pattern, grow N-type ohmic metal by evaporation or sputtering, then peel it off in an organic solution to form gate 9, and perform high-temperature rapid annealing in a nitrogen atmosphere to allow the metal in part of the gate 9 to penetrate downward and form N-type ohmic contact with the recovered two-dimensional electron gas channel below.

[0052] Step 8: The pattern is defined using photolithography. Wet etching is used to etch the source 10 and drain 11, completely etching the dielectric passivation layer 7 in this area to expose the surface of the P-type gallium nitride channel layer 6. Then, P-type ohmic metal is grown by evaporation or sputtering. After that, the source 10 and drain 11 are stripped in an organic solution to form the source 10 and drain 11. The source 10 and drain 11 are then subjected to high-temperature rapid annealing in an oxygen atmosphere or a nitrogen and oxygen mixed atmosphere to form P-type ohmic contact between the source 10 and drain 11 and the two-dimensional hole channel below.

[0053] Example of the effect:

[0054] Figure 13 and Figure 14 To utilize the device transfer characteristics obtained from TCAD simulation software, under the same epitaxial structure and fixed device width and length conditions, this invention provides a P-channel gallium nitride transistor with a back gate that significantly improves the subthreshold slope and on-state current density compared to the currently mainstream grooved gate P-channel gallium nitride transistor.

Claims

1. A gallium nitride P-MOSFET transistor structure, comprising an epitaxial substrate (1), a gallium nitride buffer layer (2) disposed on the upper surface of the substrate (1), an unintentionally doped gallium nitride channel layer (3) disposed on the upper surface of the gallium nitride buffer layer (2), a first aluminum nitride insertion layer (51) disposed on the unintentionally doped gallium nitride channel layer (3), an aluminum gallium nitride barrier layer (4) disposed on the first aluminum nitride insertion layer (51), a second aluminum nitride insertion layer (52) disposed on the aluminum gallium nitride barrier layer (4), and a P-type gallium nitride channel layer (6) disposed on the second aluminum nitride insertion layer (52). A dielectric passivation layer (7) and a metal electrode are provided on a P-type gallium nitride channel layer (6). A two-dimensional hole gas is generated at the interface between the second aluminum nitride insertion layer (52) and the P-type gallium nitride channel layer (6). The metal electrode includes a gate (9), a source (10), and a drain (11), wherein the source (10) and the drain (11) are located at the two ends of the top of the transistor, the gate (9) is located in the middle of the top of the transistor, and the source (10) and the drain (11) penetrate the dielectric passivation layer (7) along the vertical direction of the device and then contact the upper surface of the P-type gallium nitride channel layer (6). After the gate (9) penetrates the dielectric passivation layer (7) in the vertical direction of the device, both ends of the gate (9) completely penetrate the P-type gallium nitride channel layer (6) in the vertical direction of the device, while the middle part of the gate (9) partially penetrates the P-type gallium nitride channel layer (6) in the vertical direction of the device. Furthermore, at the middle part of both ends of the gate (9) in the lateral direction of the device, there is a protrusion structure. This protrusion structure, in turn, completely penetrates the second aluminum nitride insertion layer (52), the aluminum gallium nitride barrier layer (4), and the first aluminum nitride insertion layer (51) in sequence in the vertical direction of the device, and then merges with the unintentionally doped gallium nitride channel layer (3). Surface contact; the vertical direction, the lateral direction and the longitudinal direction of the device form a three-dimensional rectangular coordinate system, and the lateral direction of the device is from the source (10) to the drain (11), and the vertical direction of the device is from the top of the device to the bottom; the upper surface of the dielectric passivation layer (7) between the gate (9) and the second aluminum nitride insertion layer (52), between the gate (9) and the P-type gallium nitride channel layer (6), between the gate (9) and the source (10), and between the gate (9) and the drain (11) have a gate dielectric layer (8).

2. The gallium nitride P-MOSFET transistor structure according to claim 1, characterized in that, The portion of the gate (9) located in the P-type gallium nitride channel layer (6) is formed by partially etching the P-type gallium nitride channel layer (6). The portion of the gate (9) located in the P-type gallium nitride channel layer (6) is used to regulate the device threshold voltage and restore the two-dimensional electron gas at the interface between the unintentionally doped gallium nitride channel layer (3) and the first aluminum nitride insertion layer (51).

3. The gallium nitride P-MOSFET transistor structure according to claim 1, characterized in that, The portion of the gate (9) located in the P-type gallium nitride channel layer (6) forms a MIS gate structure through the gate (9), the gate dielectric layer (8), and the P-type gallium nitride channel layer (6); The portion of the gate (9) other than that located in the P-type gallium nitride channel layer (6) forms an N-type ohmic contact with the two-dimensional electron gas, making the gate (9) and the two-dimensional electron gas at the same potential. This portion of the two-dimensional electron gas is defined as the back gate.

4. The gallium nitride P-MOSFET transistor structure according to claim 1, characterized in that, The first aluminum nitride intercalation layer (51) and the second aluminum nitride intercalation layer (52) are used to suppress leakage current path from the source (10) to the gate (9).

5. The gallium nitride P-MOSFET transistor structure according to claim 1, characterized in that, The gate dielectric layer (8) is one or more of silicon nitride, silicon dioxide, aluminum oxide, magnesium oxide and hafnium dioxide, with a thickness of 1-100 nm.

6. A method for manufacturing a gallium nitride P-MOSFET transistor structure as described in any one of claims 1 to 5, characterized in that, Includes the following steps: Step 1: On the substrate (1), a gallium nitride buffer layer (2), an unintentionally doped gallium nitride channel layer (3), a first aluminum nitride insertion layer (51), an aluminum gallium nitride barrier layer (4), a second aluminum nitride insertion layer (52), and a P-type gallium nitride channel layer (6) are epitaxially grown sequentially. Step 2: Deposit a dielectric passivation layer (7) to passivate the surface of the P-type gallium nitride material; Step 3: Use dry or wet etching techniques to perform the first round of etching on the gate (9) position, completely etch the dielectric passivation layer (7) at the gate (9) position, and then use dry etching techniques to etch the gate (9) at the middle position along the longitudinal direction of the device, partially etch the P-type gallium nitride channel layer (6) at the middle position along the longitudinal direction of the device, deplete the two-dimensional hole gas channel under the gate, and restore the two-dimensional electron gas channel under the gate; Step 4: Use dry etching technology to perform a second round of etching on the gate position, completely etching the P-type gallium nitride channel layer (6) at both ends of the gate (9) along the longitudinal direction of the device. Step 5: Deposit the gate dielectric layer (8); Step 6: Use dry or wet etching techniques to create openings in the area of ​​the P-type gallium nitride channel layer (6) that was completely etched in Step 4. The openings are located in the middle of the device's lateral direction. Etch the gate dielectric layer (8) in the area of ​​the P-type gallium nitride channel layer (6) that was completely etched in Step 4, and make the etching stop surface in the first aluminum nitride insertion layer (51), the aluminum gallium nitride barrier layer (4), or the second aluminum nitride insertion layer (52). Step 7: The gate (9) metal is grown by evaporation or sputtering and then subjected to high-temperature rapid annealing in a nitrogen atmosphere so that a portion of the gate (9) forms an N-type ohmic contact with the recovered two-dimensional electron channel below. Step 8: Wet etching is used to etch the source (10) and drain (11) positions to completely etch the dielectric passivation layer (7) at the source (10) and drain (11) positions. Then, the source (10) and drain (11) metals are grown by evaporation or sputtering, and high-temperature rapid annealing is performed in an oxygen atmosphere or a nitrogen and oxygen mixed atmosphere to form a P-type ohmic contact between the source (10) and drain (11) and the two-dimensional hole channel below.

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