Light-emitting diode with improved luminous uniformity and preparation method thereof

Abstract

The present disclosure provides a light-emitting diode with improved light-emitting uniformity and a method for preparing the same, belonging to the field of optoelectronic manufacturing technology. The light-emitting diode includes: a substrate, an epitaxial layer, an insulating layer, a transparent conductive layer, a first electrode, and a second electrode; the substrate, the epitaxial layer, and the insulating layer are stacked in sequence, the insulating layer has a via hole exposing the epitaxial layer, the transparent conductive layer is located on the surface of the insulating layer away from the substrate, and extends to the surface of the epitaxial layer through the via hole; the first electrode is located on the surface of the transparent conductive layer away from the substrate, the orthographic projection of the first electrode on the substrate is located outside the orthographic projection of the via hole on the substrate, and the second electrode is located on the surface of the epitaxial layer and is insulated from the transparent conductive layer. The embodiment of the present disclosure can improve the problem of affecting the light-emitting efficiency due to light absorption by the electrode after the light-emitting area is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode with improved light emission uniformity and a preparation method thereof. Background Art

[0002] A light-emitting diode (LED) chip typically consists of a substrate, an epitaxial layer, a transparent conductive layer, and electrodes. These layers are stacked in sequence, with the electrodes located on the surface of the transparent conductive layer. The electrodes are electrically connected to the semiconductor layer of the epitaxial layer through the transparent conductive layer. When the electrodes are energized, the transparent conductive layer spreads the current to various areas on the epitaxial layer's surface, causing the LED to emit light. Therefore, the area on the epitaxial layer where the transparent conductive layer is located typically represents the light-emitting region of the LED.

[0003] In related technologies, the transparent conductive layer is typically a single film covering the surface of the epitaxial layer. Under high current, the brightness of the light-emitting region remains consistent across all locations. However, under low current, brightness differences may occur across the region. To improve uniformity across the light-emitting region, the area of ​​the transparent conductive layer is typically reduced, thereby reducing the size of the light-emitting region.

[0004] However, the electrodes are overlapped on the surface of the transparent conductive layer, and the electrodes will block part of the transparent conductive layer and absorb light. Therefore, reducing the area of ​​the transparent conductive layer will affect the luminous efficiency of the light-emitting diode. Summary of the Invention

[0005] The present disclosure provides a light-emitting diode with improved light uniformity and a method for manufacturing the same, which can improve the problem of reduced light-emitting area, where the light-absorbing electrode reduces the light-emitting efficiency. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode, which includes: a substrate, an epitaxial layer, an insulating layer, a transparent conductive layer, a first electrode, and a second electrode; the substrate, the epitaxial layer, and the insulating layer are stacked in sequence, the insulating layer has a via exposing the epitaxial layer, the transparent conductive layer is located on a surface of the insulating layer away from the substrate, and is connected to the epitaxial layer through the via; the first electrode is located on a surface of the transparent conductive layer away from the substrate, the orthographic projection of the first electrode on the substrate is outside the orthographic projection of the via on the substrate, and the second electrode is located on the surface of the epitaxial layer and is insulated from the transparent conductive layer.

[0007] Optionally, the via hole is located between the first electrode and the second electrode.

[0008] Optionally, the via hole is a tapered hole, and an end of the via hole with a larger size is away from the substrate.

[0009] Optionally, an angle between a hole wall of the via hole and a surface of the insulating layer away from the substrate is 10° to 60°.

[0010] Optionally, the insulating layer includes at least two sub-layers stacked sequentially, and in the stacking direction, the etching rates of the materials of the sub-layers in the same etching solution increase sequentially.

[0011] Optionally, the insulating layer includes a first sub-layer and a second sub-layer stacked in sequence, the first sub-layer is an aluminum oxide layer, and the second sub-layer is a silicon oxide layer.

[0012] Optionally, the first sublayer has a thickness of 600 angstroms to 1200 angstroms.

[0013] Optionally, the second sub-layer has a thickness of 2400 angstroms to 5000 angstroms.

[0014] Optionally, the light-emitting diode further includes a passivation layer, a first solder block and a second solder block; the passivation layer is located at least on the surface of the insulating layer, the surface of the transparent conductive layer, the surface of the first electrode and the surface of the second electrode; the first solder block and the second solder block are spaced apart on the passivation layer, and the passivation layer has two through holes that expose the first electrode and the second electrode respectively, and the first solder block and the second solder block are connected to the first electrode and the second electrode respectively through the two through holes.

[0015] On the other hand, an embodiment of the present disclosure also provides a method for preparing a light-emitting diode, the method comprising: providing a substrate; forming an epitaxial layer, an insulating layer and a transparent conductive layer on the substrate in sequence, the insulating layer having a via exposing the epitaxial layer, the transparent conductive layer being located on a surface of the insulating layer away from the substrate, and being connected to the epitaxial layer through the via; making a first electrode and a second electrode, the first electrode being located on a surface of the transparent conductive layer away from the substrate, the orthographic projection of the first electrode on the substrate being outside the orthographic projection of the via on the substrate, and the second electrode being located on the surface of the epitaxial layer and being insulated from the transparent conductive layer.

[0016] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0017] The light-emitting diode provided in the embodiments of the present disclosure includes an epitaxial layer and an insulating layer stacked on a substrate. The insulating layer has a via hole exposing the epitaxial layer. A transparent conductive layer is located on the insulating layer and extends through the via hole to the surface of the epitaxial layer, thereby electrically connecting the transparent conductive layer to the epitaxial layer. A first electrode is located on the transparent conductive layer so that current can be conducted through the first electrode to the transparent conductive layer, and then through the transparent conductive layer to the epitaxial layer.

[0018] Since the transparent conductive layer is electrically connected to the epitaxial layer only through the via hole, that is, the contact area between the transparent conductive layer and the epitaxial layer is the area surrounded by the via hole, the area of ​​the light-emitting region of the epitaxial layer is reduced; at the same time, since the orthographic projections of the first electrode and the via hole on the substrate do not overlap, that is, the first electrode is not overlapped above the via hole, but is offset to one side of the via hole, this can effectively prevent the first electrode from absorbing light in the light-emitting region, improve the problem of affecting the light-emitting efficiency due to electrode light absorption after the light-emitting region is reduced, and enhance the light-emitting effect of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 is a top view of a light emitting diode provided by an embodiment of the present disclosure;

[0021] Figure 2 yes Figure 1 AA cross-section provided;

[0022] Figure 3 This is a schematic diagram of a partial method of producing a light emitting diode according to an embodiment of the present disclosure;

[0023] Figure 4 This is a flow chart of a method for preparing a light emitting diode provided in an embodiment of the present disclosure.

[0024] The descriptions of the marks in the figure are as follows:

[0025] 10. Substrate;

[0026] 20. epitaxial layer; 21. first semiconductor layer; 22. multi-quantum well layer; 23. second semiconductor layer; 24. groove;

[0027] 30. Insulation layer; 31. First sublayer; 32. Second sublayer; 33. Via hole;

[0028] 40. Transparent conductive layer;

[0029] 51. First electrode; 52. Second electrode;

[0030] 60. passivation layer; 61. through hole;

[0031] 71. First soldering point block; 72. Second soldering point block. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0033] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar words used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprise" mean that the elements or objects preceding "include" or "comprises" encompass the elements or objects listed after "include" or "comprises," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0034] Figure 1 This is a top view of a light emitting diode provided by an embodiment of the present disclosure. Figure 2 yes Figure 1 AA cross-section provided. Figure 2 The indication is from Figure 1 The cross-section is taken along the AA section line. Figure 1 、 2 As shown, the light emitting diode includes: a substrate 10 , an epitaxial layer 20 , an insulating layer 30 , a transparent conductive layer 40 , a first electrode 51 and a second electrode 52 .

[0035] like Figure 2 As shown, the substrate 10 , the epitaxial layer 20 and the insulating layer 30 are stacked in sequence. The insulating layer 30 has a via 33 exposing the epitaxial layer 20 . The transparent conductive layer 40 is located on the surface of the insulating layer 30 away from the substrate 10 and is connected to the epitaxial layer 20 through the via 33 .

[0036] like Figure 2As shown, the first electrode 51 is located on the surface of the transparent conductive layer 40 away from the substrate 10, and the orthographic projection of the first electrode 51 on the substrate 10 is located outside the orthographic projection of the via 33 on the substrate 10. The second electrode 52 is located on the surface of the epitaxial layer 20, and the second electrode 52 is insulated from the transparent conductive layer 40.

[0037] The light-emitting diode provided in the embodiments of the present disclosure includes an epitaxial layer 20 and an insulating layer 30 stacked on a substrate 10. The insulating layer 30 has a via 33 exposing the epitaxial layer 20. A transparent conductive layer 40 is located on the insulating layer 30 and extends through the via 33 to the surface of the epitaxial layer 20, thereby electrically connecting the transparent conductive layer 40 to the epitaxial layer 20. A first electrode 51 is located on the transparent conductive layer 40 so that current can be conducted through the first electrode 51 to the transparent conductive layer 40 and then to the epitaxial layer 20.

[0038] Since the transparent conductive layer 40 is electrically connected to the epitaxial layer 20 only through the via 33, that is, the contact area between the transparent conductive layer 40 and the epitaxial layer 20 is the area surrounded by the via 33, the area of ​​the light-emitting region of the epitaxial layer 20 is reduced; at the same time, since the orthographic projections of the first electrode 51 and the via 33 on the substrate 10 do not overlap, that is, the first electrode 51 does not overlap above the via 33, but is offset to one side of the via 33, this can effectively prevent the first electrode 51 from absorbing light in the light-emitting region, improve the problem of affecting the light-emitting efficiency due to electrode light absorption after the light-emitting region is reduced, and enhance the light-emitting effect of the light-emitting diode.

[0039] Optionally, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate 10. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.

[0040] In the embodiment of the present disclosure, Figure 2 As shown, the epitaxial layer 20 includes a first semiconductor layer 21 , a multi-quantum well layer 22 and a second semiconductor layer 23 sequentially stacked on the substrate 10 . The surface of the second semiconductor layer 23 has a groove 24 exposing the first semiconductor layer 21 .

[0041] For example, Figure 2 As shown, the first electrode 51 is located on the transparent conductive layer 40 on the second semiconductor layer 23 .

[0042] For example, Figure 2 As shown, the insulating layer 30 is located on the surface of the second semiconductor layer 23 and extends into the groove 24 . The insulating layer 30 has an opening in the area within the groove 24 . The second electrode 52 is located in the groove 24 and is connected to the first semiconductor layer 21 through the opening of the insulating layer 30 .

[0043] like Figure 1 As shown, the epitaxial layer 20 is rectangular, and the grooves 24 are located at the corners of the epitaxial layer 20. Since the corners are more difficult to break than the side areas, the grooves 24 are provided at the corners to improve the anti-breakage performance of the light-emitting diode.

[0044] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0045] Exemplarily, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0046] Optionally, the first semiconductor layer 21 is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0047] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers, wherein the multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0048] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0049] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0050] Optionally, the second semiconductor layer 23 is a magnesium-doped p-type GaN layer, and the thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0051] Alternatively, as Figure 2 As shown, the light emitting diode further includes a passivation layer 60 , a first soldering block 71 and a second soldering block 72 .

[0052] like Figure 2 As shown, the passivation layer 60 is at least located on the surface of the insulating layer 30 , the surface of the transparent conductive layer 40 , the surface of the first electrode 51 , and the surface of the second electrode 52 .

[0053] Among them, the first solder block 71 and the second solder block 72 are spaced apart and distributed on the passivation layer 60, and the passivation layer 60 has two through holes 61 that expose the first electrode 51 and the second electrode 52 respectively. The first solder block 71 and the second solder block 72 are connected to the first electrode 51 and the second electrode 52 respectively through the two through holes 61.

[0054] The passivation layer 60 is provided to isolate the connection between the solder joint block and the epitaxial layer 20 or the transparent conductive layer 40 , thereby protecting the light emitting diode from short circuit.

[0055] For example, the passivation layer 60 may be a distributed Bragg reflector (DBR layer), which includes a plurality of periodically alternating SiO2 layers and TiO2 layers. The number of periods in the DBR layer may be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0056] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0057] In addition to the passivation function, the DBR layer is also used to reflect the light emitted from the multi-quantum well layer 22 to the DBR layer to the substrate 10, thereby improving the light extraction effect.

[0058] Alternatively, as Figure 1 As shown, the two soldering point blocks are both rectangular blocks, which increase the area and facilitate electrical conduction. In addition, the two soldering point blocks are spaced apart on the surface of the passivation layer 60.

[0059] For example, the first solder bump 71 and the second solder bump 72 may each be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked in sequence.

[0060] The thickness of the first Al layer is 8000 angstroms to 12000 angstroms, the thickness of the first Ti layer is 100 angstroms to 500 angstroms, the thickness of the second Al layer is 8000 angstroms to 12000 angstroms, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms, and the thickness of the Au layer is 2000 angstroms to 5000 angstroms.

[0061] For example, the thickness of the first Al layer is 10,000 angstroms, the thickness of the first Ti layer is 200 angstroms, the thickness of the second Al layer is 10,000 angstroms, the thickness of the second Ti layer is 1,000 angstroms, and the thickness of the Au layer is 3,000 angstroms.

[0062] Alternatively, as Figure 1 、 2 As shown, the via hole 33 is located between the first electrode 51 and the second electrode 52. Since the area corresponding to the via hole 33 is the light-emitting area, the light-emitting area is avoided from the positions of the first electrode 51 and the second electrode 52 to avoid the electrodes blocking light and ensure the light-emitting effect of the light-emitting diode.

[0063] Alternatively, as Figure 3 As shown, the via hole 33 is a tapered hole, and the larger end of the via hole 33 is away from the substrate 10. Setting the via hole 33 as a tapered hole allows the hole wall of the via hole 33 to form a slope, which is conducive to the subsequent coverage of the transparent conductive layer 40 and better coverage.

[0064] For example, the cross section of the via hole 33 in the direction parallel to the substrate 10 may be circular or rectangular. Figure 1 As shown, the cross section of the via hole 33 in a direction parallel to the substrate 10 is rectangular.

[0065] Alternatively, as Figure 3 As shown, the angle α between the hole wall of the via hole 33 and the surface of the insulating layer 30 away from the substrate 10 is 10° to 60°.

[0066] For example, the angle α between the wall of the via hole 33 and the surface of the insulating layer 30 away from the substrate 10 is 30°. This allows the wall of the via hole 33 to form a small slope, which is beneficial for subsequent coverage by the transparent conductive layer 40 and provides better coverage.

[0067] Optionally, the insulating layer 30 includes at least two sub-layers stacked sequentially, and in the stacking direction, the etching rates of the materials of the sub-layers in the same etching solution increase sequentially.

[0068] The etch rate refers to the amount of material lost per unit area per unit time on a sublayer. A higher etch rate results in a greater loss of material during the etching process, and the resulting openings are larger. A lower etch rate results in a lower loss of material during the etching process, and the resulting openings are smaller.

[0069] In the disclosed embodiment, vias 33 are formed on the surface of the insulating layer 30 by etching. The etching rate of the sublayer closest to the substrate 10 is relatively low, and the etching rate of the sublayer gradually increases as the distance from the substrate 10 increases. Thus, among the sublayers, the sublayer closest to the substrate 10 has the smallest etched opening, and the opening of the sublayer gradually increases as it moves away from the substrate 10, so that the openings of the multiple stacked sublayers collectively form a tapered hole.

[0070] For example, Figure 3 As shown, the insulating layer 30 includes a first sub-layer 31 and a second sub-layer 32 stacked in sequence. The first sub-layer 31 is an aluminum oxide layer, and the second sub-layer 32 is a silicon oxide layer.

[0071] Since the etching rate of the aluminum oxide layer is lower than that of the silicon oxide layer, the opening formed by etching on the aluminum oxide layer is smaller, while the opening formed by etching on the silicon oxide layer is larger. In this way, after the aluminum oxide layer and the silicon oxide layer are stacked, the two openings can be combined to form a via 33 with an inclined hole wall.

[0072] Illustratively, the thickness of the first sub-layer 31 is 600 angstroms to 1200 angstroms. For example, the thickness of the first sub-layer 31 is 1000 angstroms.

[0073] Illustratively, the thickness of the second sub-layer 32 is 2400 angstroms to 5000 angstroms. For example, the thickness of the second sub-layer 32 is 3000 angstroms.

[0074] In the embodiment of the present disclosure, the thickness of the second sublayer 32 is greater than that of the first sublayer 31 , which allows the hole wall of the via 33 to form a smaller angle α with the surface of the insulating layer 30 away from the substrate 10 , facilitating subsequent coverage by the transparent conductive layer 40 and providing better coverage.

[0075] Optionally, the transparent conductive layer 40 is an indium tin oxide (ITO) layer. ITO has good transmittance and low resistivity. Using ITO as the transparent conductive layer 40 allows more light to be transmitted through the transparent conductive layer 40, thereby ensuring the desired effect. Furthermore, due to its low resistivity, it facilitates carrier conduction and improves injection efficiency.

[0076] Optionally, the transparent conductive layer 40 is an indium zinc oxide (IZO) layer. IZO has good transmittance and low resistivity. Using IZO as the transparent conductive layer 40 allows more light to be transmitted through the transparent conductive layer 40, thereby ensuring the desired effect. Furthermore, due to its low resistivity, it facilitates carrier conduction and improves injection efficiency.

[0077] For example, the thickness of the transparent conductive layer 40 may be 3000 angstroms to 6000 angstroms. For example, the thickness of the transparent conductive layer 40 is 4000 angstroms.

[0078] Figure 4 This is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure. Figures 1 to 3 As shown in the light emitting diode. Figure 4 As shown, the preparation method comprises:

[0079] S11: providing a substrate 10.

[0080] S12 : forming an epitaxial layer 20 , an insulating layer 30 and a transparent conductive layer 40 in sequence on the substrate 10 .

[0081] The insulating layer 30 has a via hole 33 exposing the epitaxial layer 20 . The transparent conductive layer 40 is located on a surface of the insulating layer 30 away from the substrate 10 and is connected to the epitaxial layer 20 through the via hole 33 .

[0082] S13: Fabricate the first electrode 51 and the second electrode 52 .

[0083] Among them, the first electrode 51 is located on the surface of the transparent conductive layer 40 away from the substrate 10, and the orthographic projection of the first electrode 51 on the substrate 10 is located outside the orthographic projection of the via 33 on the substrate 10. The second electrode 52 is located on the surface of the epitaxial layer 20 and is insulated from the transparent conductive layer 40.

[0084] The light-emitting diode fabricated using this method includes an epitaxial layer 20 and an insulating layer 30 stacked on a substrate 10. The insulating layer 30 has a via 33 exposing the epitaxial layer 20. A transparent conductive layer 40 is positioned on the insulating layer 30 and extends through the via 33 to the surface of the epitaxial layer 20, electrically connecting the transparent conductive layer 40 to the epitaxial layer 20. A first electrode 51 is positioned on the transparent conductive layer 40, allowing current to flow through the first electrode 51 to the transparent conductive layer 40 and then to the epitaxial layer 20. Since the transparent conductive layer 40 is electrically connected to the epitaxial layer 20 only through the via 33, that is, the contact area between the transparent conductive layer 40 and the epitaxial layer 20 is the area surrounded by the via 33, the area of ​​the light-emitting region of the epitaxial layer 20 is reduced; at the same time, since the orthographic projections of the first electrode 51 and the via 33 on the substrate 10 do not overlap, that is, the first electrode 51 does not overlap above the via 33, but is offset to one side of the via 33, this can effectively prevent the first electrode 51 from absorbing light in the light-emitting region, improve the problem of affecting the light-emitting efficiency due to electrode light absorption after the light-emitting region is reduced, and enhance the light-emitting effect of the light-emitting diode.

[0085] In step S11, the substrate 10 is a sapphire substrate 10, a silicon substrate 10, or a silicon carbide substrate 10. The substrate 10 can be a flat substrate 10 or a patterned substrate 10.

[0086] As an example, in the embodiment of the present disclosure, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 is a commonly used substrate 10 with mature technology and low cost. Specifically, it can be a patterned sapphire substrate 10 or a sapphire flat sheet substrate 10.

[0087] The sapphire substrate 10 may be pre-treated by placing it in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking it for 12 to 18 minutes. For example, in the embodiment of the present disclosure, the sapphire substrate 10 is baked for 15 minutes.

[0088] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0089] Growing the epitaxial layer 20 on the substrate 10 in step S12 may include: sequentially forming a first semiconductor layer 21 , a multi-quantum well layer 22 , and a second semiconductor layer 23 on the sapphire substrate 10 by using MOCVD technology.

[0090] The first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0091] Optionally, the first semiconductor layer 21 is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0092] The growth temperature of the n-type GaN layer may be 1000° C. to 1100° C., and the growth pressure of the n-type GaN layer may be 100 Torr to 300 Torr.

[0093] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers, wherein the multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0094] When growing the multi-quantum well layer 22, the pressure of the MOCVD reaction chamber is controlled at 200 Torr. When growing the InGaN quantum well layer, the reaction chamber temperature is 760°C to 780°C. When growing the GaN quantum barrier layer, the reaction chamber temperature is 860°C to 890°C.

[0095] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0096] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0097] Optionally, the second semiconductor layer 23 is a magnesium-doped p-type GaN layer, and the thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0098] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer may be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer may be 800° C. to 1000° C.

[0099] After forming the epitaxial layer 20 in step S12 , the preparation method further includes etching the second semiconductor layer 23 to form a groove 24 exposing the second semiconductor layer 23 .

[0100] In the embodiment of the present disclosure, the insulating layer 30 includes a first sub-layer 31 and a second sub-layer 32 stacked in sequence. The first sub-layer 31 is an aluminum oxide layer, and the second sub-layer 32 is a silicon oxide layer.

[0101] After forming the groove 24, an insulating layer 30 is formed on the epitaxial layer 20. The formation of the insulating layer 30 may include the following two steps.

[0102] In the first step, a silicon aluminum oxide layer is formed on the surface of the second semiconductor layer 23 and the surface of the first semiconductor layer 21 .

[0103] Illustratively, the thickness of the silicon aluminum oxide layer is 600 angstroms to 1200 angstroms. For example, the thickness of the silicon aluminum oxide layer is 1000 angstroms.

[0104] In the second step, a silicon oxide layer is formed on the surface of the aluminum oxide layer.

[0105] Illustratively, the thickness of the silicon oxide layer is 2400 angstroms to 5000 angstroms. For example, the thickness of the silicon oxide layer is 3000 angstroms.

[0106] The thickness of the second sublayer 32 is greater than that of the first sublayer 31 , which allows the hole wall of the via hole 33 to form a smaller angle α with the surface of the insulating layer 30 away from the substrate 10 , facilitating subsequent covering by the transparent conductive layer 40 and achieving better coverage.

[0107] After the insulating layer 30 is formed, the further step includes forming a via hole 33 on the surface of the insulating layer 30 by etching.

[0108] Since the etching rate of the aluminum oxide layer is lower than that of the silicon oxide layer, the opening formed by etching on the aluminum oxide layer is smaller, while the opening formed by etching on the silicon oxide layer is larger. In this way, after the aluminum oxide layer and the silicon oxide layer are stacked, the two openings can be combined to form a via 33 with an inclined hole wall.

[0109] like Figure 3 As shown, the via hole 33 is a tapered hole, and the larger end of the via hole 33 is away from the substrate 10. The cross section of the via hole 33 in a direction parallel to the substrate 10 is rectangular.

[0110] Alternatively, as Figure 3 As shown, the angle α between the hole wall of the via hole 33 and the surface of the insulating layer 30 away from the substrate 10 is 10° to 60°.

[0111] Exemplarily, the angle α between the hole wall of the via hole 33 and the surface of the insulating layer 30 away from the substrate 10 is 30°.

[0112] After forming the insulating layer 30 , the preparation method further includes forming a transparent conductive layer 40 on the surface of the insulating layer 30 , and the transparent conductive layer 40 extends to the surface of the second semiconductor layer 23 through the via hole 33 .

[0113] Exemplarily, the transparent conductive layer 40 is an indium tin oxide layer or an indium zinc oxide layer.

[0114] For example, the thickness of the transparent conductive layer 40 may be 3000 angstroms to 6000 angstroms. For example, the thickness of the transparent conductive layer 40 is 4000 angstroms.

[0115] Step S13 includes: forming a first electrode 51 on a surface of the transparent conductive layer 40 away from the substrate 10 , and forming a second electrode 52 on a surface of the first semiconductor layer 21 in the groove 24 .

[0116] Among them, the first electrode 51 is mainly composed of gold beryllium, and the second electrode 52 is evaporated with gold germanium as the base material. When evaporating the gold germanium alloy, the evaporation power must be guaranteed to avoid the evaporation time exceeding seconds to prevent the deviation of the alloy composition, and annealing is performed.

[0117] After step S13 , the preparation method further includes forming a passivation layer 60 on the surface of the insulating layer 30 , the surface of the transparent conductive layer 40 , the surface of the first electrode 51 , and the surface of the second electrode 52 .

[0118] The passivation layer 60 may be a DBR layer, which includes a plurality of SiO2 layers and TiO2 layers periodically and alternately stacked. The number of periods of the DBR layer may be between 20 and 50. For example, the number of periods of the DBR layer is 32.

[0119] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0120] After the passivation layer 60 is formed, two through holes 61 need to be formed on the surface of the passivation layer 60 by etching.

[0121] like Figure 2 As shown, one of the through holes 61 exposes the first electrode 51 , and the other through hole 61 exposes the second electrode 52 .

[0122] After etching to form two through holes 61 on the passivation layer 60 , the manufacturing method further includes: forming a first soldering block 71 and a second soldering block 72 on the surface of the passivation layer 60 .

[0123] The first soldering point block 71 is connected to the first electrode 51 through one through hole 61 , and the second soldering point block 72 is connected to the second electrode 52 through another through hole 61 .

[0124] For example, the first solder bump 71 and the second solder bump 72 may each be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked in sequence.

[0125] The thickness of the first Al layer is 8000 angstroms to 12000 angstroms, the thickness of the first Ti layer is 100 angstroms to 500 angstroms, the thickness of the second Al layer is 8000 angstroms to 12000 angstroms, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms, and the thickness of the Au layer is 2000 angstroms to 5000 angstroms.

[0126] For example, the thickness of the first Al layer is 10,000 angstroms, the thickness of the first Ti layer is 200 angstroms, the thickness of the second Al layer is 10,000 angstroms, the thickness of the second Ti layer is 1,000 angstroms, and the thickness of the Au layer is 3,000 angstroms.

[0127] In the embodiment of the present disclosure, after the solder joint block is manufactured, the preparation method may further include: manufacturing a protective layer on the surface of the passivation layer 60 .

[0128] For example, in the embodiment of the present disclosure, the protective layer may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.

[0129] It should be noted that after a protective layer is grown on the surface of the passivation layer 60 , a photolithography technique may be used to etch through holes 61 on the surface of the protective layer to expose the solder joints, so as to facilitate electrical connection.

[0130] Finally, the sapphire substrate 10 can be subjected to invisible cutting and cleaving, which can effectively reduce the loss of brightness. Then, the light emitting diode is obtained by testing.

[0131] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light-emitting diode comprises: a substrate (10), an epitaxial layer (20), an insulating layer (30), a transparent conductive layer (40), a first electrode (51) and a second electrode (52); The substrate (10), the epitaxial layer (20), and the insulating layer (30) are stacked in sequence, the insulating layer (30) has a via hole (33) exposing the epitaxial layer (20), and the transparent conductive layer (40) is located on a surface of the insulating layer (30) away from the substrate (10), and is connected to the epitaxial layer (20) through the via hole (33); The first electrode (51) is located on a surface of the transparent conductive layer (40) away from the substrate (10); the orthographic projection of the first electrode (51) on the substrate (10) is located outside the orthographic projection of the via hole (33) on the substrate (10); the epitaxial layer (20) comprises a first semiconductor layer (21), a multi-quantum well layer (22), and a second semiconductor layer (23) stacked in sequence on the substrate (10); the second electrode (52) is located on the surface of the first semiconductor layer (21) and is insulated from the transparent conductive layer (40).

2. The light emitting diode according to claim 1, characterized in that The via hole (33) is located between the first electrode (51) and the second electrode (52).

3. The light emitting diode according to claim 1, characterized in that The via hole (33) is a tapered hole, and the end of the via hole (33) with a larger size is away from the substrate (10).

4. The light emitting diode according to claim 3, characterized in that The angle between the hole wall of the via hole (33) and the surface of the insulating layer (30) away from the substrate (10) is 10° to 60°.

5. The light emitting diode according to claim 3, characterized in that The insulating layer (30) comprises at least two sub-layers stacked in sequence, and in the stacking direction, the etching rates of the materials of the sub-layers in the same etching solution increase in sequence.

6. The light emitting diode according to claim 5, characterized in that The insulating layer (30) comprises a first sublayer (31) and a second sublayer (32) stacked in sequence, the first sublayer (31) being an aluminum oxide layer, and the second sublayer (32) being a silicon oxide layer.

7. The light emitting diode according to claim 6, characterized in that The thickness of the first sublayer (31) is 600 angstroms to 1200 angstroms.

8. The light emitting diode according to claim 6, characterized in that The thickness of the second sub-layer (32) is 2400 angstroms to 5000 angstroms.

9. The light emitting diode according to any one of claims 1 to 8, characterized in that: The light emitting diode further includes a passivation layer (60), a first soldering point block (71) and a second soldering point block (72); The passivation layer (60) is at least located on the surface of the insulating layer (30), the surface of the transparent conductive layer (40), the surface of the first electrode (51), and the surface of the second electrode (52); The first soldering point block (71) and the second soldering point block (72) are spaced apart and distributed on the passivation layer (60); the passivation layer (60) has two through holes (61) respectively exposing the first electrode (51) and the second electrode (52); the first soldering point block (71) and the second soldering point block (72) are respectively connected to the first electrode (51) and the second electrode (52) through the two through holes (61).

10. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: providing a substrate; An epitaxial layer, an insulating layer, and a transparent conductive layer are sequentially formed on the substrate, wherein the insulating layer has a via hole exposing the epitaxial layer, the transparent conductive layer is located on a surface of the insulating layer away from the substrate and is connected to the epitaxial layer through the via hole, and the epitaxial layer includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer sequentially stacked on the substrate; A first electrode and a second electrode are manufactured, wherein the first electrode is located on a surface of the transparent conductive layer away from the substrate, the orthographic projection of the first electrode on the substrate is located outside the orthographic projection of the via on the substrate, and the second electrode is located on a surface of the first semiconductor layer and is insulated from the transparent conductive layer.

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