A three-level dc-dc bus midpoint voltage control method

Abstract

The application provides a three-level DCDC bus midpoint voltage control method in the field of power electronics, comprising the following steps: S10, real-time monitoring of the working state of a three-level circuit topology and the bias direction of a bus midpoint voltage VBUS_M, charging and positive bias, entering step S20; charging and reverse bias, entering step S30; discharging and positive bias, entering step S40; discharging and reverse bias, entering step S50; S20, adjusting the duty cycle of a switching tube T4 to discharge the voltage V_P of a capacitor cp; S30, adjusting the duty cycle of a switching tube T1 to discharge the voltage V_N of a capacitor cn; S40, adjusting the duty cycle of the switching tube T1 to boost the voltage V_N of the capacitor cn; and S50, adjusting the duty cycle of the switching tube T4 to boost the voltage V_P of the capacitor cp. The application has the advantage that the bus midpoint voltage is controlled, and the stability of the operation of a DCDC converter is greatly improved.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a method for controlling the midpoint voltage of a three-level DC-DC bus. Background Technology

[0002] With the rise of the new energy industry, most electrical equipment is developing towards high voltage and high power to meet the ever-increasing demand for electricity. Traditional DC-DC converters use a two-level circuit topology, which, due to the limitations of the voltage withstand capability and switching frequency of the switching devices, cannot simultaneously achieve small size and high-voltage output ripple. Since the three-level circuit topology has only half the switching transistor voltage stress of the two-level circuit topology, it has an inherent advantage in the topology selection of high-voltage DC-DC converters.

[0003] Existing three-level circuit topologies (DC-CDC converters) such as Figure 7 As shown, using synchronous switching of transistors T1 and T4, and synchronous switching of transistors T2 and T3, the three-level circuit topology has only two current loops during operation: VBUS_P-T1-LP-Rload-LN-T4-VBUS_N and T2-LP-Rload-LN-T3. The bus midpoint voltage VBUS_M is maintained by hardware parameters and the RH / RL loop. Due to the differences in the hardware parameters of the components in the three-level circuit topology, the bus midpoint voltage VBUS_M will shift. The greater the difference, the greater the shift. Traditionally, no corresponding compensation has been made for this, thus affecting the stability of the DC-DC converter operation.

[0004] Therefore, how to provide a method for controlling the bus midpoint voltage of a three-level DC-DC converter to improve the stability of the DC-DC converter's operation has become an urgent technical problem to be solved. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for controlling the bus midpoint voltage of a three-level DC-DC converter, so as to improve the stability of the DC-DC converter operation by controlling the bus midpoint voltage.

[0006] This invention is implemented as follows: a method for controlling the neutral point voltage of a three-level DC-DC bus, comprising the following steps:

[0007] Step S10: Monitor the operating status of the three-level circuit topology and the bias direction of the bus midpoint voltage VBUS_M in real time. When the operating status is charging and the bias direction is positive, proceed to step S20; when the operating status is charging and the bias direction is negative, proceed to step S30; when the operating status is discharging and the bias direction is positive, proceed to step S40; when the operating status is discharging and the bias direction is negative, proceed to step S50.

[0008] Step S20: Adjust the duty cycle of the switching transistor T4 to discharge the voltage V_P of the capacitor cp;

[0009] Step S30: Adjust the duty cycle of the switching transistor T1 to discharge the voltage V_N of capacitor cn;

[0010] Step S40: Adjust the duty cycle of the switching transistor T1 to increase the voltage V_N of the capacitor cn;

[0011] Step S50: Adjust the duty cycle of the switching transistor T4 to increase the voltage V_P of the capacitor cp.

[0012] Further, in step S10, the bias direction of the bus midpoint voltage VBUS_M of the real-time monitoring three-level circuit topology is specifically as follows:

[0013] The voltage V_P of capacitor cp and the voltage V_N of capacitor cn are monitored in real time. When the voltage V_P is greater than the voltage V_N, the bias direction is positive; when the voltage V_P is less than the voltage V_N, the bias direction is negative.

[0014] Further, step S20 specifically includes:

[0015] Based on the synchronous control of switching transistors T1 and T4, the duty cycle of switching transistor T4 is reduced. Switch T4 is turned off the instant the duty cycle decreases. Switch T3 is turned on due to its complementarity with switching transistor T4, forming the first discharge loop with the path VBUS_P-T1-LP-Rload-LN-T3-VBUS_M. This discharges the voltage V_P of capacitor cp so that the bus midpoint voltage VBUS_M can be balanced.

[0016] Further, step S30 specifically includes:

[0017] Based on the synchronous control of switching transistors T1 and T4, the duty cycle of switching transistor T1 is reduced. Switch T1 is turned off the instant the duty cycle decreases. Switch T2 is turned on due to its complementarity with switching transistor T1, forming a second discharge circuit with the path VBUS_M-T2-LP-Rload-LN-T4-VBUS_N. This discharges the voltage V_N of capacitor cn so that the bus midpoint voltage VBUS_M can be balanced.

[0018] Further, step S40 specifically includes:

[0019] Based on the synchronous control of switching transistors T1 and T4, the duty cycle of switching transistor T1 is reduced. Switch T1 is turned off the instant the duty cycle decreases. Switch T2 is turned on due to its complementarity with switching transistor T1, forming the first compensation loop with the path Rload-LP-T2-VBUS_M-VBUS_N-T4-LN. This increases the voltage V_N of capacitor cn so that the bus midpoint voltage VBUS_M can reach balance.

[0020] Further, step S50 specifically includes:

[0021] Based on the synchronous control of switching transistors T1 and T4, the duty cycle of switching transistor T4 is reduced. Switch T4 is turned off the instant the duty cycle decreases. Switch T3 is turned on due to its complementarity with switching transistor T4, forming a second compensation loop with the path Rload-LP-T1-VBUS_P-VBUS_M-T3-LN. This increases the voltage V_P of capacitor cp so that the bus midpoint voltage VBUS_M can reach balance.

[0022] The advantages of this invention are:

[0023] By real-time monitoring of the operating state of the three-level circuit topology and the bias direction of the bus midpoint voltage VBUS_M, when the operating state is charging and the bias direction is positive, the first discharge circuit with the path VBUS_P-T1-LP-Rload-LN-T3-VBUS_M is formed by reducing the duty cycle of the switch T4 to discharge the voltage V_P of capacitor cp. When the operating state is charging and the bias direction is reverse, the second discharge circuit with the path VBUS_M-T2-LP-Rload-LN-T4-VBUS_N is formed by reducing the duty cycle of the switch T1 to discharge the voltage V_N of capacitor cn. When the operating state is discharging and the bias direction is positive, the second discharge circuit with the path VBUS_M-T2-LP-Rload-LN-T4-VBUS_N is formed by reducing the duty cycle of the switch T1 to discharge the voltage V_N of capacitor cn.

[0024] The first compensation circuit, Rload-LP-T2-VBUS_M-VBUS_N-T4-LN, boosts the voltage V_N of capacitor cn. When the operating state is discharge and the bias direction is reversed, the second compensation circuit, Rload-LP-T1-VBUS_P-VBUS_M-T3-LN, is formed by reducing the duty cycle of switch T4 to boost the voltage V_P of capacitor cp. That is, regardless of the current operating state and bias direction, the voltage of capacitor cp or capacitor cn can be discharged or boosted, keeping the bus midpoint voltage VBUS_M balanced. In other words, the offset of the bus midpoint voltage VBUS_M is compensated, thereby controlling the bus midpoint voltage and greatly improving the stability of the DC-DC converter. Attached Figure Description

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0026] Figure 1 This is a flowchart of a three-level DC-DC bus midpoint voltage control method according to the present invention.

[0027] Figure 2 This is a schematic diagram of the superimposed midpoint compensation loop of the present invention.

[0028] Figure 3 This is a schematic diagram of the circuit in which the present invention is in a charging state and the bias direction is positive.

[0029] Figure 4 This is a schematic diagram of the circuit in which the present invention is in a charging state and the bias direction is reversed.

[0030] Figure 5 This is a schematic diagram of the circuit in which the present invention is in the discharge state and the bias direction is positive.

[0031] Figure 6 This is a schematic diagram of the circuit in which the present invention is in the discharge state and the bias direction is reversed.

[0032] Figure 7 This is a circuit diagram of a three-level circuit topology. Detailed Implementation

[0033] The overall idea of ​​the technical solution in this application embodiment is as follows: Real-time monitoring of the operating state of the three-level circuit topology and the bias direction of the bus midpoint voltage VBUS_M; reducing the duty cycle of switch T4 or switch T1 based on the operating state and bias direction; thereby forming a first discharge circuit, a second discharge circuit, a first compensation circuit, or a second compensation circuit to discharge or boost the voltage of capacitor cp or capacitor cn, and to compensate for the offset of the bus midpoint voltage VBUS_M, so as to improve the stability of the DC-DC converter operation.

[0034] Please refer to Figures 1 to 7 As shown, a preferred embodiment of the three-level DC-DC bus neutral point voltage control method of the present invention includes the following steps:

[0035] Step S10: Real-time monitoring of the operating status of the three-level circuit topology and the bias direction of the bus midpoint voltage VBUS_M. When the operating status is charging (energy flows from the bus end to the load end) and the bias direction is positive, proceed to step S20; when the operating status is charging and the bias direction is reversed, proceed to step S30; when the operating status is discharging (energy flows from the load end to the bus end) and the bias direction is positive, proceed to step S40; when the operating status is discharging and the bias direction is reversed, proceed to step S50.

[0036] Step S20: Adjust the duty cycle of the switching transistor T4 to discharge the voltage V_P of the capacitor cp;

[0037] Step S30: Adjust the duty cycle of the switching transistor T1 to discharge the voltage V_N of capacitor cn;

[0038] Step S40: Adjust the duty cycle of the switching transistor T1 to increase the voltage V_N of the capacitor cn;

[0039] Step S50: Adjust the duty cycle of the switching transistor T4 to increase the voltage V_P of the capacitor cp.

[0040] This invention determines the bias direction of the bus midpoint voltage VBUS_M based on the voltage difference between voltages V_P and V_N, and then determines the bias direction based on the inductor current i. LP The direction of the bias is used to determine whether the current state is charging or discharging. Finally, based on the bias direction and operating state (charging / discharging), the compensation duty cycle is calculated to create a discharge circuit for the half bus with a higher voltage or a compensation circuit (charging circuit) for the half bus with a lower voltage. The calculation process is as follows:

[0041] a. Preset an expected bus differential pressure value, VbusDiff_ref;

[0042] b. Preset a proportional parameter for a midpoint control loop. The initial value of Kp_2 is set to one-thousandth of the current loop Kp_1, Kp_2 = (Kp_1 / 1000);

[0043] c. Preset the integral parameters of a midpoint control loop. The initial value of Ki_2 is set to one ten-thousandth of the current loop Ki_1. Ki_2 = (Ki_1 / 10000).

[0044] d. Calculate the current bus differential pressure: VbusDiff = V_P - V_N;

[0045] e. Obtain the error value of the previous bus differential pressure: VbusDiff_lasterr = VbusDiff_err;

[0046] f. Calculate the error between the current bus differential pressure and the expected differential pressure: VbusDiff_err = VbusDiff - VbusDiff_ref;

[0047] g. Calculate the midpoint control loop result:

[0048] PI_2=PI_2+Kp_2*(VbusDiff_err-VbusDiff_lasterr)

[0049] +Ki_2*VbusDiff_err.

[0050] In step S10, the bias direction of the bus midpoint voltage VBUS_M of the real-time monitoring three-level circuit topology is specifically as follows:

[0051] The voltage V_P across capacitor cp and the voltage V_N across capacitor cn are monitored in real time. When V_P is greater than V_N, the bias direction is forward; when V_P is less than V_N, the bias direction is reverse. The capacitance values ​​of capacitors cp and cn are equal, and the resistance values ​​of resistors RH and RL are equal.

[0052] Step S20 specifically involves:

[0053] Based on the synchronous control of switching transistors T1 and T4, the duty cycle of switching transistor T4 is reduced. Switch T4 is turned off the instant the duty cycle decreases. Switch T3 is turned on due to its complementarity with switching transistor T4, forming the first discharge loop with the path VBUS_P-T1-LP-Rload-LN-T3-VBUS_M. This discharges the voltage V_P of capacitor cp so that the bus midpoint voltage VBUS_M can be balanced.

[0054] The output voltage at this time is as follows:

[0055] PI_OUT(T1) = PI_1;

[0056] PI_OUT(T4) = PI_1 - PI_2.

[0057] Step S30 specifically involves:

[0058] Based on the synchronous control of switching transistors T1 and T4, the duty cycle of switching transistor T1 is reduced. Switch T1 is turned off the instant the duty cycle decreases. Switch T2 is turned on due to its complementarity with switching transistor T1, forming a second discharge circuit with the path VBUS_M-T2-LP-Rload-LN-T4-VBUS_N. This discharges the voltage V_N of capacitor cn so that the bus midpoint voltage VBUS_M can be balanced.

[0059] The output voltage at this time is as follows:

[0060] PI_OUT(T1) = PI_1 - PI_2;

[0061] PI_OUT(T4) = PI_1.

[0062] Step S40 specifically involves:

[0063] Based on the synchronous control of switching transistors T1 and T4, the duty cycle of switching transistor T1 is reduced. Switch T1 is turned off the instant the duty cycle decreases. Switch T2 is turned on due to its complementarity with switching transistor T1, forming the first compensation loop with the path Rload-LP-T2-VBUS_M-VBUS_N-T4-LN. This increases the voltage V_N of capacitor cn so that the bus midpoint voltage VBUS_M can reach balance.

[0064] The output voltage at this time is as follows:

[0065] PI_OUT(T1) = PI_1 - PI_2;

[0066] PI_OUT(T4) = PI_1.

[0067] Step S50 specifically involves:

[0068] Based on the synchronous control of switching transistors T1 and T4, the duty cycle of switching transistor T4 is reduced. Switch T4 is turned off the instant the duty cycle decreases. Switch T3 is turned on due to its complementarity with switching transistor T4, forming a second compensation loop with the path Rload-LP-T1-VBUS_P-VBUS_M-T3-LN. This increases the voltage V_P of capacitor cp so that the bus midpoint voltage VBUS_M can reach balance.

[0069] The output voltage at this time is as follows:

[0070] PI_OUT(T1) = PI_1;

[0071] PI_OUT(T4) = PI_1 - PI_2.

[0072] In summary, the advantages of this invention are as follows:

[0073] By real-time monitoring of the operating state of the three-level circuit topology and the bias direction of the bus midpoint voltage VBUS_M, when the operating state is charging and the bias direction is positive, the first discharge circuit with the path VBUS_P-T1-LP-Rload-LN-T3-VBUS_M is formed by reducing the duty cycle of switch T4 to discharge the voltage V_P of capacitor cp. When the operating state is charging and the bias direction is reverse, the second discharge circuit with the path VBUS_M-T2-LP-Rload-LN-T4-VBUS_N is formed by reducing the duty cycle of switch T1 to discharge the voltage V_N of capacitor cn. When the operating state is discharging and the bias direction is positive, the second discharge circuit with the path Rloa is formed by reducing the duty cycle of switch T1 to discharge the voltage V_N of capacitor cn. The first compensation circuit, d-LP-T2-VBUS_M-VBUS_N-T4-LN, boosts the voltage V_N of capacitor cn. When the operating state is discharge and the bias direction is reversed, the second compensation circuit, formed by reducing the duty cycle of switch T4, with the path Rload-LP-T1-VBUS_P-VBUS_M-T3-LN, boosts the voltage V_P of capacitor cp. That is, regardless of the current operating state and bias direction, it can discharge or boost the voltage of capacitor cp or capacitor cn, keeping the bus midpoint voltage VBUS_M balanced. In other words, it compensates for the offset of the bus midpoint voltage VBUS_M, thereby controlling the bus midpoint voltage and greatly improving the stability of the DC-DC converter.

[0074] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for controlling the neutral point voltage of a three-level DC-DC bus, characterized in that: Includes the following steps: Step S10: Monitor the operating status of the three-level circuit topology and the bias direction of the bus midpoint voltage VBUS_M in real time. When the operating status is charging and the bias direction is positive, proceed to step S20; when the operating status is charging and the bias direction is negative, proceed to step S30; when the operating status is discharging and the bias direction is positive, proceed to step S40; when the operating status is discharging and the bias direction is negative, proceed to step S50. Step S20: Adjust the duty cycle of the switching transistor T4 to discharge the voltage V_P of the capacitor cp; Step S30: Adjust the duty cycle of the switching transistor T1 to discharge the voltage V_N of capacitor cn; Step S40: Adjust the duty cycle of the switching transistor T1 to increase the voltage V_N of the capacitor cn; Step S50: Adjust the duty cycle of the switching transistor T4 to increase the voltage V_P of the capacitor cp; Step S20 specifically involves: Based on the synchronous control of switching transistors T1 and T4, the duty cycle of switching transistor T4 is reduced. Switch T4 is turned off the instant the duty cycle decreases. Switch T3 is turned on due to its complementarity with switching transistor T4, forming the first discharge loop with the path VBUS_P-T1-LP-Rload-LN-T3-VBUS_M. This discharges the voltage V_P of capacitor cp so that the bus midpoint voltage VBUS_M can be balanced.

2. The method for controlling the neutral point voltage of a three-level DC-DC bus as described in claim 1, characterized in that: In step S10, the bias direction of the bus midpoint voltage VBUS_M of the real-time monitoring three-level circuit topology is specifically as follows: The voltage V_P of capacitor cp and the voltage V_N of capacitor cn are monitored in real time. When the voltage V_P is greater than the voltage V_N, the bias direction is positive; when the voltage V_P is less than the voltage V_N, the bias direction is negative.

3. The method for controlling the neutral point voltage of a three-level DC-DC bus as described in claim 1, characterized in that: Step S30 specifically involves: Based on the synchronous control of switching transistors T1 and T4, the duty cycle of switching transistor T1 is reduced. Switch T1 is turned off the instant the duty cycle decreases. Switch T2 is turned on due to its complementarity with switching transistor T1, forming a second discharge circuit with the path VBUS_M-T2-LP-Rload-LN-T4-VBUS_N. This discharges the voltage V_N of capacitor cn so that the bus midpoint voltage VBUS_M can be balanced.

4. The method for controlling the neutral point voltage of a three-level DC-DC bus as described in claim 1, characterized in that: Step S40 specifically involves: Based on the synchronous control of switching transistors T1 and T4, the duty cycle of switching transistor T1 is reduced. Switch T1 is turned off the instant the duty cycle decreases. Switch T2 is turned on due to its complementarity with switching transistor T1, forming the first compensation loop with the path Rload-LP-T2-VBUS_M-VBUS_N-T4-LN. This increases the voltage V_N of capacitor cn so that the bus midpoint voltage VBUS_M can reach balance.

5. The method for controlling the neutral point voltage of a three-level DC-DC bus as described in claim 1, characterized in that: Step S50 specifically involves: Based on the synchronous control of switching transistors T1 and T4, the duty cycle of switching transistor T4 is reduced. Switch T4 is turned off the instant the duty cycle decreases. Switch T3 is turned on due to its complementarity with switching transistor T4, forming a second compensation loop with the path Rload-LP-T1-VBUS_P-VBUS_M-T3-LN. This increases the voltage V_P of capacitor cp so that the bus midpoint voltage VBUS_M can reach balance.

Images