Inductor current multiplexing detection circuit for DC-DC converter, and DC-DC converter

Abstract

Embodiments of this disclosure provide an inductor current multiplexing detection circuit for a DC-DC converter, comprising: first and second resistors, a comparator, a current source circuit, an initialization control circuit, an initialization circuit, a detection control circuit, and first and second current detection circuits. The current source circuit controls the sum of the first and second currents flowing through the first and second resistors to be equal to a constant current. The initialization control circuit generates an initialization signal. The initialization circuit controls the magnitudes of the first and second currents, thereby causing the comparator's output signal to be at a second level. The detection control circuit causes the voltages at the fourth and fifth nodes to be equal to the voltages at the first and second terminals of the freewheeling diode, respectively. The first current detection circuit causes the comparator's output signal to be at a first level when the inductor current is equal to or less than a first threshold current. The second current detection circuit causes the comparator's output signal to be at a first level when the inductor current is equal to or less than a second threshold current.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to an inductor current multiplexing detection circuit for a DC-DC converter, and a DC-DC converter. Background Technology

[0002] With the development of the Internet of Things era, the demand for smart electronic devices has grown rapidly, and DC-DC converters can be found in many of these devices. DC-DC converters include buck converters and boost converters. Buck converters convert higher DC voltages to lower DC voltages. Boost converters convert lower DC voltages to higher DC voltages. When a buck converter operates in discontinuous conduction mode, an inductor current zero-crossing detection circuit is needed to turn off the freewheeling diode when the inductor current is zero. During the switching process to a light load, the output voltage may overshoot or drop, requiring a negative inductor current detection circuit to help the output voltage quickly return to normal. Summary of the Invention

[0003] The embodiments described herein provide an inductor current multiplexing detection circuit for a DC-DC converter, and a DC-DC converter.

[0004] According to a first aspect of this disclosure, an inductor current multiplexing detection circuit for a DC-DC converter is provided. The inductor current multiplexing detection circuit includes: a first resistor, a second resistor, a comparator, a current source circuit, an initialization control circuit, an initialization circuit, a detection control circuit, a first current detection circuit, and a second current detection circuit. A first terminal of the first resistor is coupled to a first terminal and a first voltage terminal of the second resistor. A second terminal of the first resistor is coupled to a first input terminal of the comparator. A second terminal of the second resistor is coupled to a second input terminal of the comparator. The current source circuit is configured to control the sum of a first current flowing through the first resistor and a second current flowing through the second resistor to be equal to a constant current. The initialization control circuit is configured to generate an initialization signal based on a freewheeling diode conduction control signal of the DC-DC converter and provide the initialization signal to the initialization circuit and the detection control circuit via a first node. The initialization circuit is configured to control the magnitudes of the first and second currents via a second node and a third node, respectively, when the initialization signal is at an active level, thereby causing the comparator's output signal to be at a second level. The detection control circuit is configured to, when the initialization signal is at an invalid level, ensure that the voltages of the fourth and fifth nodes are equal to the voltages of the first and second terminals of the freewheeling diode of the DC-DC converter, respectively. The first current detection circuit is configured to, based on the first enable signal and the voltages of the fourth and fifth nodes, control the magnitudes of the first and second currents via the second and third nodes, respectively, so that the comparator's output signal is at a first level when the inductor current of the DC-DC converter is equal to or less than a first threshold current. The second current detection circuit is configured to, based on the second enable signal and the voltages of the fourth and fifth nodes, control the magnitudes of the first and second currents via the second and third nodes, respectively, so that the comparator's output signal is at a first level when the inductor current is equal to or less than a second threshold current.

[0005] In some embodiments of this disclosure, the resistance value of the first resistor is equal to the resistance value of the second resistor.

[0006] In some embodiments of this disclosure, the first input of the comparator is an inverting input. The second input of the comparator is a non-inverting input.

[0007] In some embodiments of this disclosure, the current source circuit includes: a constant current source and a first transistor to a fourth transistor. A first terminal of the constant current source is coupled to a first voltage terminal. A second terminal of the constant current source is coupled to the control electrode and the second electrode of the first transistor, and to the control electrode and the second electrode of the second transistor. The first electrode of the first transistor is coupled to a second node and the first electrode of a third transistor. The first electrode of the second transistor is coupled to a third node and the first electrode of the fourth transistor. The control electrode of the third transistor is coupled to the control electrode of the first transistor. The second electrode of the third transistor is coupled to the second terminal of a first resistor. The control electrode of the fourth transistor is coupled to the control electrode of the second transistor. The second electrode of the fourth transistor is coupled to the second terminal of a second resistor.

[0008] In some embodiments of this disclosure, the first to fourth transistors are bipolar transistors. The emitter junction area of ​​the third transistor is X times the emitter junction area of ​​the first transistor. The emitter junction area of ​​the fourth transistor is X times the emitter junction area of ​​the second transistor. X is greater than or equal to 1.

[0009] In some embodiments of this disclosure, the first to fourth transistors are metal-oxide-semiconductor transistors. The aspect ratio of the third transistor is X times that of the first transistor. The aspect ratio of the fourth transistor is X times that of the second transistor. X is greater than or equal to 1.

[0010] In some embodiments of this disclosure, the initialization control circuit includes a first inverter. The input of the first inverter is provided with a freewheeling diode conduction control signal. The output of the first inverter is coupled to a first node.

[0011] In some embodiments of this disclosure, the initialization circuit includes a third resistor, a fourth resistor, a fifth transistor, and a sixth transistor. The first terminal of the third resistor is coupled to a second node. The second terminal of the third resistor is coupled to the second terminal of the fifth transistor. The first terminal of the fourth resistor is coupled to the third node. The second terminal of the fourth resistor is coupled to the second terminal of the sixth transistor. The control terminal of the fifth transistor is coupled to the first node and the control terminal of the sixth transistor. The first terminal of the fifth transistor is coupled to a second voltage terminal and the first terminal of the sixth transistor.

[0012] In some embodiments of this disclosure, the resistance value of the third resistor is greater than the resistance value of the fourth resistor.

[0013] In some embodiments of this disclosure, the detection control circuit includes a second inverter, a seventh transistor, and an eighth transistor. The input terminal of the second inverter is coupled to a first node. The output terminal of the second inverter is coupled to the control terminals of the seventh and eighth transistors. The first terminal of the seventh transistor is coupled to a fourth node. The second terminal of the seventh transistor is coupled to the first terminal of a freewheeling diode. The first terminal of the eighth transistor is coupled to a fifth node. The second terminal of the eighth transistor is coupled to the second terminal of the freewheeling diode.

[0014] In some embodiments of this disclosure, the first current detection circuit includes a ninth transistor, a tenth transistor, a fifth resistor, and a sixth resistor. The control terminals of the ninth and tenth transistors are provided with a first enable signal. The first terminal of the ninth transistor is coupled to the first end of the fifth resistor. The second terminal of the ninth transistor is coupled to a second node. The first terminal of the tenth transistor is coupled to the first end of the sixth resistor. The second terminal of the tenth transistor is coupled to a third node. The second end of the fifth resistor is coupled to a fourth node. The second end of the sixth resistor is coupled to the fifth node.

[0015] In some embodiments of this disclosure, the resistance value of the fifth resistor is equal to the resistance value of the sixth resistor.

[0016] In some embodiments of this disclosure, the second current detection circuit includes an eleventh transistor, a twelfth transistor, a seventh resistor, and an eighth resistor. The control terminals of the eleventh and twelfth transistors are provided with a second enable signal. The first terminal of the eleventh transistor is coupled to the first terminal of the seventh resistor. The second terminal of the eleventh transistor is coupled to a second node. The first terminal of the twelfth transistor is coupled to the first terminal of the eighth resistor. The second terminal of the twelfth transistor is coupled to a third node. The second terminal of the seventh resistor is coupled to a fourth node. The second terminal of the eighth resistor is coupled to a fifth node.

[0017] In some embodiments of this disclosure, the resistance value of the seventh resistor is less than the resistance value of the eighth resistor.

[0018] In some embodiments of this disclosure, the ratio of the resistance values ​​of the fifth resistor to the sixth resistor is different from the ratio of the resistance values ​​of the seventh resistor to the eighth resistor.

[0019] In some embodiments of this disclosure, the inductor current multiplexing detection circuit further includes at least one third current detection circuit. Each third current detection circuit is configured to control the magnitudes of a first current and a second current via the second and third nodes respectively, based on a third enable signal and the voltages of the fourth and fifth nodes, such that the comparator's output signal is at a first level when the inductor current of the DC-DC converter is equal to or less than a third threshold current. At least one third current detection circuit corresponds to a different third enable signal and a different third threshold current.

[0020] According to a second aspect of this disclosure, an inductor current multiplexing detection circuit for a DC-DC converter is provided. The inductor current multiplexing detection circuit includes: a first resistor to a tenth resistor, a comparator, a constant current source, a first transistor to a fourteenth transistor, a first inverter, and a second inverter. A first terminal of the first resistor is coupled to a first terminal of the second resistor and a first voltage terminal. A second terminal of the first resistor is coupled to a first input terminal of the comparator. A second terminal of the second resistor is coupled to a second input terminal of the comparator. A first terminal of the constant current source is coupled to the first voltage terminal. A second terminal of the constant current source is coupled to the control electrode and the second electrode of the first transistor, and to the control electrode and the second electrode of the second transistor. A first electrode of the first transistor is coupled to a first electrode of the third transistor. A first electrode of the second transistor is coupled to a first electrode of the fourth transistor. The control electrode of the third transistor is coupled to the control electrode of the first transistor. A second electrode of the third transistor is coupled to a second terminal of the first resistor. The control electrode of the fourth transistor is coupled to the control electrode of the second transistor. The second electrode of the fourth transistor is coupled to a second terminal of the second resistor. The input terminal of the first inverter is provided with a freewheeling diode turn-on control signal for the DC-DC converter. The output of the first inverter is coupled to the input of the second inverter. The first terminal of the third resistor is coupled to the first terminal of the third transistor. The second terminal of the third resistor is coupled to the second terminal of the fifth transistor. The first terminal of the fourth resistor is coupled to the first terminal of the fourth transistor. The second terminal of the fourth resistor is coupled to the second terminal of the sixth transistor. The control terminal of the fifth transistor is coupled to the output of the first inverter and the control terminal of the sixth transistor. The first terminal of the fifth transistor is coupled to the second voltage terminal and the first terminal of the sixth transistor. The output of the second inverter is coupled to the control terminals of the seventh and eighth transistors. The first terminal of the seventh transistor is coupled to the second terminals of the fifth, seventh, and ninth resistors. The second terminal of the seventh transistor is coupled to the first terminal of the freewheeling diode of the DC-DC converter. The first terminal of the eighth transistor is coupled to the second terminals of the sixth, eighth, and tenth resistors. The second terminal of the eighth transistor is coupled to the second terminal of the freewheeling diode. The control terminals of the ninth and tenth transistors are provided with a first enable signal. The first terminal of the ninth transistor is coupled to the first terminal of the fifth resistor. The second terminal of the ninth transistor is coupled to the first terminal of the third transistor. The first terminal of the tenth transistor is coupled to the first terminal of the sixth resistor. The second terminal of the tenth transistor is coupled to the first terminal of the fourth transistor. The control terminals of the eleventh and twelfth transistors are provided with a second enable signal. The first terminal of the eleventh transistor is coupled to the first terminal of the seventh resistor. The second terminal of the eleventh transistor is coupled to the first terminal of the third transistor. The first terminal of the twelfth transistor is coupled to the first terminal of the eighth resistor. The second terminal of the twelfth transistor is coupled to the first terminal of the fourth transistor. The control terminals of the thirteenth and fourteenth transistors are provided with a third enable signal. The first terminal of the thirteenth transistor is coupled to the first terminal of the ninth resistor.The second terminal of the thirteenth transistor is coupled to the first terminal of the third transistor. The first terminal of the fourteenth transistor is coupled to the first terminal of the tenth resistor. The second terminal of the fourteenth transistor is coupled to the first terminal of the fourth transistor.

[0021] According to a third aspect of this disclosure, a DC-DC converter is provided. The DC-DC converter includes an inductor current multiplexing detection circuit as described in a first or second aspect of this disclosure.

[0022] In some embodiments of this disclosure, the DC-DC converter is a buck converter. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0024] Figure 1 This is an exemplary circuit diagram of a part of a DC-DC converter;

[0025] Figure 2 This is a schematic block diagram of an inductor current multiplexing detection circuit for a DC-DC converter according to an embodiment of the present disclosure;

[0026] Figure 3 These are exemplary waveforms of some signals used in a DC-DC converter;

[0027] Figure 4 This is an exemplary circuit diagram of an inductor current multiplexing detection circuit for a DC-DC converter according to embodiments of the present disclosure; and

[0028] Figure 5 This is another exemplary circuit diagram of an inductor current multiplexing detection circuit for a DC-DC converter according to embodiments of the present disclosure.

[0029] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0032] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, for the sake of consistency, in this context, the base of a bipolar junction transistor (BJT) is referred to as the control terminal, the emitter of the BJT as the first terminal, and the collector of the BJT as the second terminal. Additionally, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0033] Figure 1 An exemplary circuit diagram of a portion of a DC-DC converter is shown. This DC-DC converter is a buck converter. The DC-DC converter converts the input voltage Vin, which is input at the input terminal, into an output voltage Vout and outputs this output voltage Vout from the output terminal (the upper plate of the output capacitor Cout). When the power transistor turn-on control signal HG is active (high level), the power transistor HS is turned on, and the inductor current IL flowing through the inductor L increases. When the freewheeling transistor turn-on control signal LG is active, the freewheeling transistor LS is turned on, and the inductor current IL flowing through the inductor L decreases. The power transistor turn-on control signal HG and the freewheeling transistor turn-on control signal LG are alternately active to alternately turn on the power transistor HS and the freewheeling transistor LS.

[0034] When the buck converter operates in discontinuous conduction mode, an inductor current zero-crossing detection circuit is required to turn off the freewheeling diode when the inductor current is zero. When the inductor current is zero, the voltage at point SW is equal to the voltage at point PGND. During the switchover to light load, the output voltage may overshoot or overvoltage, requiring a negative inductor current detection circuit to help the output voltage quickly drop back down. When the inductor current is negative, the voltage at point SW is higher than the voltage at point PGND. Therefore, by detecting the voltages at points SW and PGND, zero inductor current detection or negative inductor current detection can be achieved. In some applications, both inductor current zero-crossing detection and negative inductor current detection circuits are needed. Multiplexing these two circuits can adapt to more application scenarios and save hardware resources.

[0035] Embodiments of this disclosure provide an inductor current multiplexing detection circuit for a DC-DC converter. Figure 2 A schematic block diagram of an inductor current multiplexing detection circuit 200 for a DC-DC converter according to an embodiment of the present disclosure is shown. The inductor current multiplexing detection circuit 200 may include: a first resistor R1, a second resistor R2, a comparator COMP, a current source circuit 230, an initialization control circuit 210, an initialization circuit 220, a detection control circuit 240, a first current detection circuit 250, and a second current detection circuit 260.

[0036] The first terminal of the first resistor R1 is coupled to the first terminal of the second resistor R2 and the first voltage terminal V1. The second terminal of the first resistor R1 is coupled to the first input terminal of the comparator COMP. The second terminal of the second resistor R2 is coupled to the second input terminal of the comparator COMP. In some embodiments of this disclosure, the resistance value of the first resistor R1 is equal to the resistance value of the second resistor R2. In some embodiments of this disclosure, the first input terminal Vinn of the comparator COMP is an inverting input terminal. The second input terminal Vinp of the comparator COMP is a non-inverting input terminal.

[0037] The current source circuit 230 can be coupled to the second terminal of the first resistor R1, the second terminal of the second resistor R2, the second node N2, and the third node N3. The current source circuit 230 can be configured to control the first current I flowing through the first resistor R1. R1 and the second current I flowing through the second resistor R2 R2 The sum of these equals the constant current.

[0038] Initialization control circuit 210 can be coupled to the control terminal of the freewheeling diode LS of the DC-DC converter. Initialization control circuit 210 can be coupled to initialization circuit 220 and detection control circuit 240 via first node N1. Initialization control circuit 210 can be configured to generate an initialization signal LGN based on the freewheeling diode turn-on control signal LG of the DC-DC converter, and provide the initialization signal LGN to initialization circuit 220 and detection control circuit 240 via first node N1. In some embodiments of this disclosure, the initialization signal LGN is the inverted signal of the freewheeling diode turn-on control signal LG.

[0039] Initialization circuit 220 can be coupled to initialization control circuit 210 and detection control circuit 240 via first node N1. Initialization circuit 220 can be coupled to current source circuit 230, first current detection circuit 250, and second current detection circuit 260 via second node N2 and third node N3. Initialization circuit 220 can be configured to control the first current I via second node N2 and third node N3 respectively when initialization signal LGN is at an active level. R1 With the second current I R2 The magnitude of the value determines the output signal ZCD&NCD of the comparator COMP, thus placing it at the second level. The effective level of the initialization signal LGN indicates that the inductor current multiplexing detection circuit 200 has entered the initialization state.

[0040] The detection control circuit 240 can be coupled to the first terminal (PGND point) and the second terminal (SW point) of the freewheeling diode LS. The detection control circuit 240 can be coupled to the initialization control circuit 210 and the initialization circuit 220 via the first node N1. The detection control circuit 240 can be coupled to the first current detection circuit 250 and the second current detection circuit 260 via the fourth node N4 and the fifth node N5. The detection control circuit 240 can be configured such that, when the initialization signal LGN is at an invalid level, the voltages of the fourth node N4 and the fifth node N5 are equal to the voltages of the first terminal (PGND point) and the second terminal (SW point) of the freewheeling diode LS of the DC-DC converter, respectively. The invalid level of the initialization signal LGN is used to indicate that the inductor current multiplexing detection circuit 200 enters the detection state.

[0041] The first current detection circuit 250 can be coupled to the detection control circuit 240 and the second current detection circuit 260 via the fourth node N4 and the fifth node N5. The first current detection circuit 250 can also be coupled to the current source circuit 230 and the second current detection circuit 260 via the second node N2 and the third node N3. The first current detection circuit 250 can be configured to control a first current I via the second node N2 and the third node N3 based on the first enable signal VG1 and the voltages of the fourth node N4 and the fifth node N5, respectively. R1 With the second current I R2The magnitude of the current is such that when the inductor current of the DC-DC converter is equal to or less than the first threshold current, the output signal ZCD&NCD of the comparator COMP is at the first level. In some embodiments of this disclosure, the first current detection circuit 250 is enabled (starts operation) when the first enable signal VG1 is at an active level. When the first enable signal VG1 is at an inactive level, the first current detection circuit 250 stops operating. The voltage of the fourth node N4 and the voltage of the fifth node N5 can affect the constant current's influence on the first current I. R1 Second current I R2 The current shunting ratio can be adjusted to control the first current I. R1 With the second current I R2 The magnitude of the threshold current. In some embodiments of this disclosure, the first threshold current may be equal to zero.

[0042] The second current detection circuit 260 can be coupled to the detection control circuit 240 and the first current detection circuit 250 via the fourth node N4 and the fifth node N5. The second current detection circuit 260 can also be coupled to the current source circuit 230 and the first current detection circuit 250 via the second node N2 and the third node N3. The second current detection circuit 260 can be configured to control the first current I via the second node N2 and the third node N3 respectively, based on the second enable signal VG2 and the voltages of the fourth node N4 and the fifth node N5. R1 With the second current I R2 The magnitude of the current is determined such that when the inductor current is equal to or less than the second threshold current, the output signal ZCD&NCD of the comparator COMP is at the first level. In some embodiments of this disclosure, the second current detection circuit 260 is enabled (starts operation) when the second enable signal VG2 is at an active level. When the second enable signal VG2 is at an inactive level, the second current detection circuit 260 stops operating. The voltage of the fourth node N4 and the voltage of the fifth node N5 can affect the constant current's influence on the first current I. R1 Second current I R2 The current shunting ratio can be adjusted to control the first current I. R1 With the second current I R2 The magnitude of the threshold current. In some embodiments of this disclosure, the second threshold current may be negative.

[0043] In some embodiments of this disclosure, the first level is, for example, a high level, and the second level is, for example, a low level.

[0044] Figure 3 Exemplary waveforms of some signals used in a DC-DC converter are shown below. Figure 3 The following example illustrates the operation of the inductor current multiplexing detection circuit 200 according to an embodiment of the present disclosure.

[0045] During the phase when the freewheeling diode turn-on control signal LG is at an invalid level (e.g., before time T1), the freewheeling diode LS is off, the power transistor HS is on, and the inductor current IL rises. During this phase, there is no need to worry about the inductor current dropping to zero or a negative current. The initialization control circuit 210 controls the inductor current multiplexing detection circuit 200 to enter the initialization state. At this time, the initialization circuit 220 operates, and the detection control circuit 240 does not operate. The initialization circuit 220 controls the first current I by controlling a constant current. R1 Second current I R2 The shunt ratio is used to control the first current I. R1 With the second current I R2 The magnitude of the voltage is such that the voltage at the inverting input Vinn of comparator COMP is higher than the voltage at the non-inverting input Vinp of comparator COMP, thus causing the output signal ZCD&NCD of comparator COMP to be at a low level (invalid level).

[0046] During the period when the freewheeling diode turn-on control signal LG is at an active level (e.g., from time T1 to T2), the freewheeling diode LS is turned on, the power transistor HS is turned off, and the inductor current IL decreases. In scenarios requiring zero inductor current detection, the first enable signal VG1 can be at an active level while the second enable signal VG2 is at an inactive level, thus enabling the first current detection circuit 250 and disabling the second current detection circuit 260. When the inductor current is equal to or less than zero (e.g., at time T2), the output signals ZCD&NCD of the comparator COMP are at a high level (active level) to indicate that the inductor current has crossed zero. In this case, the output signals ZCD&NCD of the comparator COMP can be considered as zero-crossing indication signals. The DC-DC converter can turn off the freewheeling diode LS when the zero-crossing indication signal is at an active level to prevent the inductor current from becoming negative.

[0047] although Figure 3 Only the waveforms of the inductor current IL and the voltage at point SW are shown in the scenario of zero inductor current sensing, but it can be seen from... Figure 3Knowing that in a scenario requiring negative inductor current detection, the inductor current drops to a negative value at time T2, and the voltage at point SW rises above the voltage at point PGND. In such a scenario, the second enable signal VG2 can be enabled while the first enable signal VG1 is disabled, thus activating the second current detection circuit 260 and deactivating the first current detection circuit 250. When the inductor current is equal to or less than a preset negative current (e.g., -4A) (e.g., at time T2), the output signal ZCD&NCD of comparator COMP is high (active level) to indicate that the inductor current has fallen to the preset negative current. In this case, the output signal ZCD&NCD of comparator COMP can be considered a negative current indication signal. The DC-DC converter can turn off the freewheeling diode LS when the negative current indication signal is active to help the output voltage of the DC-DC converter quickly drop back, mitigating overshoot or overvoltage.

[0048] Furthermore, in scenarios where zero inductor current detection and negative inductor current detection need to be performed alternately, the output signal ZCD&NCD of comparator COMP can be reset to a low level by initialization circuit 220 to prevent the output signal ZCD&NCD of comparator COMP from having an uncertain state.

[0049] Figure 4 An exemplary circuit diagram of an inductor current multiplexing detection circuit 400 for a DC-DC converter according to an embodiment of the present disclosure is shown.

[0050] The current source circuit 430 may include: a constant current source 431, and first transistors Q1 to fourth transistors Q4. The first terminal of the constant current source 431 is coupled to a first voltage terminal V1. The second terminal of the constant current source 431 is coupled to the control and second terminals of the first transistor Q1 and the second transistor Q2. The first terminal of the first transistor Q1 is coupled to the second node N2 and the first terminal of the third transistor Q3. The first terminal of the second transistor Q2 is coupled to the third node N3 and the first terminal of the fourth transistor Q4. The control terminal of the third transistor Q3 is coupled to the control terminal of the first transistor Q1. The second terminal of the third transistor Q3 is coupled to the second terminal of the first resistor R1. The control terminal of the fourth transistor Q4 is coupled to the control terminal of the second transistor Q2. The second terminal of the fourth transistor Q4 is coupled to the second terminal of the second resistor R2. The first transistor Q1 and the third transistor Q3 form a current mirror. The second transistor Q2 and the fourth transistor Q4 form another current mirror.

[0051] In some embodiments of this disclosure, the constant current source 431 can provide a current of 2×Ib to the first transistor Q1 and the second transistor Q2.

[0052] In some embodiments of this disclosure, the first transistor Q1 to the fourth transistor Q4 are bipolar transistors. The emitter junction area of ​​the third transistor Q3 is X times the emitter junction area of ​​the first transistor Q1. The emitter junction area of ​​the fourth transistor Q4 is X times the emitter junction area of ​​the second transistor Q2. The current I3 flowing through the third transistor Q3 is X times the current I1 flowing through the first transistor Q1. The current I4 flowing through the fourth transistor Q4 is X times the current I2 flowing through the second transistor Q2. X is greater than or equal to 1. Thus, the first current I flowing through the first resistor R1... R1 The second current I flowing through the second resistor R2 R2 The sum of these is a constant current 2×X×Ib.

[0053] In some embodiments of this disclosure, the first transistor Q1 to the fourth transistor Q4 are metal-oxide-semiconductor (MOS) transistors. The aspect ratio of the third transistor Q3 is X times that of the first transistor Q1. The aspect ratio of the fourth transistor Q4 is X times that of the second transistor Q2. The current I3 flowing through the third transistor Q3 is X times that of the current I1 flowing through the first transistor Q1. The current I4 flowing through the fourth transistor Q4 is X times that of the current I2 flowing through the second transistor Q2. X is greater than or equal to 1. Thus, the first current I flowing through the first resistor R1... R1 The second current I flowing through the second resistor R2 R2 The sum is a constant current 2 × X × Ib. Since the area of ​​a MOS transistor is smaller than that of a bipolar transistor, using MOS transistors to implement the first transistor Q1 to the fourth transistor Q4 can save chip area in the DC-DC converter.

[0054] The initialization control circuit 410 may include a first inverter INV1. The input terminal of the first inverter INV1 is provided with a freewheeling diode on-control signal LG. The output terminal of the first inverter INV1 is coupled to a first node N1.

[0055] The initialization circuit 420 may include: a third resistor R3, a fourth resistor R4, a fifth transistor M5, and a sixth transistor M6. The first terminal of the third resistor R3 is coupled to the second node N2. The second terminal of the third resistor R3 is coupled to the second terminal of the fifth transistor M5. The first terminal of the fourth resistor R4 is coupled to the third node N3. The second terminal of the fourth resistor R4 is coupled to the second terminal of the sixth transistor M6. The control terminal of the fifth transistor M5 is coupled to the first node N1 and the control terminal of the sixth transistor M6. The first terminal of the fifth transistor M5 is coupled to the second voltage terminal V2 and the first terminal of the sixth transistor M6.

[0056] In some embodiments of this disclosure, the resistance value of the third resistor R3 is greater than the resistance value of the fourth resistor R4.

[0057] The detection control circuit 440 may include: a second inverter INV2, a seventh transistor M7, and an eighth transistor M8. The input terminal of the second inverter INV2 is coupled to the first node N1. The output terminal of the second inverter INV2 is coupled to the control terminals of the seventh transistor M7 and the eighth transistor M8. The first terminal of the seventh transistor M7 is coupled to the fourth node N4. The second terminal of the seventh transistor M7 is coupled to the first terminal (PGND point) of the freewheeling diode LS. The first terminal of the eighth transistor M8 is coupled to the fifth node N5. The second terminal of the eighth transistor M8 is coupled to the second terminal (SW point) of the freewheeling diode LS.

[0058] The first current detection circuit 450 may include: a ninth transistor M9, a tenth transistor M10, a fifth resistor R5, and a sixth resistor R6. The control terminals of the ninth transistor M9 and the tenth transistor M10 are provided with a first enable signal VG1. The first terminal of the ninth transistor M9 is coupled to the first end of the fifth resistor R5. The second terminal of the ninth transistor M9 is coupled to the second node N2. The first terminal of the tenth transistor M10 is coupled to the first end of the sixth resistor R6. The second terminal of the tenth transistor M10 is coupled to the third node N3. The second end of the fifth resistor R5 is coupled to the fourth node N4. The second end of the sixth resistor R6 is coupled to the fifth node N5.

[0059] In some embodiments of this disclosure, the resistance value of the fifth resistor R5 is equal to the resistance value of the sixth resistor R6.

[0060] The second current detection circuit 460 may include: an eleventh transistor M11, a twelfth transistor M12, a seventh resistor R7, and an eighth resistor R8. The control terminals of the eleventh transistor M11 and the twelfth transistor M12 are provided with a second enable signal VG2. The first terminal of the eleventh transistor M11 is coupled to the first terminal of the seventh resistor R7. The second terminal of the eleventh transistor M11 is coupled to the second node N2. The first terminal of the twelfth transistor M12 is coupled to the first terminal of the eighth resistor R8. The second terminal of the twelfth transistor M12 is coupled to the third node N3. The second terminal of the seventh resistor R7 is coupled to the fourth node N4. The second terminal of the eighth resistor R8 is coupled to the fifth node N5.

[0061] In some embodiments of this disclosure, the resistance value of the seventh resistor R7 is less than the resistance value of the eighth resistor R8.

[0062] In some embodiments of this disclosure, the ratio of the resistance values ​​of the fifth resistor R5 to the sixth resistor R6 is different from the ratio of the resistance values ​​of the seventh resistor R7 to the eighth resistor R8.

[0063] When the freewheeling diode turn-on control signal LG is low, the freewheeling diode LS is off, the power transistor HS is on, and the inductor current IL rises. The initialization signal LGN output by the first inverter INV1 is high. The inductor current multiplexing detection circuit 400 enters the initialization state. At this time, the fifth transistor M5 and the sixth transistor M6 are on. The high-level initialization signal LGN is input to the second inverter INV2, thereby controlling the seventh transistor M7 and the eighth transistor M8 to turn off. By setting the resistance value of the third resistor R3 to be greater than the resistance value of the fourth resistor R4, the first current I flowing through the first resistor R1 can be increased. R1 The second current I flowing through the second resistor R2 is less than R2 Since the resistance of the first resistor R1 is equal to the resistance of the second resistor R2, the voltage at the inverting input Vinn of comparator COMP is higher than the voltage at the non-inverting input Vinp of comparator COMP, thus causing the output signal ZCD&NCD of comparator COMP to be at a low level.

[0064] When the freewheeling diode conduction control signal LG is high, the freewheeling diode LS is turned on, the power transistor HS is turned off, and the inductor current IL decreases. The initialization signal LGN output by the first inverter INV1 is low. The inductor current multiplexing detection circuit 400 enters the detection state. At this time, the fifth transistor M5 and the sixth transistor M6 are turned off. The low-level initialization signal LGN is input to the second inverter INV2, thereby controlling the seventh transistor M7 and the eighth transistor M8 to turn on. Therefore, the voltage at the fourth node N4 is equal to the voltage at point PGND. The voltage at the fifth node N5 is equal to the voltage at point SW. If the first enable signal VG1 is high and the second enable signal VG2 is low, then the ninth transistor M9 and the tenth transistor M10 are turned on, and the eleventh transistor M11 and the twelfth transistor M12 are turned off. Without considering the DC on-resistance of the seventh transistor M7 to the tenth transistor M10, the voltage V at the second node N2 can be calculated as follows. N2 and the voltage V at the third node N3 N3 :

[0065] V N2 =V PGND +(I1+I3)×R5=V PGND +(X+1)×I1×R5 (1)

[0066] V N3 =V SW +(I2+I4)×R6=V SW +(X+1)×I2×R6 (2)

[0067] Among them, V PGND This represents the voltage at point PGND, V.SW R5 represents the voltage at point SW, R6 represents the resistance value of the fifth resistor R5, and R6 represents the resistance value of the sixth resistor R6.

[0068] refer to Figure 1 When the freewheeling diode LS is turned on, the voltage V at point SW is... SW The calculation can be performed as follows:

[0069] V SW =V PGND -IL×RdsonL (3)

[0070] Where RdsonL represents the DC on-resistance of the freewheeling diode LS, and IL represents the inductor current. Combining equations (2) and (3), the voltage at the third node N3 can be obtained as follows:

[0071] V N3 =V PGND +(X+1)×I2×R6-IL×RdsonL (4)

[0072] The resistance value of the fifth resistor R5 can be designed to be equal to the resistance value of the sixth resistor R6, so that zero inductive current detection can be performed in this case (see example). Figure 3 (The waveform diagram is shown). At time T1, the freewheeling transistor LS starts to conduct, and the inductor current IL is positive at this time. According to equation (3), since the freewheeling transistor LS has a DC on-resistance RdsonL, the voltage at point SW is less than the voltage at point PGND. Therefore, the voltage V at the third node N3 is... N3 The voltage V below the second node N2 N2 The second current I R2 Greater than the first current I R1 The voltage Vinp at the non-inverting input Vinp of comparator COMP is lower than the voltage Vinn at the inverting input Vinn, so the output signals ZCD & NCD of comparator COMP remain low. As the inductor current IL gradually decreases, the voltage at point SW rises, and the voltage V at the third node N3... N3 It also rises. When the voltage V at the third node N3... N3 Equal to the voltage V at the second node N2 N2 At that time, the second current I R2 Equal to the first current I R1 And both are equal to X×Ib, so the voltages at the two input terminals of comparator COMP are equal. The output signal ZCD&NCD of comparator COMP flips to a high level, indicating that zero inductor current is detected. Equating equations (1) and (2) yields:

[0073] (X+1)×Ib×(R6-R5)=IL×RdsonL (5)

[0074] Since R5 = R6, the inductor current IL detected by the inductor current multiplexing detection circuit 400 is 0A, indicating that the inductor current multiplexing detection circuit 400 has achieved zero inductor current detection.

[0075] If the second enable signal VG2 is high and the first enable signal VG1 is low, then the ninth transistor M9 and the tenth transistor M10 are turned off, and the eleventh transistor M11 and the twelfth transistor M12 are turned on. Referring to equation (5), if the resistance value of the eighth resistor R8 is designed to be lower than that of the seventh resistor R7, then the value of IL can be calculated to be negative, thereby enabling the inductor current multiplexing detection circuit 400 to achieve negative inductor current detection.

[0076] exist Figure 4 Based on the example shown, the inductor current multiplexing detection circuit may further include at least one third current detection circuit 570. Each third current detection circuit 570 is configured to control a first current I via a second node N2 and a third node N3 based on the voltages of a third enable signal VG3, a fourth node N4, and a fifth node N5, respectively. R1 With the second current I R2 The magnitude of the third threshold current is determined so that when the inductor current IL of the DC-DC converter is equal to or less than the third threshold current, the output signal ZCD&NCD of the comparator COMP is at the first level. In this context, the third threshold current does not refer to a specific current value, but rather to current values ​​other than the first and second threshold currents. The third enable signal VG3 does not refer to a specific enable signal, but rather to enable signals other than the first enable signal VG1 and the second enable signal VG2. In cases where the at least one third current detection circuit includes multiple third current detection circuits, these multiple third current detection circuits can correspond to different third enable signals VG3 and third threshold currents. Figure 5 An exemplary circuit diagram of an inductor current multiplexing detection circuit 500, including a third current detection circuit 570, is shown. Figure 5 The ellipsis indicates that there may be more third current detection circuits.

[0077] The third current detection circuit 570 may include: a thirteenth transistor M13, a fourteenth transistor M14, a ninth resistor R9, and a tenth resistor R10. The control terminals of the thirteenth transistor M13 and the fourteenth transistor M14 are provided with a third enable signal VG3. The first terminal of the thirteenth transistor M13 is coupled to the first terminal of the ninth resistor R9. The second terminal of the thirteenth transistor M13 is coupled to the second node N2. The first terminal of the fourteenth transistor M14 is coupled to the first terminal of the tenth resistor R10. The second terminal of the fourteenth transistor M14 is coupled to the third node N3. The second terminal of the ninth resistor R9 is coupled to the fourth node N4. The second terminal of the tenth resistor R10 is coupled to the fifth node N5.

[0078] As shown in Equation (5), if the resistance value of the tenth resistor R10 is designed to be lower than that of the ninth resistor R9, the value of IL can be calculated to be negative, thus enabling the inductor current multiplexing detection circuit 500 to detect negative inductor current. By designing the resistance difference between the tenth resistor R10 and the ninth resistor R9 to be different from the resistance difference between the eighth resistor R8 and the seventh resistor R7, different negative inductor currents can be detected. In this way, the function of detecting multiple negative inductor currents can be realized through one inductor current multiplexing detection circuit 500.

[0079] In the example disclosed herein, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The fifth transistor M5 through the fourteenth transistor M14 are NMOS switching transistors. Those skilled in the art will understand that, based on the above inventive concept... Figure 4 or Figure 5 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 4 or Figure 5 The examples shown have different settings.

[0080] The inductor current multiplexing detection circuit according to the embodiments of this disclosure can realize the function of multiplexing zero inductor current detection with one or more negative inductor current detections, so that zero inductor current detection and one or more negative inductor current detections can be easily switched, and hardware resources can be saved and the chip area of ​​DC-DC converter can be reduced.

[0081] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0082] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0083] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. An inductor current multiplexing detection circuit for a DC-DC converter, comprising: The circuit includes a first resistor, a second resistor, a comparator, a current source circuit, an initialization control circuit, an initialization circuit, a detection control circuit, a first current detection circuit, and a second current detection circuit. Wherein, the first end of the first resistor is coupled to the first end of the second resistor and the first voltage terminal, and the second end of the first resistor is coupled to the first input terminal of the comparator; The second terminal of the second resistor is coupled to the second input terminal of the comparator; The current source circuit is configured to control the sum of the first current flowing through the first resistor and the second current flowing through the second resistor to be equal to a constant current; The initialization control circuit is configured to generate an initialization signal based on the freewheeling diode conduction control signal of the DC-DC converter, and provide the initialization signal to the initialization circuit and the detection control circuit via the first node; The initialization circuit is configured to: when the initialization signal is at an active level, control the magnitudes of the first current and the second current via the second node and the third node respectively, thereby causing the output signal of the comparator to be at the second level; the initialization circuit is coupled to the initialization control circuit and the detection control circuit via the first node, and coupled to the current source circuit, the first current detection circuit and the second current detection circuit via the second node and the third node. The detection control circuit is configured such that, when the initialization signal is at an invalid level, the voltages of the fourth node and the fifth node are equal to the voltages of the first and second terminals of the freewheeling diode of the DC-DC converter, respectively. The first current detection circuit is configured to: control the magnitudes of the first current and the second current via the second node and the third node respectively, based on the first enable signal and the voltages of the fourth node and the fifth node, such that the output signal of the comparator is at a first level when the inductor current of the DC-DC converter is equal to or less than the first threshold current; the first current detection circuit is coupled to the detection control circuit and the second current detection circuit via the fourth node and the fifth node, and coupled to the current source circuit and the second current detection circuit via the second node and the third node; The second current detection circuit is configured to: control the magnitudes of the first current and the second current via the second node and the third node respectively, based on the second enable signal and the voltages of the fourth node and the fifth node, such that the output signal of the comparator is at the first level when the inductor current is equal to or less than the second threshold current; the second current detection circuit is coupled to the detection control circuit and the first current detection circuit via the fourth node and the fifth node, and coupled to the current source circuit and the first current detection circuit via the second node and the third node.

2. The inductor current multiplexing detection circuit according to claim 1, wherein, The current source circuit includes: a constant current source, and a first transistor to a fourth transistor. Wherein, the first end of the constant current source is coupled to the first voltage terminal, and the second end of the constant current source is coupled to the control electrode and the second electrode of the first transistor, as well as the control electrode and the second electrode of the second transistor. The first terminal of the first transistor is coupled to the second node and the first terminal of the third transistor; The first terminal of the second transistor is coupled to the third node and the first terminal of the fourth transistor; The control electrode of the third transistor is coupled to the control electrode of the first transistor, and the second electrode of the third transistor is coupled to the second terminal of the first resistor; The control electrode of the fourth transistor is coupled to the control electrode of the second transistor, and the second electrode of the fourth transistor is coupled to the second terminal of the second resistor.

3. The inductor current multiplexing detection circuit according to claim 1, wherein, The initialization control circuit includes: a first inverter, The input terminal of the first inverter is provided with the freewheeling tube conduction control signal, and the output terminal of the first inverter is coupled to the first node.

4. The inductor current multiplexing detection circuit according to claim 1, wherein, The initialization circuit includes: a third resistor, a fourth resistor, a fifth transistor, and a sixth transistor. Wherein, the first end of the third resistor is coupled to the second node, and the second end of the third resistor is coupled to the second electrode of the fifth transistor; The first end of the fourth resistor is coupled to the third node, and the second end of the fourth resistor is coupled to the second terminal of the sixth transistor; The control electrode of the fifth transistor is coupled to the first node and the control electrode of the sixth transistor, and the first electrode of the fifth transistor is coupled to the second voltage terminal and the first electrode of the sixth transistor.

5. The inductor current multiplexing detection circuit according to claim 1, wherein, The detection control circuit includes: a second inverter, a seventh transistor, and an eighth transistor. The input terminal of the second inverter is coupled to the first node, and the output terminal of the second inverter is coupled to the control terminal of the seventh transistor and the control terminal of the eighth transistor. The first terminal of the seventh transistor is coupled to the fourth node, and the second terminal of the seventh transistor is coupled to the first terminal of the freewheeling diode; The first terminal of the eighth transistor is coupled to the fifth node, and the second terminal of the eighth transistor is coupled to the second terminal of the freewheeling diode.

6. The inductor current multiplexing detection circuit according to claim 1, wherein, The first current detection circuit includes: a ninth transistor, a tenth transistor, a fifth resistor, and a sixth resistor. The control electrodes of the ninth transistor and the tenth transistor are provided with the first enable signal. The first electrode of the ninth transistor is coupled to the first terminal of the fifth resistor, and the second electrode of the ninth transistor is coupled to the second node. The first terminal of the tenth transistor is coupled to the first terminal of the sixth resistor, and the second terminal of the tenth transistor is coupled to the third node; The second end of the fifth resistor is coupled to the fourth node; The second end of the sixth resistor is coupled to the fifth node.

7. The inductor current multiplexing detection circuit according to claim 1, wherein, The second current detection circuit includes: an eleventh transistor, a twelfth transistor, a seventh resistor, and an eighth resistor. The control terminals of the eleventh transistor and the twelfth transistor are provided with the second enable signal. The first terminal of the eleventh transistor is coupled to the first terminal of the seventh resistor, and the second terminal of the eleventh transistor is coupled to the second node. The first terminal of the twelfth transistor is coupled to the first terminal of the eighth resistor, and the second terminal of the twelfth transistor is coupled to the third node; The second end of the seventh resistor is coupled to the fourth node; The second end of the eighth resistor is coupled to the fifth node.

8. The inductor current multiplexing detection circuit according to claim 1 further includes: At least one third current detection circuit, Each third current detection circuit is configured to control the magnitude of the first current and the second current via the second node and the third node respectively according to the third enable signal, the voltage of the fourth node and the fifth node, so that the output signal of the comparator is at the first level when the inductor current of the DC-DC converter is equal to or less than the third threshold current. The at least one third current detection circuit corresponds to different third enable signals and third threshold currents.

9. An inductor current multiplexing detection circuit for a DC-DC converter, comprising: The circuit consists of resistors 1 through 10, a comparator, a constant current source, transistors 1 through 14, a first inverter, and a second inverter. Wherein, the first end of the first resistor is coupled to the first end of the second resistor and the first voltage end, and the second end of the first resistor is coupled to the first input end of the comparator; The second terminal of the second resistor is coupled to the second input terminal of the comparator; The first end of the constant current source is coupled to the first voltage terminal, and the second end of the constant current source is coupled to the control electrode and the second electrode of the first transistor, as well as the control electrode and the second electrode of the second transistor. The first terminal of the first transistor is coupled to the first terminal of the third transistor; The first terminal of the second transistor is coupled to the first terminal of the fourth transistor; The control electrode of the third transistor is coupled to the control electrode of the first transistor, and the second electrode of the third transistor is coupled to the second terminal of the first resistor; The control electrode of the fourth transistor is coupled to the control electrode of the second transistor, and the second electrode of the fourth transistor is coupled to the second terminal of the second resistor; The input terminal of the first inverter is provided with the freewheeling diode turn-on control signal of the DC-DC converter, and the output terminal of the first inverter is coupled to the input terminal of the second inverter; The first end of the third resistor is coupled to the first electrode of the third transistor, and the second end of the third resistor is coupled to the second electrode of the fifth transistor. The first end of the fourth resistor is coupled to the first terminal of the fourth transistor, and the second end of the fourth resistor is coupled to the second terminal of the sixth transistor. The control electrode of the fifth transistor is coupled to the output terminal of the first inverter and the control electrode of the sixth transistor, and the first electrode of the fifth transistor is coupled to the second voltage terminal and the first electrode of the sixth transistor; The output of the second inverter is coupled to the control electrode of the seventh transistor and the control electrode of the eighth transistor; The first terminal of the seventh transistor is coupled to the second terminal of the fifth resistor, the second terminal of the seventh resistor, and the second terminal of the ninth resistor; the second terminal of the seventh transistor is coupled to the first terminal of the freewheeling diode of the DC-DC converter. The first terminal of the eighth transistor is coupled to the second terminal of the sixth resistor, the second terminal of the eighth resistor, and the second terminal of the tenth resistor; the second terminal of the eighth transistor is coupled to the second terminal of the freewheeling diode. The control terminals of the ninth transistor and the tenth transistor are provided with a first enable signal, the first terminal of the ninth transistor is coupled to the first terminal of the fifth resistor, and the second terminal of the ninth transistor is coupled to the first terminal of the third transistor; The first terminal of the tenth transistor is coupled to the first terminal of the sixth resistor, and the second terminal of the tenth transistor is coupled to the first terminal of the fourth transistor; The control terminals of the eleventh transistor and the twelfth transistor are provided with a second enable signal. The first terminal of the eleventh transistor is coupled to the first terminal of the seventh resistor, and the second terminal of the eleventh transistor is coupled to the first terminal of the third transistor. The first terminal of the twelfth transistor is coupled to the first terminal of the eighth resistor, and the second terminal of the twelfth transistor is coupled to the first terminal of the fourth transistor; The control terminals of the thirteenth transistor and the fourteenth transistor are provided with a third enable signal. The first terminal of the thirteenth transistor is coupled to the first terminal of the ninth resistor, and the second terminal of the thirteenth transistor is coupled to the first terminal of the third transistor. The first terminal of the fourteenth transistor is coupled to the first terminal of the tenth resistor, and the second terminal of the fourteenth transistor is coupled to the first terminal of the fourth transistor.

10. A DC-DC converter, comprising an inductor current multiplexing detection circuit according to any one of claims 1 to 9.

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