High speed variable pulse width amplitude signal synthesis circuit

Abstract

The application provides a high-speed variable pulse width amplitude signal synthesis circuit, wherein x+1 DAC digital-to-analog conversion circuits are connected to x+1 differential switch circuits through x+1 constant current circuits, and then the signals are output through a load resistor; an FPGA / CPLD circuit generates x differential signals to x PECL circuits, each of the PECL circuits generates two differential signal pulses to input into a corresponding differential switch circuit; the last differential switch circuit inputs a non-differential I / O direct current signal to control the lower limit value of the overall signal, and is used for generating an initial current of a pulsed laser; and the DAC digital-to-analog conversion circuit generates a plurality of voltage signals for current setting through an SPI signal of an MCU. The application realizes the functions of adjustable pulse width, multiple pulses and adjustable amplitude of the super-low rising edge and falling edge signals of the pulse signal light seed source in the MOPA pulsed laser.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of electronics and laser technology, in particular to a high-speed variable pulse width amplitude signal synthesis circuit, and relates to the application of programmable signals and high-speed pulse seed sources. BACKGROUND

[0002] In the application of MOPA pulse laser, it has the characteristics of high conversion efficiency, low laser threshold, simple structure, flexible medium, easy to use, high beam quality, multiple spectral lines, wide tuning range, small size, light weight, good heat dissipation effect and long service life, etc. It is widely used in laser micro welding technology, laser deburring, laser micro hole processing and other fields.

[0003] The signal light seed source with high beam quality is an important part of the MOPA pulse laser structure. Different pulse width lasers have different applications, which requires the signal light seed source to have a pulse width adjustable function; different applications such as double pulse, triple pulse, and even multiple pulse application scenarios require the signal light seed source to have a multiple pulse combination function; in the multi-stage pumping amplification process, the amplified energy will be attenuated, showing a phenomenon of high front and low back, which requires the signal light seed source to have an amplitude adjustable function.

[0004] The traditional op amp + MOS constant current circuit generates constant current through DAC, and forcibly pulls down the DAC op amp input by turning off the DAC output to realize variable pulse width amplitude signal synthesis. But it has two obvious defects and deficiencies:

[0005] Firstly, the change of DAC output value is limited by the conversion rate of DAC device, and the speed can only reach several hundred K. High conversion rate DAC devices cost much more, and increasing the conversion bits of DAC also affects its conversion rate. The above limits the pulse circuit generated by DAC output to only microsecond level, including the pulse circuit generated by the signal generator.

[0006] The second limitation is that the MOS in the front end of the op amp needs to use a high-speed MOS. To make the MOS tube work in a high-speed switching state, a certain driving voltage and load capacity are required, which also limits the rise time and fall time of the driving signal pulse signal, making it impossible to achieve nanosecond rise and fall edges.

[0007] In order to realize the pulse width adjustable, multiple pulse, amplitude adjustable function of the ultra-low rise and fall edge signal of the pulse signal light seed source in the MOPA pulse laser, a high-speed pulse driving signal is needed to achieve a rise and fall edge of 1 nanosecond. SUMMARY

[0008] In view of defects and shortcomings of the prior art, the application provides a high-speed variable pulse width amplitude signal synthesis circuit to realize the functions of pulse width adjustment, multi-pulse and amplitude adjustment of the ultra-low rising edge and falling edge signals of a pulse signal light seed source in a MOPA pulse laser.

[0009] The design goals include:

[0010] 1. The high-speed pulse signal has an ultra-low rising edge time and falling edge time of 1 nanosecond;

[0011] 2. The high-speed FPGA / CPLD device is used to realize self-defined different pulse widths of multiple channels;

[0012] 3. The multiple output pulse signals realize different amplitudes;

[0013] 4. Signals with different pulse widths or different amplitudes are combined with each other;

[0014] 5. The above functions can be programmed and controlled by software.

[0015] The application specifically adopts the following technical solutions:

[0016] The high-speed variable pulse width amplitude signal synthesis circuit is characterized by an FPGA / CPLD circuit, a PECL circuit, a constant current circuit, a differential switch circuit and a load resistor.

[0017] x+1 DAC digital-to-analog conversion circuits are connected to x+1 differential switch circuits through x+1 constant current circuits, and then the synthesized signals are output through load resistors;

[0018] The FPGA / CPLD circuit generates x differential signals to x PECL circuits, each of which generates 2 differential signal pulses and inputs the pulses into a corresponding differential switch circuit; the last differential switch circuit inputs a non-differential I / O direct current signal to control the lower limit value of the overall signal, and is used to generate an initial current of a pulse laser;

[0019] The DAC digital-to-analog conversion circuit generates multiple voltage signals for current setting through SPI signals of an MCU.

[0020] Further, the DAC digital-to-analog conversion circuit is used to provide a setting voltage for the subsequent constant current circuit, and only needs to output a constant voltage signal, without generating a variable analog signal.

[0021] Further, the constant current circuit is used to generate pulse signals with different amplitudes, and the amplitude voltage of the pulse = the output current of the constant current circuit x the load resistor; the output current of the constant current circuit is set by the voltage signal output by the DAC digital-to-analog conversion circuit, so as to realize variable setting of the pulse with different amplitudes.

[0022] Further, the differential switching circuit is used to make the constant current output of the constant current drive not affect its rising edge and falling edge, so that its rising edge and falling edge can be controlled within 1 nanosecond; and the constant current pulse signals of the multi-way output directly act on the load resistance, so that the high-speed driving signals of directly synthesized output multi-pulse, different amplitude and different pulse width are realized.

[0023] Further, the differential switching circuit adopts a differential high-speed transistor switching circuit.

[0024] Further, the FPGA / CPLD circuit adopts a 400MHz main frequency FPGA or CPLD, which meets the minimum high-speed differential pulse signal with a pulse width of 2.5ns, so as to realize the output of high-speed differential pulse signals with different pulse widths and phases for the later-stage driving and signal synthesis.

[0025] Further, the PECL circuit is used to shape the high-speed differential pulse signals output by the front-stage FPGA / CPLD circuit, so as to improve the load capacity and expand the differential pulse signals.

[0026] Compared with the prior art, the present application and the preferred scheme thereof realize the functions of adjustable pulse width, multi-pulse and adjustable amplitude of the ultra-low rising edge and falling edge signals of the pulse signal light seed source in the MOPA pulse laser, and the combination of multi-way different pulse widths or different amplitude signals can be completely controlled by the upper computer, instead of using the fixed output of the hardware circuit, so that the programmable control is realized. BRIEF DESCRIPTION OF DRAWINGS

[0027] The present application will be further described in detail below in combination with the drawings and specific embodiments:

[0028] Figure 1 The figure is a schematic diagram of the structure and working principle of the high-speed variable pulse width and amplitude signal synthesis circuit of the embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the features and advantages of the patent more obvious and easy to understand, the following embodiments are specifically described as follows:

[0030] In order to make the features and advantages of the patent more obvious and easy to understand, the following embodiments are specifically described as follows:

[0031] It should be noted that the following detailed description is exemplary in nature and is intended to provide further description of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0032] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0033] As shown in Figure 1 The embodiment provides a high-speed variable pulse width amplitude signal synthesis circuit. It is composed of FPGA / CPLD circuit, PECL circuit, DAC digital-to-analog conversion circuit, constant current circuit, differential switch circuit, and load resistance. The main purpose is to generate adjustable amplitude high-speed pulse drive signal, so that the switch speed reaches 1 nanosecond ultra-low rising and falling edge, and different size pulse width signals can be set. Different amplitude or different pulse width signals are combined with each other to realize the functions of pulse width adjustment, multi-pulse, and amplitude adjustment of the ultra-low rising and falling edge signal of the pulse signal light seed source in the MOPA pulse laser, and it can be further expanded to meet the needs of different application scenarios.

[0034] Among them, the FPGA / CPLD circuit uses a 400MHz main frequency FPGA or CPLD, which can generate a high-speed differential pulse signal with a minimum pulse width of 2.5ns to realize the output of multiple high-speed differential pulse signals with different pulse widths and phases for driving and signal synthesis in the next stage.

[0035] The PECL circuit is used to shape the high-speed differential pulse signal output by the previous FPGA / CPLD and improve the load capacity. It can expand multiple differential pulse signals (1, 2,..., x).

[0036] The DAC digital-to-analog conversion circuit is used to provide a set voltage for the constant current circuit in the next stage. It only needs to output a constant voltage signal and does not need to generate a variable analog signal, so there is no high requirement for the conversion rate of the DAC device, solving the problem of high conversion rate DAC device in the prior art. The DAC digital-to-analog conversion circuit generates multiple voltage signals for current setting through SPI signal setting of the MCU.

[0037] The constant current circuit is used to generate pulse signals with different amplitudes, and the amplitude voltage of the pulse = the output current of the constant current circuit x the load resistance. The output current of the constant current circuit is set by the voltage signal output by the DAC digital-to-analog conversion circuit to achieve variable setting of the different amplitude pulses in the present scheme.

[0038] The main purpose of the differential switching circuit is to make the constant current output of the constant current circuit not affect the rising edge and falling edge, so that the rising edge and falling edge can be controlled within 1 nanosecond. The differential high-speed transistor switching circuit is mainly used to achieve the above requirements, and the multi-output constant current pulse signals can all directly act on the load resistance to realize the direct synthesis of output multi-pulse, different amplitude, different pulse width high-speed drive signals. The non-differential I / O direct current signal control lower limit value of the whole signal can be realized to generate an initial current of a pulse laser.

[0039] The above description of the embodiments is only used to help understand the method of the present application and its core idea. At the same time, the above is only the preferred embodiment of the present application, and is not a limitation on other forms of the present application. Any skilled person in the art can use the above disclosed technical content to make changes or modifications as equivalent embodiments. However, any simple modification, equivalent change and modification made according to the technical essence of the present application to the above embodiments without departing from the technical scheme content of the present application still belongs to the protection scope of the present application.

Claims

1. A high-speed variable pulse width amplitude signal synthesis circuit, characterized in that: x+1 DAC digital-to-analog conversion circuits are connected to x+1 differential switch circuits through x+1 constant current circuits, and then output a synthesized signal through a load resistor; FPGA / CPLD circuits generate x differential signals to x PECL circuits, each of which generates 2 differential signal pulses to enter a corresponding differential switch circuit; the last differential switch circuit is connected to a non-differential I / O DC signal to control the lower limit value of the overall signal, used to generate an initial current for a pulsed laser; The DAC digital-to-analog conversion circuit generates a plurality of voltage signals for current setting through SPI signals from an MCU; The DAC digital-to-analog conversion circuit is used to provide a setting voltage to the subsequent constant current circuit, which only needs to output a constant voltage signal and does not need to generate a variable analog signal; The constant current circuit is used to generate pulsed signals with different amplitudes, and the amplitude voltage of the pulse = constant current circuit output current x load resistor; the size of the constant current circuit output current is set by the voltage signal output by the DAC digital-to-analog conversion circuit to achieve variable setting of different amplitude pulses.

2. The high speed variable pulse width amplitude signal synthesis circuit of claim 1, wherein: The differential switch circuit is used to drive the constant current output without affecting the rising and falling edges, so that the rising and falling edges can be controlled within 1 nanosecond; and the multiple output constant current pulse signals directly act on the load resistor to realize direct synthesis of high-speed driving signals with multiple pulses, different amplitudes, and different pulse widths.

3. The high speed variable pulse width amplitude signal synthesis circuit of claim 1, wherein: The differential switch circuit uses a differential high-speed transistor switch circuit.

4. The high speed variable pulse width amplitude signal synthesis circuit of claim 1, wherein: The FPGA / CPLD circuit uses a 400MHz FPGA or CPLD to meet the minimum requirement of generating a high-speed differential pulse signal with a pulse width of 2.5ns to realize output of multiple high-speed differential pulse signals with different pulse widths and phases for subsequent driving and signal synthesis.

5. The high speed variable pulse width amplitude signal synthesis circuit of claim 1, wherein: The PECL circuit is used to shape the high-speed differential pulse signal output by the previous FPGA / CPLD circuit to improve the load capacity and expand to multiple differential pulse signals.

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