Pipelined successive approximation analog-to-digital converter calibration method and system

Abstract

The application provides a pipeline successive approximation analog-digital converter calibration method and system, comprising the following steps: a misadjustment calibration step: calibrating the misadjustment voltage of a foreground comparator and a residual amplifier, measuring and storing the misadjustment voltage of the foreground comparator and the residual amplifier as a misadjustment calibration code, and compensating the misadjustment voltage of the foreground comparator and the residual amplifier; a mismatch calibration step: calibrating the mismatch of a foreground capacitor, measuring the capacitor mismatch in a previous CDAC, and calibrating the output code value of the pipeline successive approximation analog-digital converter in a digital error correction logic; a mismatch correction step: correcting the mismatch of an inter-stage gain combined by the foreground and the background, correcting the inter-stage gain mismatch once during startup, adjusting the gain of the residual amplifier, and detecting the inter-stage gain change by using a pseudo-random signal injection in the background and calibrating. The application can calibrate the non-ideal factors in the pipeline successive approximation analog-digital converter.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, and more specifically, to a pipelined successive approximation analog-to-digital converter calibration method and system. Background Technology

[0002] Traditional pipelined analog-to-digital converters (ADCs) operate in a pipelined manner through multiple cascaded stages, offering high accuracy and high sampling rates. However, the presence of multiple inter-stage residual amplifiers consumes significant power. In contrast, traditional successive approximation register (SAR) ADCs are simple in structure, highly digitized, and low-power. Pipelined SAR ADCs (PSAR ADCs) combine the advantages of both, offering high sampling rates, high accuracy, and low power consumption, making them a hot research topic in recent years.

[0003] A pipelined successive approximation analog-to-digital converter (ADC) mainly consists of a sample-and-hold network, a sub-successive approximation ADC, a residual amplifier, and digital error calibration logic. Due to the high accuracy of the sub-ADC, a two- to three-stage pipelined successive approximation ADC can generally achieve a resolution of 12 to 14 bits. However, due to various non-ideal factors in the pipelined successive approximation ADC, including comparator and residual amplifier misalignment, inter-stage gain mismatch, and capacitor mismatch, the performance of the ADC is severely degraded. Therefore, it is necessary to calibrate these non-ideal factors in the actual implementation process.

[0004] Patent document CN106849949B discloses a front-end calibration circuit and calibration method for a pipelined analog-to-digital converter. This calibration circuit includes an amplifier with local positive feedback, a subsequent analog-to-digital converter, a fixed analog input signal module, a constant module, a delay-aligned summation unit, an accumulator-average unit, registers, adders, subtractors, an n-bit sub-ADC, a sub-DAC, and a calibration state machine. However, the technical solution in this patent document differs from that in this application. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the purpose of this invention is to provide a pipeline successive approximation analog-to-digital converter calibration method and system.

[0006] A pipeline successive approximation analog-to-digital converter calibration method according to the present invention includes the following steps:

[0007] Offset calibration steps: The offset voltages of the front-end comparator and the residual amplifier are calibrated. The offset voltages of the front-end comparator and the residual amplifier are measured and stored as offset calibration codes using a successive approximation analog-to-digital converter. During normal operation, the calibration capacitor array is controlled to compensate for the offset voltages of the front-end comparator and the residual amplifier.

[0008] Mismatch calibration steps: Perform mismatch calibration on the front-end capacitors, use the subsequent pipeline to measure the capacitor mismatch in the front-end CDAC to obtain the actual capacitor weights, and calibrate the output code value of the pipeline successive approximation analog-to-digital converter in the digital error correction logic;

[0009] Mismatch correction steps: Perform mismatch correction on the interstage gain of the front-end and back-end combined system. After the ADC is started, perform a power-on correction on the interstage gain mismatch and adjust the gain of the residual amplifier to make the interstage gain equal to the preset value. In the back-end, use pseudo-random signal injection to detect and calibrate the interstage gain change.

[0010] Preferably, the offset voltage of the front-end comparator is calibrated, specifically including the following steps:

[0011] Step A1: During the measurement phase, short-circuit the positive and negative terminals of CDAC in the sampling phase and reset it to the common-mode level, while simultaneously resetting the calibration capacitor array; in the conversion phase, keep the lower plate of the main capacitor array unchanged, use the calibration capacitor array as the capacitor array for successive approximation of the analog-to-digital converter to measure the offset voltage of the front-end comparator and store the result in the register; measure the offset voltage of the front-end comparator and use the measurement result as the offset voltage calibration code of the front-end comparator;

[0012] Step A2: During normal operation, in the sampling phase, the calibration capacitor array is reset; in the switching phase, the calibration capacitor array flips the lower plate of the calibration capacitor array according to the offset voltage calibration code to calibrate the offset voltage of the front comparator.

[0013] Preferably, in step A1, the offset voltage of the front-end comparator is measured four times, and the average value of the four measurements is used as the offset voltage calibration code of the front-end comparator.

[0014] Preferably, the offset voltage of the residual amplifier is calibrated, specifically including the following steps:

[0015] Step B1: During the measurement phase, in the sampling phase, the positive and negative terminals of the CDAC are shorted and reset to the common-mode level, and the calibration capacitor array is reset at the same time; at the end of the conversion phase, the calibration capacitor array flips the lower plate of the calibration capacitor array according to the current residual amplifier calibration code, so that the lower plate of the main CDAC remains unchanged; when the offset calibration code of the residual amplifier is stable, the calibration is completed and the offset calibration code of the residual amplifier is stored in the register.

[0016] Step B2: During normal operation, in the sampling phase, the calibration capacitor array is reset; in the amplification phase, the calibration capacitor array flips the lower plate of the calibration capacitor array according to the offset calibration code of the residual amplifier, thereby calibrating the offset voltage of the residual amplifier.

[0017] Preferably, in step B1, during the amplification phase, the residual amplifier amplifies the residual voltage to the next stage pipeline. The front comparator of the next stage pipeline compares the residual voltage. If the residual voltage is greater than 0, the offset calibration code of the residual amplifier is incremented by 1; otherwise, the offset calibration code of the residual amplifier is decremented by 1.

[0018] Preferably, the front-end capacitor is mismatch calibrated, which specifically includes the following steps:

[0019] Step C1: Reset the CDAC of the first-stage successive approximation analog-to-digital converter in the sampling phase; in the conversion phase, flip the capacitor to be calibrated to the positive reference voltage, keep the capacitors above it unchanged, and flip the lower plate of the capacitors below it to ground level; in the amplification phase, the residual amplifier amplifies the residual voltage and it is measured by the next stage successive approximation analog-to-digital converter, and the measurement results are recorded.

[0020] Step C2: Calculate the actual weight of each capacitor based on the measurement results;

[0021] Step C3: During normal operation, the calculated actual weights are used to calibrate the digital output calibration code.

[0022] Preferably, in step C1, all high-to-low-order capacitors in the front-end pipeline CDAC are traversed.

[0023] Preferably, mismatch correction is performed on the interstage gain of the front-end and back-end combination, specifically including the following steps:

[0024] Step D1: After the ADC starts, a front-end calibration is performed to make the ADC input a common-mode voltage, and the dithering capacitor C in the front-end pipeline CDAC is used. d Inject a square wave signal and adjust the gain of the residual amplifier to stabilize the interstage gain at the preset value;

[0025] Step D2: After the ADC is working normally, it switches to background calibration. The dithering capacitor C in the front-end pipeline CDAC is used. d A pseudo-random signal is injected and superimposed on the residual voltage of the first-stage pipeline, and then amplified by the residual amplifier to the second-stage pipeline. The digital output code value of the second-stage pipeline is obtained by conversion. The digital output code value is multiplied by the pseudo-random signal, and its expected value is calculated after a conversion cycle. The actual interstage gain is then calculated, and the calibration is completed.

[0026] Preferably, in step D1, the residual amplifier gain is adjusted using the LMS algorithm.

[0027] The present invention also provides a pipeline successive approximation analog-to-digital converter calibration system, comprising the following modules:

[0028] Offset calibration module: calibrates the offset voltage of the front comparator and the residual amplifier. It uses a successive approximation analog-to-digital converter to measure and store the offset voltage of the front comparator and the residual amplifier as an offset calibration code. During normal operation, it controls the calibration capacitor array to compensate for the offset voltage of the front comparator and the residual amplifier.

[0029] Mismatch calibration module: performs mismatch calibration on the front-end capacitors, uses the subsequent pipeline to measure the capacitor mismatch in the front-end CDAC to obtain the actual capacitor weights, and calibrates the output code value of the pipeline successive approximation analog-to-digital converter in the digital error correction logic;

[0030] Mismatch correction module: Performs mismatch correction on the interstage gain of the front-end and back-end combined. After the ADC is started, it performs a power-on correction on the interstage gain mismatch and adjusts the gain of the residual amplifier to make the interstage gain equal to the preset value. In the back-end, pseudo-random signal injection is used to detect and calibrate the interstage gain change.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] 1. This invention can calibrate the offset voltage of comparators and residual amplifiers to prevent pipeline saturation in subsequent stages;

[0033] 2. This invention reduces the fixation error caused by capacitor mismatch by using a subsequent capacitor array to calibrate the preceding capacitor mismatch.

[0034] 3. This invention uses a front-end and back-end combined interstage gain error calibration method to ensure that the interstage gain does not deviate too much from the design value while reducing harmonic distortion caused by interstage gain mismatch. Attached Figure Description

[0035] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0036] Figure 1 This is a flowchart of the pipeline successive approximation analog-to-digital converter calibration method of the present invention;

[0037] Figure 2 This is a schematic diagram of the structure of a pipelined successive approximation analog-to-digital converter calibration system in one embodiment;

[0038] Figure 3 This is a circuit diagram of the first-stage capacitor array in one embodiment;

[0039] Figure 4Here are the timing diagram and phase diagram of one embodiment;

[0040] Figure 5 This is a flowchart of the calibration system workflow in one embodiment;

[0041] Figure 6 This is a spectrum of the analog-to-digital converter output without calibration in one embodiment;

[0042] Figure 7 This is an example of the output spectrum of an analog-to-digital converter with calibration in one embodiment. Detailed Implementation

[0043] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0044] Example 1:

[0045] like Figures 1-7 As shown, this embodiment provides a pipelined successive approximation analog-to-digital converter calibration method, including the following steps:

[0046] Offset calibration steps: The offset voltages of the front-end comparator and the residual amplifier are calibrated. The offset voltages of the front-end comparator and the residual amplifier are measured and stored as offset calibration codes using a successive approximation analog-to-digital converter. During normal operation, the calibration capacitor array is controlled to compensate for the offset voltages of the front-end comparator and the residual amplifier. The offset voltage of the front-end comparator is calibrated, specifically including the following steps: Step A1: Measurement phase, in the sampling phase, the positive and negative terminals of CDAC are shorted and reset to the common-mode level, and the calibration capacitor array is reset simultaneously; in the switching phase, the lower plate of the main capacitor array remains unchanged, and the calibration capacitor array is used as the capacitor array for successive approximation of the analog-to-digital converter to measure the offset voltage of the front-end comparator and store the result in the register; the offset voltage of the front-end comparator is measured, and the measurement result is used as the offset voltage calibration code of the front-end comparator. The measurement of the offset voltage of the front-end comparator is repeated four times, and the average value of the four measurement results is used as the offset voltage calibration code of the front-end comparator; Step A2: Normal operation phase, in the sampling phase, the calibration capacitor array is reset; in the switching phase, the lower plate of the calibration capacitor array is flipped according to the offset voltage calibration code to calibrate the offset voltage of the front-end comparator. The offset voltage of the residual amplifier is calibrated using the following steps: Step B1: During the measurement phase, in the sampling phase, the positive and negative terminals of the CDAC are shorted and reset to the common-mode level, and the calibration capacitor array is reset simultaneously. At the end of the conversion phase, the calibration capacitor array flips the lower plate of the calibration capacitor array according to the current residual amplifier calibration code, keeping the lower plate of the main CDAC unchanged. When the offset calibration code of the residual amplifier stabilizes, the calibration is completed, and the offset calibration code of the residual amplifier is stored in a register. In the amplification phase, the residual amplifier amplifies the residual voltage to the next stage pipeline. The front comparator of the next stage pipeline compares the residual voltage. If the residual voltage is greater than 0, the offset calibration code of the residual amplifier is incremented by 1; otherwise, the offset calibration code of the residual amplifier is decremented by 1. Step B2: During the normal operation phase, in the sampling phase, the calibration capacitor array is reset. In the amplification phase, the calibration capacitor array flips the lower plate of the calibration capacitor array according to the offset calibration code of the residual amplifier to calibrate the offset voltage of the residual amplifier.

[0047] Mismatch calibration steps: Mismatch calibration is performed on the front-end capacitors. The capacitor mismatch in the front-end CDAC is measured using the subsequent pipeline stage to obtain the actual capacitor weights. The output code value of the pipeline successive approximation analog-to-digital converter is then calibrated in the digital error correction logic. The mismatch calibration of the front-end capacitors specifically includes the following steps: Step C1: The CDAC of the first-stage successive approximation analog-to-digital converter is reset in the sampling phase. In the conversion phase, the capacitor to be calibrated is flipped to the positive reference voltage, the capacitors with higher bits remain unchanged, and the lower plate of the capacitors with lower bits flips to ground level. In the amplification phase, the residual amplifier amplifies the residual voltage and iterates through all high-to-low bits of the front-end pipeline CDAC, recording the measurement results. Step C2: The actual weights of each capacitor are calculated based on the measurement results. Step C3: During normal operation, the calculated actual weights are used to calibrate the digital output calibration code.

[0048] Mismatch Correction Steps: Mismatch correction is performed on the interstage gain of the combined front-end and back-end stages. After the ADC starts, a power-on calibration is performed to correct the interstage gain mismatch, and the gain of the residual amplifier is adjusted to make the interstage gain equal to the preset value. In the back-end stage, pseudo-random signal injection is used to detect and calibrate the interstage gain change. The specific steps for mismatch correction of the interstage gain of the combined front-end and back-end stages include: Step D1: After the ADC starts, a front-end calibration is performed to make the ADC input a common-mode voltage. The jitter capacitor C in the front-end pipeline CDAC is... d Inject a square wave signal, adjust the residual amplifier gain to stabilize the interstage gain at a preset value, and adjust the residual amplifier gain using the LMS algorithm; Step D2: After the ADC is working normally, switch to background calibration, and adjust the dithering capacitor C of the front-end pipeline CDAC. d A pseudo-random signal is injected and superimposed on the residual voltage of the first-stage pipeline, and then amplified by the residual amplifier to the second-stage pipeline. The digital output code value of the second-stage pipeline is obtained by conversion. The digital output code value is multiplied by the pseudo-random signal, and its expected value is calculated after a conversion cycle. The actual interstage gain is then calculated, and the calibration is completed.

[0049] Example 2:

[0050] This embodiment provides a pipelined successive approximation analog-to-digital converter calibration system, including the following modules:

[0051] Offset calibration module: calibrates the offset voltage of the front comparator and the residual amplifier. It uses a successive approximation analog-to-digital converter to measure and store the offset voltage of the front comparator and the residual amplifier as an offset calibration code. During normal operation, it controls the calibration capacitor array to compensate for the offset voltage of the front comparator and the residual amplifier.

[0052] Mismatch calibration module: performs mismatch calibration on the front-end capacitors, uses the subsequent pipeline to measure the capacitor mismatch in the front-end CDAC to obtain the actual capacitor weights, and calibrates the output code value of the pipeline successive approximation analog-to-digital converter in the digital error correction logic;

[0053] Mismatch correction module: Performs mismatch correction on the interstage gain of the front-end and back-end combined. After the ADC is started, it performs a power-on correction on the interstage gain mismatch and adjusts the gain of the residual amplifier to make the interstage gain equal to the preset value. In the back-end, pseudo-random signal injection is used to detect and calibrate the interstage gain change.

[0054] Example 3:

[0055] Those skilled in the art can understand this embodiment as a more specific description of Embodiment 1 and Embodiment 2.

[0056] This embodiment proposes a calibration method and system for a pipelined successive approximation analog-to-digital converter. It performs front-end calibration for offset voltage and capacitance mismatch in comparators and residual amplifiers, and combines front-end and back-end calibration for inter-stage gain mismatch. The calibration method and system proposed in this embodiment have advantages such as simple structure, high energy efficiency, and strong portability.

[0057] The following technical solution is adopted in this embodiment:

[0058] A pipelined successive approximation analog-to-digital converter (ADC) calibration method and system, wherein the pipelined ADC calibration method includes:

[0059] A method for offset calibration of a front-end comparator and a residual amplifier is provided, which uses a successive approximation analog-to-digital converter to measure and store the offset voltage of the comparator and the residual amplifier as an offset calibration code, and controls a calibration capacitor array to compensate for the offset voltage of the comparator and the residual amplifier during normal operation.

[0060] A front-end capacitor mismatch calibration method utilizes the downstream pipeline to measure the capacitor mismatch in the front-end CDAC (Capacitor Digital-to-Analog Converter), obtains the actual capacitor weight, and calibrates the output code value of the pipeline successive approximation analog-to-digital converter in the digital error correction logic;

[0061] A front-end and back-end combined interstage gain mismatch correction method is proposed. After the ADC is started, the interstage gain mismatch is corrected once upon startup, and the gain of the residual amplifier is adjusted so that the interstage gain is equal to the design value. In the back-end, pseudo-random signal injection is used to detect and calibrate the interstage gain change.

[0062] Furthermore, the comparator offset voltage calibration includes the following steps:

[0063] S1, Measurement Phase: In the sampling phase, the positive and negative terminals of CDAC are shorted and reset to the common-mode level, and the calibration capacitor array is reset at the same time; In the conversion phase, the lower plate of the main capacitor array remains unchanged, and the calibration capacitor array is used as the capacitor array to successively approximate the analog-to-digital converter. The offset voltage of the comparator is measured and the result is stored in the register; The comparator offset voltage measurement is completed, repeated four times, and the average of the four results is used as the comparator offset voltage calibration code to eliminate the influence of noise;

[0064] S2, during normal operation, in the sampling phase, the calibration array is reset; in the conversion phase, the calibration array flips the lower plate of the calibration capacitor array according to the calibration code to calibrate the comparator offset voltage.

[0065] Furthermore, the offset voltage calibration of the residual amplifier includes the following steps:

[0066] S1, Measurement Phase: In the sampling phase, the positive and negative terminals of the CDAC are shorted and reset to the common-mode level, and the calibration capacitor array is reset simultaneously. At the end of the conversion phase, the calibration capacitor array flips the lower plate of the calibration capacitor array according to the current residual amplifier calibration code, while the lower plate of the main CDAC remains unchanged. In the amplification phase, the residual amplifier amplifies the residual voltage to the next stage pipeline. The comparator in the next stage pipeline compares the residual voltage. If the residual voltage is greater than 0, the residual amplifier offset calibration code is incremented by 1; otherwise, the residual amplifier offset calibration code is decremented by 1. When the residual amplifier offset calibration code is stable, the calibration is completed, and the residual amplifier offset calibration code is stored in the register.

[0067] S2, during normal operation, in the sampling phase, the calibration capacitor array is reset; in the amplification phase, the calibration capacitor array flips the lower plate of the calibration capacitor array according to the residual amplifier calibration code to calibrate the offset voltage of the residual amplifier.

[0068] The capacitor mismatch calibration includes the following steps:

[0069] S1, the first-stage successive approximation analog-to-digital converter (CDAC) is reset in the sampling phase. In the conversion phase, the capacitor to be calibrated flips to the positive reference voltage, the capacitors higher than it remain unchanged, and the lower plate of the capacitors lower than it flips to ground. In the amplification phase, the residual amplifier amplifies the residual voltage and it is measured by the next stage successive approximation analog-to-digital converter, and the result is recorded. This process iterates through all the high-to-low capacitors in the previous stage pipeline CDAC.

[0070] S2, calculate the actual weight of each capacitor based on the measurement results;

[0071] S3, during normal operation, uses the calculated actual weights to calibrate the digital output calibration code.

[0072] The interstage gain mismatch calibration includes the following steps:

[0073] S1, after the ADC starts, a front-end calibration is performed. The ADC input is a common-mode voltage, and the dithering capacitor C in the front-end pipeline CDAC is used. d A square wave signal is injected, and the LMS algorithm is used to adjust the gain of the residual amplifier so that the interstage gain is stabilized at the design value.

[0074] S2, after the ADC is working normally, it switches to background calibration, and the jitter capacitor C in the front-end pipeline CDAC is used. d A pseudo-random signal is injected and superimposed on the residual voltage of the first-stage pipeline, and then amplified by the residual amplifier to the second-stage pipeline. The digital output code value of the second-stage pipeline is obtained by conversion. The digital output code value is multiplied by the pseudo-random signal, and after a large number of conversion cycles, its expected value is calculated to obtain the actual interstage gain, thus completing the calibration.

[0075] Example 3:

[0076] Those skilled in the art can understand this embodiment as a more specific description of Embodiment 1.

[0077] The pipelined successive approximation analog-to-digital converter (ADC) calibration method and system proposed in this embodiment can achieve offset calibration of comparators and residual amplifiers, capacitor mismatch calibration, and interstage gain mismatch calibration. It is applicable to pipelined successive approximation ADCs with two or more pipelines. This embodiment specifically illustrates a two-stage pipelined successive approximation ADC, wherein the first stage of the two-stage pipelined successive approximation ADC has a resolution of 6 bits, the second stage has a resolution of 9 bits, and there is a 1-bit interstage redundancy.

[0078] Figure 2 This is a schematic diagram of the pipelined successive approximation analog-to-digital converter and its calibration system in this embodiment. For the sake of simplicity, Figure 2 The differential structures shown in the diagram only depict the positive terminals, with the negative terminals grounded for simplification. This pipelined successive approximation analog-to-digital converter includes a sample-and-hold network, a first-stage CDAC (6 bits), a first-stage comparator, a first-stage SAR logic, a residual amplifier, a second-stage CDAC (9 bits), a second-stage comparator, a second-stage SAR logic, an inter-stage gain calibration module, a capacitor mismatch calibration module, and digital error correction logic.

[0079] The sample-and-hold network is connected to the first-stage CDAC to sample the analog input voltage V. inThe first-stage CDAC, first-stage comparator, and first-stage SAR logic are connected in pairs to form a sub-successive approximation analog-to-digital converter (ADC) in the first-stage pipeline, quantizing the input voltage and generating a residual voltage. The first-stage CDAC, residual amplifier, and second-stage CDAC are connected sequentially. The residual amplifier amplifies the residual voltage from the first-stage pipeline to the second stage, where it is quantized by the sub-successive approximation ADC in the second-stage pipeline, which consists of the second-stage CDAC, second-stage comparator, and second-stage SAR logic. The first-stage SAR logic stores a pseudo-random signal and the offset calibration code for the first-stage comparator and residual amplifier. The pseudo-random signal controls the random injection capacitor C in the first-stage CDAC. d The first and second stage SAR logics are used to implement inter-stage gain mismatch calibration. The mismatch calibration code controls the calibration capacitor array to calibrate the mismatch of the first-stage comparator and residual amplifier. The second-stage SAR logic stores the mismatch calibration code of the second-stage comparator, which is used to control the calibration capacitor array of the second-stage CDAC to calibrate the mismatch of the second-stage comparator. The first and second stage SAR logics are connected to the inter-stage gain calibration module and the capacitor mismatch calibration module. During the foreground calibration, the inter-stage gain calibration module uses the LMS algorithm to adjust the residual amplifier gain so that the inter-stage gain equals the design value. During the background calibration, it monitors the change in inter-stage gain. The capacitor mismatch calibration module calculates C6~C1 and C2 in the first-stage CDAC (6 bits). d The actual weights are calculated and output to the digital error correction module. The digital error correction module receives the digital output code values ​​from the two-stage pipeline and, based on the actual capacitor weights and actual inter-stage gain, integrates and corrects the output digital code values, outputting the value corresponding to the input analog voltage V. in The digital code value.

[0080] Figure 3 This is the circuit diagram of the first-stage capacitor array in this embodiment. For the sake of simplicity, Figure 3 The diagram only shows the positive terminal circuit of the first-stage CDAC capacitor array, which is connected to the positive terminal of the residual amplifier. In reality, the negative terminal of the residual amplifier is connected to an identical capacitor array. The capacitor array uses a split-monotonic switching method, therefore... Figure 2 Each corresponding array consists of p-terminal capacitors and m-terminal capacitors. The C6 capacitor is composed of C... 6p C 6m The structure can be deduced from C5 to C1 in sequence, with randomly injected capacitor C. d By C dp C dm Composition. The offset correction capacitor consists of C cp and C cmThe calibration capacitor array consists of a P-terminal calibration capacitor array and an M-terminal calibration capacitor array. VREF is the reference voltage, pnp and pnm are pseudo-random injection signals, and VCM is the common-mode level. When the CDAC needs to be reset in calibration mode, the upper plate of the CDAC is reset to the common-mode level VCM. 6p C 5p C 4p C 3p C 2p C 1p C dp The lower electrode is reset to VREF, C 6m C 5m C 4m C 3m C 2m C 1m C dm The lower electrode is reset to low level GND. C cp The lower plate of the P-terminal calibration capacitor array and the upper plate of the P-terminal calibration capacitor array are reset to VREF, and the lower plate of the P-terminal calibration capacitor array is reset to VREF. cm The lower plate of the M-terminal calibration capacitor array and the upper plate of the M-terminal calibration capacitor array are reset to GND, and the lower plate of the M-terminal capacitor array is reset to GND.

[0081] Furthermore, the circuit diagram of the second-stage CDAC capacitor array is similar to that of the first-stage CDAC, except that the main capacitor array of the second-stage CDAC has 9 capacitors, C9 to C1, and there is no random signal injection capacitor C. d .

[0082] Figure 4 The timing diagram and phase diagram are for the operation of this embodiment. and and Figure 1 The signals in the text correspond to each other. The sample-and-hold network is controlled; when it is pulled high, the network performs sampling, and the first-stage pipeline enters the sampling phase. When pulled down, The first-stage comparator is controlled to start comparison, and the first-stage pipeline enters the conversion phase. After the conversion is completed, a residual voltage is generated on the first-stage CDAC. The residual amplifier is controlled to amplify the voltage. When it is pulled high, the residual amplifier amplifies the residual voltage to the second stage, and the first-stage pipeline enters the amplification phase. At the same time, the second-stage pipeline enters the sampling phase. When the signal is pulled low, the residual amplifier ends amplification, and the second-stage pipeline enters the transition phase. The second-stage comparator is controlled to begin comparison and complete the conversion.

[0083] This embodiment describes the comparator offset calibration method in detail: Taking the offset calibration of the first-stage comparator as an example, the offset calibration is divided into two steps. S1, the measurement stage, during which the pipeline successive approximation analog-to-digital converter cannot function properly. When the first-stage pipeline enters the sampling phase, the first-stage CDAC is reset. During the conversion phase, the main capacitor C in the first-stage CDAC... 6p ~C 1p C 6m ~C 1m Still in reset state, C dp C dm It is also in the reset state. C cp and C cm The lower plate is disconnected from VREF and GND respectively. The first-stage SAR logic, the first-stage comparator, and the calibration capacitor arrays at the P and M terminals constitute the calibration SAR ADC. The offset voltage of the first-stage comparator is measured. To avoid noise affecting the offset voltage measurement, the comparator offset voltage measurement is repeated four times, and the average of the four results is taken as the offset calibration code of the first-stage comparator. S2, calibration phase: When the pipeline successively approaches the normal operation of the analog-to-digital converter, in the sampling phase, the input is sampled onto the upper plate of the first-stage CDAC, and the calibration capacitor arrays at the P and M terminals are reset. In the conversion phase, the comparator starts working, and the lower plate of the calibration capacitor arrays at the P and M terminals is flipped according to the first-stage comparator offset calibration code, creating a voltage difference of the same magnitude but opposite polarity to the first-stage comparator offset voltage on the upper plate of the CDAC at the positive and negative terminals of the comparator, thereby achieving the calibration of the first-stage comparator offset voltage. The calibration method for the second-stage comparator offset voltage is the same as that for the first stage and will not be described again.

[0084] The offset voltage calibration of the residual amplifier is described in detail in this embodiment: The calibration of the offset voltage of the residual amplifier is divided into two steps: S1. Measurement phase. When the first-stage pipeline is in the sampling phase, the first-stage CDAC is reset. In the conversion phase, the first-stage comparator does not work, and the first-stage CDAC remains in the reset state. At the end of the conversion phase, the P-terminal and M-terminal calibration capacitor arrays of the first-stage CDAC flip the lower-plate level according to the current offset calibration code of the residual amplifier (initially 0), creating a voltage difference between the positive and negative terminals of the residual amplifier. When the first-stage pipeline enters the amplification phase (simultaneously the second-stage pipeline enters the sampling phase), the residual amplifier amplifies the residual voltage to the second-stage pipeline. At this time, due to the existence of the offset voltage of the residual amplifier, the amplified voltage is the sum of the offset voltage of the residual amplifier and the created voltage difference multiplied by the amplification factor. When the second stage enters the conversion phase, the calibration capacitor array of the second-stage CDAC flips the lower-plate voltage according to the offset calibration code of the second-stage comparator to cancel the influence of the offset voltage of the second-stage comparator, and the comparator judges the polarity of the amplified residual voltage. When the amplified residual voltage is greater than 0, the offset voltage calibration code of the residual amplifier is incremented by 1; otherwise, the offset voltage calibration code of the residual amplifier is decremented by 1, obtaining a new offset voltage calibration code of the residual amplifier. Repeat the above operations using the new offset voltage calibration code of the residual amplifier. When the offset calibration code of the residual amplifier tends to be stable (alternately incrementing by 1 and decrementing by 1), it means that the created voltage difference is opposite in polarity and equal in magnitude to the residual amplifier, and the measurement of the offset voltage of the residual amplifier is completed. Store the offset calibration code at this time in the register. S2. Calibration phase. When the pipelined successive approximation converter operates normally, when the first-stage pipeline enters the conversion phase, the P-terminal and M-terminal calibration capacitors flip the lower-plates according to the offset calibration code of the comparator. When entering the amplification phase, the P-terminal and M-terminal calibration capacitors flip the lower-plates according to the offset calibration code of the residual amplifier, completing the offset calibration of the residual amplifier.

[0085] The capacitance mismatch calibration method is described in detail in this embodiment: The principle of capacitance mismatch calibration is that, first, assume that the second-stage pipeline is an ideal 9-bit successive approximation analog-to-digital converter. Use the second-stage successive approximation analog-to-digital converter to measure the capacitance mismatch of the first-stage pipeline and calculate the actual capacitance weights according to the measurement results to achieve calibration. The capacitance mismatch calibration method can be divided into the following three steps: S1. Measurement phase. Take the measurement of the capacitance of the i-th bit (i = 1, 2,..., 6) as an example. When the first stage is in the sampling phase, the upper plates of the CDAC are reset to the common-mode level VCM. After entering the conversion phase, the comparator does not work. The lower plate of the i-th bit capacitance on the positive terminal CDAC of the first stage im flips from GND to VREF, and C ip remains unchanged. The capacitances higher than the i-th bit remain unchanged. The C xp (x < i) of the capacitances lower than the i-th bit flip from VREF to GND, and Cxm The lower plate remains unchanged. Due to capacitor mismatch, a voltage difference exists at the upper plate of the CDAC at the positive and negative terminals, which serves as the residual voltage. In the amplification phase, this residual voltage is amplified by the residual amplifier to the second-stage pipeline and quantized by the second-stage successive approximation analog-to-digital converter. The quantization result is recorded. This process is repeated 32 times, and the average is taken. The result is denoted as D. cal (i). For C1 to C6 of the first level, C d By performing the above operations, we can obtain D. cal (i), i = 1, 2, ..., 6, d. S2, Actual weight calculation, assuming the weight of C1 is the ideal W1 = 1, then the weight of C2 is calculated as W2 = W1 + (D cal (2) / FS*VREF-D cal (1) / FS*VREF) / (D cal (1) / FS*VREF-VCM), where FS is the digital full swing, and so on. The weights of other capacitors can be calculated using the following formula: W i =W1+W2+…+W i-1 +(D cal (i) / FS*VREF-D cal (1) / FS*VREF) / (D cal (1) / FS*VREF-VCM), i=2,…,6, and C d The weight is W d =(D cal (d) / FS*VREF-VCM) / (D cal (d) / FS*VREF-VCM). S3, Calibration Phase: When the pipeline successively approaches the normal operation of the analog-to-digital converter, the output code value is multiplied by the actual weight in the digital error correction logic to obtain the corrected output code value, completing the capacitor mismatch calibration. It is worth noting that this capacitor mismatch calibration method is not limited to calibrating the capacitor mismatch in the first-stage pipeline, but can also calibrate the capacitor weight mismatch in the second stage. In this case, the low-order capacitors in the second stage can be considered to constitute an ideal SAR ADC with the second-stage comparator and the second-stage SAR logic, and the mismatch of the high-order capacitors is measured and the actual weight is calculated to achieve calibration. Furthermore, the offset calibration of the comparator and residual amplifier needs to be completed before the capacitor mismatch calibration to eliminate the influence of the offset voltage on the capacitor mismatch calibration algorithm.

[0086] This embodiment describes in detail the calibration method for interstage gain mismatch: Interstage gain mismatch calibration consists of the following steps: S1, after the ADC starts, a front-end calibration is performed. During this time, the pipeline successive approximation analog-to-digital converter is not working. In the sampling phase, the CDAC of the first-stage pipeline is reset. In the conversion phase, the first-stage comparator is not working. At the end of the conversion phase, a square wave is injected into the random signal through the random signal injection capacitor Cd instead of the random signal. In the residual amplification stage, the residual amplifier amplifies the residual voltage to the second-stage pipeline, and the second-stage pipeline completes the quantization. The LMS algorithm is used to achieve front-end calibration. Since the square wave signal alternates between positive and negative, the difference between the two quantization results can eliminate the influence caused by the offset voltage. Therefore, there is no clear order requirement between interstage gain mismatch calibration and offset calibration. The quantization value of the nth cycle of the second-stage pipeline is set to D. gcal (n), the quantization value of the (n+1)th cycle is D gcal (n+1), D gcal (n) and D gcal (n+1) correspond to two different levels of the square wave. Assuming the interstage gain is a set value and the interstage redundancy is 1 bit, then theoretically, |D gcal (n+1)-D gcal (n)| / FS*VREF=0.5*W d *VREF, where W d C d The actual weight. However, due to inter-level mismatch, |D gcal (n+1)-D gcal (n)| / FS*VREF≠0.5*W d *VREF. Based on the above equation and the principle of the LMS algorithm, the error function of the LMS algorithm, ERROR(n+1), can be set as |D gcal (n+1)-D gcal (n)| / FS*VREF-0.5*W d *VREF, while the objective function of the LMS algorithm is TARGET(n+1)=TARGET(n)+μ*ERROR(n+1), and the gain of the residual amplifier is adjusted using the objective function to form negative feedback in the LMS system, realizing the front-end calibration of inter-stage gain error. S2, the background calibration stage, after the front-end calibration is completed, the inter-stage gain is at the design value, but due to changes in the working environment during operation, the inter-stage gain will deviate from the design value again. Therefore, background calibration of inter-stage gain mismatch is required to realize real-time detection of inter-stage gain. During the normal operation of the pipeline successive approximation analog-to-digital converter, at the end of the conversion phase, the random signal is injected into the random signal capacitor C. d The injected residual voltage is amplified in the amplification phase and then quantized in the second-stage pipeline. The quantization result of the second stage is D.pncal =(V res +P d *W d )*G act +Q n , where V res For the first stage residual voltage, P d For randomly injected signals, W d C d The actual weight, Q n For the second-order quantization error, G act For the interstage gain error, we can obtain E(D) pncal *P d )=E(V res *P d *G act )+E(W d *P d 2 *G act )+E(Q n *P d Since the randomly injected signal is uncorrelated with other signals, and E(P) d ) = 0, E(P) d 2 ) = 1, therefore we have E(D) pncal *P d ) = W d *G act Therefore, G can be calculated. act =E(D) pncal *P d ) / W d Based on the above principles, and through extensive statistical calculations, the actual interstage gain during the background operation can be obtained, thus enabling background calibration.

[0087] Figure 5 This describes the workflow of the pipelined successive approximation analog-to-digital converter calibration system proposed in this embodiment. According to the calibration process, the following steps are performed sequentially: comparator offset calibration, residual amplifier offset calibration, capacitor mismatch calibration, and interstage gain mismatch calibration. The comparator offset calibration, residual amplifier offset calibration, and capacitor mismatch calibration are all front-end calibrations. The interstage gain mismatch calibration is divided into two parts: a front-end calibration and a back-end calibration. The front-end calibration of interstage gain mismatch is performed first, followed by the back-end calibration.

[0088] Figure 6The output spectrum of an uncalibrated pipelined successive approximation analog-to-digital converter with 1% standard deviation capacitor mismatch and 5% interstage gain error is shown. Its signal-to-noise-and-distortion-ratio (SNDR) is 58.7967 dB, spurious-free dynamic range (SFDR) is 66.2168 dB, and effective number of bits (ENOB) is 9.4745 bits.

[0089] Figure 7 The output spectrum of the calibrated pipeline successive approximation analog-to-digital converter with 1% standard deviation capacitor mismatch and 5% interstage gain error is SNDR = 85.2753dB, SFDR = 100.4294dB, and ENOB = 13.873bit. After calibration, SNDR increased by 26.4784dB, SFDR increased by 34.2126dB, and ENOB increased by 4.3985bit.

[0090] This invention can calibrate non-ideal factors in pipeline successive approximation analog-to-digital converters.

[0091] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0092] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A pipelined successive approximation analog-to-digital converter calibration method, characterized by, The method comprises the following steps: The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; 2. The pipeline successive approximation analog-to-digital converter calibration method of claim 1, wherein, The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; 3. The pipeline successive approximation analog-to-digital converter calibration method of claim 1, wherein, The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; 4. The pipeline successive approximation analog-to-digital converter calibration method of claim 3, wherein, The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; 5. The pipeline successive approximation analog-to-digital converter calibration method of claim 1, wherein, The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated in the digital error correction logic; The step of calibrating the mismatch of the front-stage capacitors: the capacitive mismatch of the front-stage CDAC is measured by the subsequent pipeline, and the actual capacitive weight is obtained, and the output code value of the pipeline successive approximation analog-digital converter is calibrated Step C1: the CDAC of the first stage successive approximation analog-to-digital converter is reset in the sampling phase, the capacitor to be calibrated is flipped to the positive reference voltage in the conversion phase, the capacitor higher than it is kept unchanged, and the capacitor lower than it is flipped to the ground level in the lower plate; in the amplification phase, the residual error amplifier amplifies the residual error voltage and measures it by the next stage successive approximation analog-to-digital converter, and the measurement result is recorded; Step C2: the actual weight of each bit capacitor is calculated according to the measurement result; Step C3: in normal operation, the actual weight calculated is used to calibrate the digital output calibration code.

6. The pipeline successive approximation analog-to-digital converter calibration method of claim 5, wherein, In the step C1, all the high-to-low capacitors of the previous stage pipeline CDAC are traversed.

7. The pipeline successive approximation analog-to-digital converter calibration method of claim 1, wherein, The inter-stage gain of the combination of the front and back stages is mismatch corrected, and the specific steps include the following steps: Step D1: One foreground calibration is performed after the ADC is started, so that the ADC input is a common-mode voltage, and the jitter capacitor C of the front-stage pipeline CDAC d The injected square wave signal is adjusted to make the inter-stage gain stable at a preset value. Step D2: After the ADC is working normally, it is switched to background calibration, and the jitter capacitor C of the front-stage pipeline CDAC d The pseudo-random signal is superimposed on the residual voltage of the first-stage pipeline and amplified by the residual amplifier to the second-stage pipeline. The digital output code value of the second-stage pipeline is obtained by conversion, the digital output code value is multiplied by the pseudo-random signal, the expectation is calculated after the conversion period, the actual inter-stage gain is calculated, and the calibration is completed.

8. The pipeline successive approximation analog-to-digital converter calibration method of claim 7, wherein, In the step D1, the LMS algorithm is used to adjust the gain of the residual error amplifier.

9. A system for implementing the calibration method of the pipelined successive approximation analog-to-digital converter of claim 1, characterized by, The following modules are included: The mismatch correction module: the mismatch of the capacitors in the previous stage CDAC is measured by the next stage pipeline, the actual capacitor weight is obtained, and the output code value of the pipeline successive approximation analog-to-digital converter is calibrated in the digital error correction logic. The mismatch correction module: the inter-stage gain of the combination of the front and back stages is mismatch corrected, after the ADC is started, the inter-stage gain mismatch is corrected once at startup, the gain of the residual error amplifier is adjusted, the inter-stage gain is equal to the preset value, and the pseudo-random signal injection is used to detect the inter-stage gain change and correct it in the back stage. ​

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