Quantizers, Σ-Δ modulators, and noise shaping methods

Abstract

This disclosure proposes a quantizer, a Σ-Δ modulator, and a noise shaping method for a Σ-Δ modulator. The quantizer includes: an integrator for generating a quantized signal for the Kth period based on an internal signal, a quantized signal for the (K-1)th period, a filtered quantized signal for the (K-1)th period, and a filtered quantized signal for the (K-2)th period, where K is a positive integer greater than 1; an integrating capacitor for storing the quantized signal for the Kth period and using it to weight the internal signal in the (K+1)th period; a passive low-pass filter for acquiring the quantized signal for the Kth period in the Kth discharge period and generating a filtered quantized signal accordingly, and feeding back the filtered quantized signal to the integrator in the (K+1)th and (K+2)th period; and a comparator for quantizing the quantized signal for the Kth period in the Kth discharge period to output a digital code.

Description

Technical Field

[0001] This disclosure relates to the field of electrical engineering, and specifically to a quantizer for a Σ-Δ modulator, a Σ-Δ modulator, and a noise shaping method. Background Technology

[0002] Traditional Σ-Δ modulators typically employ cascaded analog integrators to achieve high-order suppression of quantization noise, thereby reducing the power of quantization noise and improving the signal-to-noise ratio. However, as the number of analog integrators increases, the loop stability gradually deteriorates, and the system power consumption further increases.

[0003] In related technologies, in order to reduce the power consumption of the Σ-Δ modulator and ensure the stability of the loop, a quantizer with noise shaping function is usually introduced into the Σ-Δ modulator. However, the above-mentioned Σ-Δ modulator is difficult to achieve high-order noise shaping with low power consumption. Summary of the Invention

[0004] This disclosure provides a quantizer for a Σ-Δ modulator, a Σ-Δ modulator, and a noise shaping method.

[0005] According to one aspect of this disclosure, a quantizer for a Σ-Δ modulator is provided, comprising:

[0006] An integrator is used to generate the quantization error signal for the Kth period based on the internal signal, the quantization error signal for the (K-1)th period, the filtered quantization error signal for the (K-1)th period, and the filtered quantization error signal for the (K-2)th period; where K is a positive integer greater than 1.

[0007] The integrating capacitor is used to store the quantization error signal in the Kth cycle and to weight the internal signal in the (K+1)th sampling cycle.

[0008] A passive low-pass filter is used to acquire the quantization error signal of the Kth discharge cycle, generate a filtered quantization error signal accordingly, and feed the filtered quantization error signal back to the integrator in the (K+1)th and (K+2)th sampling cycles; and

[0009] The comparator is used to quantize the quantization error signal of the Kth cycle in the Kth discharge cycle to output a digital code.

[0010] Preferably, the passive low-pass filter includes: a first passive low-pass filter and a second passive low-pass filter; wherein, the first passive low-pass filter is coupled to the positive input port and the positive output port of the integrator; and the second passive low-pass filter is coupled to the negative input port and the negative output port of the integrator.

[0011] The first passive low-pass filter and the second passive low-pass filter include:

[0012] The first capacitor is used to acquire the quantization error signal of the Kth period during the Kth discharge cycle, and to generate a filtered quantization error signal accordingly, and to feed back the filtered quantization error signal to the integrator during the (K+1)th sampling cycle; and

[0013] The second and third capacitors are used to acquire quantization error signals for odd and even periods, respectively, and generate filtered quantization error signals accordingly. The filtered quantization error signals are then fed back to the integrator in the (K+2)th sampling period.

[0014] According to another aspect of this disclosure, a Σ-Δ modulator is provided, comprising:

[0015] Quantizer, wherein the quantizer is as described above;

[0016] The front-end section includes a front-end input port and a front-end output port, which are used to receive input signals and output internal signals, respectively. The front-end section is also used to generate internal signals based on the input signals.

[0017] Preferably, the front-end section includes a first analog integrator, a second analog integrator, and a second digital-to-analog converter;

[0018] The second digital-to-analog converter is coupled between the output port of the quantizer and the second feedback port of the first analog integrator and the third feedback port of the second analog integrator. It is used to convert the digital code output by the quantizer and provide the second feedback signal accordingly.

[0019] The first analog integrator is used to receive the input signal and the second feedback signal, and to generate the first integrated signal accordingly;

[0020] The second analog integrator is used to receive the input signal, the second feedback signal, and the first integration signal, and to generate an internal signal accordingly.

[0021] Preferably, the front-end portion further includes a first digital-to-analog converter for converting the digital code output by the quantizer and providing a first feedback signal accordingly;

[0022] The quantizer also includes a first feedback port, coupled to the positive input port and negative input port of the integrator and the output port of the first digital-to-analog converter, for receiving the first feedback signal;

[0023] The integrator also integrates the internal signal based on the first feedback signal.

[0024] Preferably, the Σ-Δ modulator further includes a digital integrator coupled to the output port of the quantizer for integrating the digital code output by the quantizer to provide the integrated digital code.

[0025] Preferably, the front-end section includes a first analog integrator, a second analog integrator, and a second digital-to-analog converter;

[0026] The second digital-to-analog converter is coupled between the output port of the digital integrator and the second feedback port of the first analog integrator and the third feedback port of the second analog integrator. It is used to convert the digital code output by the digital integrator and provide the second feedback signal accordingly.

[0027] The first analog integrator is used to receive the input signal and the second feedback signal, and to generate the first integrated signal accordingly;

[0028] The second analog integrator also includes a fourth feedback port, coupled to the output port of the first digital-to-analog converter, for receiving the first feedback signal;

[0029] The second analog integrator also generates internal signals based on the input signal, the first integration signal, the second feedback signal, and the first feedback signal.

[0030] Preferably, the first analog integrator includes four capacitors, wherein:

[0031] The fourth and fifth capacitors are used to acquire the input signal and the second feedback signal, and to store the difference between the input signal and the second feedback signal.

[0032] The sixth and seventh capacitors are used to receive the difference between the input signal and the second feedback signal, and to generate the first integral signal accordingly.

[0033] Preferably, the second analog integrator includes six capacitors, wherein:

[0034] The eighth and ninth capacitors are used to acquire and store the first integrated signal.

[0035] The tenth and eleventh capacitors are used to acquire the input signal and the second feedback signal, and to store the difference between the input signal and the second feedback signal.

[0036] The twelfth and thirteenth capacitors are used to receive the difference between the first integral signal, the input signal, and the second feedback signal, and to generate internal signals accordingly.

[0037] Preferably, the second analog integrator includes six capacitors, wherein:

[0038] The eighth and ninth capacitors are used to acquire the first integral signal and the first feedback signal, and to save the difference between the first integral signal and the first feedback signal.

[0039] The tenth and eleventh capacitors are used to acquire the input signal and the second feedback signal, and to store the difference between the input signal and the second feedback signal.

[0040] The twelfth and thirteenth capacitors are used to receive the difference between the first integral signal and the first feedback signal, as well as the difference between the input signal and the second feedback signal, and to generate internal signals accordingly.

[0041] According to another aspect of this disclosure, a noise shaping method is provided, comprising:

[0042] During the Kth sampling period, the integrator acquires the internal signal, the quantization error signal of the (K-1)th period stored on the integrating capacitor, the filtered quantization error signal of the (K-1)th period fed back by the passive low-pass filter, and the filtered quantization error signal of the (K-2)th period, and generates the quantization error signal of the Kth period accordingly. The quantization error signal of the Kth period is stored on the integrating capacitor and used to weight the internal signal in the (K+1)th sampling period. Here, K is a positive integer greater than 1.

[0043] During the Kth discharge cycle, the quantization error signal of the Kth cycle is acquired through a passive low-pass filter, and a filtered quantization error signal is generated accordingly. This filtered quantization error signal is then fed back to the integrator during the (K+1)th and (K+2)th sampling cycles.

[0044] The quantization error signal of the Kth cycle is quantized by a comparator to output a digital code.

[0045] Preferably, the quantization error signal of the Kth period is acquired through a passive low-pass filter, and a filtered quantization error signal is generated accordingly. This filtered quantization error signal is then fed back to the integrator in the (K+1)th and (K+2)th sampling periods, including:

[0046] The quantization error signal of the Kth period is acquired using the first capacitor, and a filtered quantization error signal is generated accordingly. This filtered quantization error signal is then fed back to the integrator in the (K+1)th sampling period.

[0047] The second and third capacitors are used to acquire quantization error signals for odd and even periods, respectively, and a filtered quantization error signal is generated accordingly. The filtered quantization error signal is then fed back to the integrator in the (K+2)th sampling period. Attached Figure Description

[0048] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0049] Figure 1A and Figure 1B A schematic diagram of the structure of a quantizer for a Σ-Δ modulator according to an embodiment of the present disclosure is shown;

[0050] Figure 2A schematic diagram of the structure of a Σ-Δ modulator according to an embodiment of the present disclosure is shown;

[0051] Figure 3 A schematic diagram of the structure of a Σ-Δ modulator according to another embodiment of the present disclosure is shown;

[0052] Figure 4 A schematic diagram of the circuit structure of a first analog integrator according to an embodiment of the present disclosure is shown;

[0053] Figure 5 A schematic diagram of the circuit structure of a second analog integrator according to an embodiment of the present disclosure is shown;

[0054] Figure 6 A schematic diagram of the circuit structure of a quantizer for a Σ-Δ modulator according to an embodiment of the present disclosure is shown;

[0055] Figure 7 It shows Figure 6 Timing diagram of the quantizer circuit during the sampling and discharge cycles;

[0056] Figure 8 It shows Figure 6 Timing diagram of the passive low-pass filter in the diagram;

[0057] Figure 9 A flowchart of a noise shaping method according to an embodiment of the present disclosure is shown. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0059] Figure 1A A schematic diagram of the structure of a quantizer for a Σ-Δ modulator according to an embodiment of the present disclosure is shown.

[0060] like Figure 1A As shown, the quantizer used in the ∑-Δ modulator specifically includes: signal input terminals IN1 and IN2, integrator 101, comparator 102, two integrating capacitors Cf, a first passive low-pass filter 103, a second passive low-pass filter 104, and a signal output terminal OUT1.

[0061] Signal input terminals IN1 and IN2 are used to acquire internal signals during the Kth sampling period.

[0062] In this embodiment of the disclosure, the internal signal is specifically generated by the front-end portion of the Σ-Δ modulator based on the input signal. Specifically, the front-end portion can, for example, perform first-order noise shaping on the input signal to generate the internal signal, which will be described in detail later.

[0063] The negative and positive input ports of integrator 101 are coupled to signal inputs IN1 and IN2, respectively, for example. The positive and negative output ports of integrator 101 are coupled to the negative input port of comparator 102, for example. Integrator 101 is used to generate the quantization error signal for the Kth period based on the internal signal, the quantization error signal for the (K-1)th period, the filtered quantization error signal for the (K-1)th period, and the filtered quantization error signal for the (K-2)th period, where K is a positive integer greater than 1.

[0064] Two integrating capacitors Cf are coupled to integrator 101. The integrating capacitors Cf are used to store the quantization error signal in the Kth cycle and to weight the internal signal in the K+1th sampling cycle.

[0065] The input and output ports of the first passive low-pass filter 103 are coupled, for example, to the positive input and output ports of the integrator 101, respectively. Similarly, the input and output ports of the second passive low-pass filter 104 are coupled, for example, to the negative input and output ports of the integrator 101, respectively. Both the first passive low-pass filter 103 and the second passive low-pass filter 104 are used to acquire the quantization error signal of the Kth period during the Kth discharge cycle, and to generate a filtered quantization error signal accordingly. The filtered quantization error signal is then fed back to the integrator during the (K+1)th and (K+2)th sampling cycles.

[0066] Comparator 102 is connected to the signal output terminal OUT1. Comparator 102 is used to quantize the quantization error signal of the Kth cycle in the Kth discharge cycle, output a digital code, and provide discharge time for the discharge cycle. The digital code output by comparator 102 is output to the outside through the signal output terminal OUT1.

[0067] In this embodiment of the disclosure, the specific working process of the quantizer is as follows:

[0068] In the Kth sampling period, the internal signal is input to the quantizer through signal input terminals IN1 and IN2. Simultaneously, the first passive low-pass filter 103 and the second passive low-pass filter 104 feed back the filtered quantization error signals from the (K-1)th and (K-2)th periods, respectively, to the input terminals of the quantizer, and superimpose them with the internal signal. These three signals are then superimposed by the integrator 101 with the quantization error signal from the (K-1)th period stored in the integrating capacitor Cf to generate the quantization error signal for the Kth period. The integrating capacitor Cf stores this quantization error signal for the Kth period and is used in the (K+1)th sampling period to weight the internal signal acquired by the input terminals IN1 and IN2, as well as the filtered quantization error signal fed back to the quantizer input terminals by the first passive low-pass filter 103 and the second passive low-pass filter 104.

[0069] In the Kth discharge cycle, comparator 102 quantizes the quantization error signal of the Kth cycle, and simultaneously, the integrating capacitor Cf begins to discharge. When comparator 102 detects a reversal in the level relationship at the output port of integrator 101, the discharging of integrating capacitor Cf ends, and quantization ends. Comparator 102 detects that the comparison cycle elapsed before the reversal is the output result of the quantizer. At this time, comparator 102 quantizes the error and outputs a digital code through the signal output terminal OUT1. In some embodiments, the integrating capacitor Cf can be reverse-charged for half a comparison cycle in the last half cycle of the comparator 102 clock. This can reduce the quantization error signal on capacitor Cf to half of its original value, thereby achieving a better noise shaping effect.

[0070] During the aforementioned Kth discharge cycle, the first passive low-pass filter 103 and the second passive low-pass filter 104 respectively acquire the quantization error signal of the Kth cycle stored on the integrating capacitor Cf, and generate a filtered quantization error signal accordingly. The filtered quantization error signal is fed back to the integrator 101 during the K+1th sampling cycle and the K+2th sampling cycle.

[0071] Figure 1B A schematic diagram of the structure of a quantizer for a Σ-Δ modulator according to another embodiment of the present disclosure is shown.

[0072] like Figure 1BAs shown, the quantizer used in the Σ-Δ modulator specifically includes: signal input terminals IN1 and IN2, integrator 101, comparator 102, two integrating capacitors Cf, a first passive low-pass filter 103, a second passive low-pass filter 104, a first feedback port 105, and a signal output terminal OUT1. The signal input terminals IN1 and IN2, integrator 101, comparator 102, two integrating capacitors Cf, the first passive low-pass filter 103, the second passive low-pass filter 104, and the signal output terminal OUT1 have the same or similar functions as those described above; repeated parts will not be repeated.

[0073] In this embodiment of the present disclosure, the first feedback port 105 is coupled to the positive input port and the negative input port of the integrator 101. The first feedback port 105 is used to receive the first feedback signal from the front end in the Kth sampling period and feed the first feedback signal back to the integrator 101. The integrator 101 also integrates the internal signal based on the first feedback signal.

[0074] Integrator 101 generates the quantization error signal for the Kth sampling period based on the internal signal, the first feedback signal, the quantization error signal for the (K-1)th period, the filtered quantization error signal for the (K-1)th period, and the filtered quantization error signal for the (K-2)th period. This process is similar to the process described above and will not be repeated here.

[0075] In some embodiments of this disclosure, the first passive low-pass filter and the second passive low-pass filter include a first capacitor, a second capacitor, and a third capacitor. The first capacitor is used to acquire the quantization error signal of the Kth period during the Kth discharge cycle, and thereby generate a filtered quantization error signal, which is then fed back to the integrator in the (K+1)th sampling cycle. The second and third capacitors are used to acquire the quantization error signals of odd-numbered and even-numbered periods, respectively, and thereby generate filtered quantization error signals, which are then fed back to the integrator in the (K+2)th sampling cycle.

[0076] In this embodiment, the first passive low-pass filter 103 and the second passive low-pass filter 104 each include, for example, a first capacitor, a second capacitor, and a third capacitor (not shown in Figure 1). The first capacitor is used to acquire the quantization error signal of the Kth period during the Kth discharge cycle, and generate a filtered quantization error signal accordingly. This filtered quantization error signal is then fed back to the integrator in the (K+1)th sampling cycle. The second and third capacitors are used to acquire the quantization error signals of odd and even periods, respectively, and generate filtered quantization error signals accordingly. These filtered quantization error signals are then fed back to the integrator in the (K+2)th sampling cycle. By using the above feedback method to feed the quantization error signal back to the input of the quantizer, the first capacitor directly feeds back the filtered quantization error signal to the quantizer input in the next sampling cycle, where it is superimposed on the internal input signal. Alternatively, the second or third capacitor delays the quantization error signal for one cycle before feeding it back to the quantizer input, where it is superimposed on the internal input signal. The three paths working together can form the transfer function H(z) = 1 - z. -1 The passive low-pass filter enables the entire quantizer to have second-order noise shaping capabilities.

[0077] The second-order noise shaping capability of the quantizer in the embodiments of this disclosure will be described below.

[0078] For example, in the Kth cycle, assuming the digital signal output by the quantizer is D(z), and the input signal of the Σ-Δ modulator is X(z) (the front-end of the Σ-Δ modulator generates an internal signal based on this input signal), the quantization error signal introduced by the comparator 102 in the Kth cycle is eq(z). The digital signal D(z) output by the quantizer and the input signal X(z) satisfy the following relationship:

[0079] D(z)=X(z)-(1-z -1 )z -1 eq(z)-z -1 eq(z)+eq(z) (1)

[0080] In the above formula (1), D(z) is the digital signal output by the quantizer in the Kth cycle, X(z) is the input signal of the ∑-Δ modulator in the Kth cycle, (1-z) -1 )z -1 eq(z) is the sum of the filtered quantization error signal in the (K-1)th cycle and the filtered quantization error signal in the (K-2)th cycle fed back by the passive low-pass filter. -1 eq(z) is the quantization error signal of the (K-1)th cycle stored on the integrating capacitor, and eq(z) is the quantization error signal introduced after quantization by comparator 102 in the Kth cycle.

[0081] From formula (1), we can further obtain:

[0082] D(z)=X(z)+(1-z -1 ) 2 eq(z) (2)

[0083] As can be seen from formula (2), the quantizer in this embodiment of the present disclosure feeds back the quantization error signal to the input of the quantizer by using a passive low-pass filter structure, thereby achieving second-order noise shaping. Since the passive low-pass filter is composed of passive components, its sampling signal is the output signal of the quantizer's discharge cycle (i.e., the quantization error signal), so it does not consume additional energy. Therefore, the quantizer in this disclosure enhances the system's noise shaping capability without significantly increasing the system's power consumption. Since the passive low-pass filter consumes almost no energy, it is more energy-efficient when the modulator's effective quantization bit depth is required to be the same, thus effectively solving the problem of high power consumption in traditional second-order noise shaping integral quantizers.

[0084] Embodiments of this disclosure provide a Σ-Δ modulator, which includes a quantizer and a front-end section. The front-end section includes a front-end input port and a front-end output port, used to receive an input signal and output an internal signal, respectively, and is used to generate the internal signal based on the input signal. The quantizer in the Σ-α modulator has the same or similar structure and operation as the quantizer described above; repeated parts will not be described in detail.

[0085] In embodiments of this disclosure, the quantizer includes an integrator, an integrating capacitor, a passive low-pass filter, and a comparator.

[0086] The integrator is used to generate the quantized signal of the Kth period based on the internal signal, the quantized signal of the (K-1)th period, the filtered quantized signal of the (K-1)th period, and the filtered quantized signal of the (K-2)th period, where K is a positive integer greater than 1.

[0087] The integrating capacitor is used to store the quantized signal in the Kth cycle and to weight the internal signal in the (K+1)th sampling cycle.

[0088] A passive low-pass filter is used to acquire the quantized signal of the Kth period in the Kth discharge cycle, and generate a filtered quantized signal accordingly. The filtered quantized signal is fed back to the integrator in the (K+1)th and (K+2)th sampling cycles.

[0089] The comparator is used to quantize the quantized signal of the Kth cycle in the Kth discharge cycle to output a digital code.

[0090] In some embodiments, the passive low-pass filter includes a first passive low-pass filter and a second passive low-pass filter. The first passive low-pass filter is coupled to the positive input port and positive output port of the integrator, and the second passive low-pass filter is coupled to the negative input port and negative output port of the integrator. The first and second passive low-pass filters each include a first capacitor, a second capacitor, and a third capacitor. The first capacitor is used to acquire the quantization signal of the Kth period in the Kth discharge cycle, and generate a filtered quantization signal accordingly, feeding back the filtered quantization signal to the integrator in the (K+1)th sampling cycle. The second and third capacitors are used to acquire the quantization signals of odd and even periods, respectively, and generate filtered quantization signals accordingly, feeding back the filtered quantization signal to the integrator in the (K+2)th sampling cycle. By using a passive low-pass filter structure to feed back the quantization error signal acquired during the discharge cycle to the input of the quantizer, a transfer function H(z) = 1 - z can be formed. -1 The passive low-pass filter enables the entire quantizer to have second-order noise shaping capabilities.

[0091] The quantizer in the embodiments of this disclosure employs a passive low-pass filter structure to feed back the quantization error signal acquired during the discharge cycle to the input of the quantizer, thereby achieving second-order noise shaping. Since the passive low-pass filter is composed of passive components, and its sampled signal is the output signal of the quantizer's discharge cycle (i.e., the quantization error signal), it does not consume additional energy. Therefore, the quantizer in this disclosure enhances the system's noise shaping capability without significantly increasing system power consumption. Because the passive low-pass filter consumes almost no energy, it is more energy-efficient when the required number of effective quantization bits in the Σ-Δ modulator is the same, thus effectively reducing the quantizer's power consumption and consequently reducing the Σ-Δ modulator's power consumption.

[0092] Figure 2 A schematic diagram of the structure of a Σ-Δ modulator according to an embodiment of the present disclosure is shown.

[0093] like Figure 2 As shown, the Σ-Δ modulator includes a front-end section 21, a quantizer 22, and a signal output port OUT. The quantizer 22 includes an integrator, an integrating capacitor, a passive low-pass filter, and a comparator. The integrator, integrating capacitor, passive low-pass filter, and comparator are the same as or similar in structure and operation to those described above, and will not be repeated here.

[0094] The front-end section 21 includes a signal input port IN, a first analog integrator 211, a second analog integrator 212, and a second digital-to-analog converter 213.

[0095] The input port IN is used to receive input signals.

[0096] The second digital-to-analog converter 213 is coupled between the output port of the quantizer 22 and the second feedback port of the first analog integrator 211 and the third feedback port of the second analog integrator 212. It is used to convert the digital code output by the quantizer 22 and provide the second feedback signal accordingly.

[0097] The first analog integrator 211 is coupled between the signal input port IN and the input port of the second analog integrator 212, and is used to receive the input signal and the second feedback signal, and generate the first integrated signal accordingly.

[0098] The input port of the second analog integrator 212 is also coupled to the signal input port IN. The second analog integrator 212 is used to receive the input signal, the second feedback signal and the first integration signal, and generate the internal signal accordingly.

[0099] In some embodiments of this disclosure, the first analog integrator 211 includes four capacitors. The fourth and fifth capacitors are used to acquire the input signal and the second feedback signal, and to store the difference between the input signal and the second feedback signal. The sixth and seventh capacitors are used to receive the difference between the input signal and the second feedback signal, and to generate a first integrated signal accordingly. Using these four capacitors allows for first-order noise shaping of the input signal and the signal fed back from the second digital-to-analog converter.

[0100] In some embodiments of this disclosure, the second analog integrator 212 includes six capacitors. The eighth and ninth capacitors are used to acquire and store the first integrated signal; the tenth and eleventh capacitors are used to acquire the input signal and the second feedback signal, and store the difference between the input signal and the second feedback signal; the twelfth and thirteenth capacitors are used to receive the first integrated signal and the difference between the input signal and the second feedback signal, and generate an internal signal accordingly. Using these six capacitors, first-order noise shaping can be achieved on the input signal, the integrated signal output by the first analog integrator, and the signal fed back from the second digital-to-analog converter.

[0101] In this embodiment of the disclosure, the process of quantizer 22 receiving the internal signal and performing quantization noise shaping is the same as the process described above, and will not be repeated here.

[0102] Figure 3 A schematic diagram of the structure of a Σ-Δ modulator according to another embodiment of the present disclosure is shown.

[0103] like Figure 3As shown, the Σ-Δ modulator includes a front-end section 31, a quantizer 32, a digital integrator 33, and a signal output port OUT. The quantizer 32 includes an integrator, an integrating capacitor, a passive low-pass filter, a comparator, and a first feedback port. The integrator, integrating capacitor, passive low-pass filter, comparator, and first feedback port are the same as or similar to those described above in terms of structure and operation, and will not be repeated here.

[0104] The front-end section 31 includes a signal input port IN, a first analog integrator 311, a second analog integrator 312, a first digital-to-analog converter 314, and a second digital-to-analog converter 313.

[0105] The input port IN is used to receive input signals.

[0106] The first digital-to-analog converter 314 is coupled between the output port of the quantizer 32 and the fourth feedback port of the second analog integrator 312, and is used to convert the digital code output by the quantizer 32 and provide the first feedback signal accordingly.

[0107] The second digital-to-analog converter 313 is coupled between the output port of the digital integrator 33 and the second feedback port of the first analog integrator 311 and the third feedback port of the second analog integrator 312. It is used to convert the digital code output by the digital integrator 33 and provide the second feedback signal accordingly.

[0108] The first analog integrator 311 is coupled between the signal input port IN and the input port of the second analog integrator 312, and is used to receive the input signal and the second feedback signal, and generate the first integrated signal accordingly.

[0109] In some embodiments of this disclosure, the first analog integrator 311 includes four capacitors, wherein the fourth and fifth capacitors are used to acquire the input signal and the second feedback signal, and to store the difference between the input signal and the second feedback signal. The sixth and seventh capacitors are used to receive the difference between the input signal and the second feedback signal, and to generate the first integrated signal accordingly.

[0110] The input port of the second analog integrator 312 is also coupled to the signal input port IN. The second analog integrator 312 is used to receive the input signal, the first integrated signal, the second feedback signal, and the first feedback signal, and to generate an internal signal accordingly.

[0111] In some embodiments of this disclosure, the second analog integrator 312 includes six capacitors, wherein the eighth and ninth capacitors are used to acquire the first integration signal and the first feedback signal, and store the difference between the first integration signal and the first feedback signal; the tenth and eleventh capacitors are used to acquire the input signal and the second feedback signal, and store the difference between the input signal and the second feedback signal; the twelfth and thirteenth capacitors are used to receive the difference between the first integration signal and the first feedback signal, as well as the difference between the input signal and the second feedback signal, and generate an internal signal accordingly.

[0112] In this embodiment of the disclosure, after the quantizer 32 receives the internal signal and the first feedback signal, the process of performing quantization noise shaping is the same as the process described above, and will not be repeated here.

[0113] In this embodiment of the disclosure, the digital integrator 33 is coupled to the output port of the quantizer 32 and is used to integrate the digital code output by the quantizer 32 to provide the integrated digital code.

[0114] A digital integrator is essentially an adder that can accumulate received digital codes, such as 3-bit digital codes, to obtain, for example, 5-bit digital codes, and then transmit them to the signal output port OUT as the system output.

[0115] In this embodiment of the Σ-Δ modulator, after the addition of the digital integrator 33 and the feedback path of the first digital-to-analog converter 314, the input signal of the quantizer 32 becomes the difference between the output signal of the second analog integrator 312 in the current cycle and the output signal of the second analog integrator 312 in the previous cycle. Due to the structural characteristics of the Σ-Δ modulator, the sampling frequency is much higher than the input signal bandwidth, and the maximum value of the signal difference in the integration path will be much smaller than the maximum value of the output signal in the integration path. Therefore, adding the digital integrator 33 and the feedback path of the first digital-to-analog converter 314 will improve the stability of the Σ-Δ modulator.

[0116] The principle of how the quantizer changes the loop transfer function of the Σ-Δ modulator in the embodiments of this disclosure will be briefly explained below.

[0117] For example, in the Kth period (K is a positive integer greater than 1), assuming the loop transfer function of the Σ-Δ modulator is H'(z), the input signal of the Σ-Δ modulator is X(z), and the filtered quantization error signal added to the Σ-Δ modulator due to the quantizer is Q(z), in this embodiment, since the integration path adopts a two-stage integral negative feedback structure, the loop transfer function of the Σ-Δ modulator satisfies the following relationship:

[0118] H′(z)=STF·X(z)+(1-z -1 ) 2 Q(z) (3)

[0119] Wherein, STF is the signal transfer function, which is approximately 1 in this embodiment.

[0120] Since the quantization error signal of the (K-1)th cycle is stored on the integrating capacitor and then filtered by a passive low-pass filter before being fed back to the quantizer input, the quantization error of the (K-1)th cycle, the quantization error of the (K-2)th cycle, and the quantization error of the Kth cycle are superimposed to obtain:

[0121] Q(z) = (1-2z) -1 +z -2 )eq(z) (4)

[0122] In the above formula (4), eq(z) is the quantization error of the Kth cycle introduced by the comparator quantization.

[0123] The quantization noise representation of Q(z) is as follows:

[0124] H′(z)=STF·X(z)+(1-z -1 ) 4 eq(z) (5)

[0125] As shown in formula (5), the Σ-Δ modulator of this embodiment completes fourth-order noise shaping for quantization noise. Furthermore, the quantizer in the Σ-Δ modulator employs a passive low-pass filter structure to feed back the quantization error signal collected during the discharge cycle to the input of the quantizer. Since the passive low-pass filter is composed of passive components, its sampled signal is the output signal of the quantizer's discharge cycle (i.e., the quantization error signal), so it does not consume additional energy. Therefore, the quantizer in this disclosure enhances the system's noise shaping capability without significantly increasing system power consumption. Because the passive low-pass filter consumes almost no energy, it is more energy-efficient when the Σ-Δ modulator requires the same number of effective quantization bits, thereby effectively reducing the quantizer's power consumption and consequently reducing the Σ-Δ modulator's power consumption. In other words, the Σ-Δ modulator in this embodiment can achieve fourth-order noise shaping with low power consumption.

[0126] Figure 4 and Figure 5 The circuit structure diagrams of the first analog integrator and the second analog integrator according to embodiments of the present disclosure are shown respectively. Figure 6 A schematic diagram of the circuit structure of a quantizer for a Σ-Δ modulator according to an embodiment of the present disclosure is shown. Figure 7 It shows Figure 6 Timing diagram of the quantizer circuit during the sampling and discharge cycles. Figure 8 It shows Figure 6 The timing diagram of the passive low-pass filter in the image is shown below. Figure 3 Taking the Σ-Δ modulator structure in the example, combined with Figures 4 to 8 right Figure 3 The specific working process of the first analog integrator, the second analog integrator, and the quantizer in the model is explained in detail.

[0127] It should be understood that Figures 4 to 8 The content shown is only for the purpose of helping those skilled in the art to understand the technical solution of this disclosure, and is not intended to limit the scope of protection of this disclosure.

[0128] like Figure 4 As shown, the first analog integrator 311 ( Figure 3 The circuit (shown in the diagram) includes signal input ports IN3 and IN4, signal output ports OUT2 and OUT3, capacitors C1 (i.e., the fourth capacitor), C2 (i.e., the fifth capacitor), C3 (i.e., the sixth capacitor), and C4 (i.e., the seventh capacitor), a second feedback port 401, a fully differential operational amplifier 402, and switches 1 to 12, etc.

[0129] The first analog integrator 311 has three operating modes: a reset phase, a sampling phase, and a computation phase.

[0130] After the circuit starts up, the first analog integrator 311 first enters the reset phase. At this time, switches 9, 10, 11, and 12 are closed, while other switches are open. Capacitors C3 and C4 are reset to zero charge. This is done to prevent residual charge from the previous signal processing from affecting the current signal processing. Typically, the reset phase only occurs once during signal processing, after which the first analog integrator 311 continuously cycles between the sampling phase and the computation phase.

[0131] After the first analog integrator 311 circuit is reset, it enters the sampling stage. At this time, switches 1, 3, 4, and 6 are closed, and other switches are open. The current input signal is input from signal input ports IN3 and IN4, and the second feedback signal fed back by the second digital-to-analog converter 313 is input from the second feedback port 401. The voltage difference between the current input signal and the second feedback signal will be stored in capacitors C1 and C2 (equivalent to completing the difference operation).

[0132] During the operation phase, switches 2, 5, 7, and 8 are closed, while the other switches are open. The fully differential operational amplifier 402 transfers the charge stored in capacitors C1 and C2 to capacitors C3 and C4 according to the law of charge conservation, achieving first-order noise shaping. The first integrated signal is then output from signal output ports OUT2 and OUT3.

[0133] For ease of explanation and understanding, the following will use the example of capacitors C1 and C2 having equal capacitance values ​​and capacitors C3 and C4 having equal capacitance values ​​to explain the principle of the first analog integrator implementing first-order noise shaping.

[0134] During the sampling phase of the Nth cycle, the current input signal is sampled and stored on capacitors C1 and C2, and the total charge is denoted as C. 1，2 V in (N). During the Nth cycle of operation, capacitors C3 and C4 store the voltage signals transferred during the (N-1)th cycle of operation, and the total charge is denoted as C. 3，4 V out (N-1), the charge on capacitors C1 and C2 becomes C after a delay. 1，2 V in (N-1). During the Nth cycle of operation, according to the law of conservation of charge, the charge stored in the capacitor is transferred and redistributed. This charge transfer equation can be expressed as:

[0135] C 3，4 V out (N)=C 1，2 V in (N-1)+C 3，4 V out (N-1) (6)

[0136] Performing a z-transform on it, we get:

[0137] C 3，4 V out (z)=C 1，2 V in (z)z -1 +C 3，4 V out (z)z -1 (7)

[0138] After a simple transformation, the transfer function of the first analog integrator can be obtained:

[0139]

[0140] In this embodiment, the ratio of capacitors C1 and C3 can be set to, for example, 0.2 to 0.5. For instance, setting the ratio of capacitors C1 and C3 to 0.2 can reduce the input signal to 0.2 times its original size, while simultaneously performing first-order noise shaping on the input signal. It should be understood that the values ​​shown above are only for the purpose of facilitating understanding of the technical solutions of this disclosure by those skilled in the art and are not intended to limit the scope of protection of this disclosure. In other embodiments, the ratio of capacitors C1 and C3 can be set according to actual needs to achieve different degrees of reduction or amplification of different input signals and to complete first-order noise shaping; this is not limited here.

[0141] like Figure 5 As shown, the second analog integrator 312 ( Figure 3The circuit (shown in the diagram) includes signal input ports IN3' and IN4', signal output ports OUT4 and OUT5, capacitors C1' (eighth capacitor), C2' (ninth capacitor), C3' (twelfth capacitor), C4' (thirteenth capacitor), C5 (tenth capacitor), and C6 (eleventh capacitor), a third feedback port 501, a fourth feedback port 502, a fully differential operational amplifier 503, and switches 1' to 16, etc.

[0142] The second analog integrator 312 has a similar working mode and operating principle to the first analog integrator 311, and will be briefly described here.

[0143] The second analog integrator 312 operates in three modes: a reset phase, a sampling phase, and a computation phase.

[0144] After the circuit starts up, the second analog integrator 312 first enters the reset phase. At this time, switches 9', 10', 11', and 12' are closed, while the other switches are open. Capacitors C3' and C4' are reset to have zero charge on them. This is done to prevent residual charge from the previous signal processing from affecting the current signal processing. Typically, the reset phase only occurs once during signal processing, after which the second analog integrator 312 continuously cycles between the sampling phase and the computation phase.

[0145] After the second analog integrator 312 circuit is reset, it enters the sampling stage. At this time, switches 1', 3', 4', 6', 13, and 15 are closed, while other switches are open. The first integrated signal output by the first analog integrator 311 is input from signal input ports IN3' and IN4', and the first feedback signal from the first digital-to-analog converter 314 is input from the third feedback port 501. The current input signal is input from signal input ports IN5 and IN6, and the second feedback signal from the second digital-to-analog converter 313 is input from the fourth feedback port 502. At this time, capacitors C1' and C2' will store the voltage difference between the first integrated signal and the first feedback signal, and capacitors C5 and C6 will store the voltage difference between the current input signal and the second feedback signal.

[0146] During the operation phase, switches 2, 5, 7, 8, 14, and 16 are closed, while other switches are open. The fully differential operational amplifier 503 transfers the charge stored in capacitors C1', C2', C5, and C6 to capacitors C3' and C4' according to the law of conservation of charge, achieving first-order noise shaping. Afterward, the internal signal is output from output ports OUT4 and OUT5 to quantizer 32.

[0147] The second analog integrator operates on a similar principle to the first analog integrator. For ease of explanation and understanding, the following will use the following examples of equal capacitance values ​​for capacitors C1' and C2', equal capacitance values ​​for capacitors C3' and C4', and equal capacitance values ​​for capacitors C5 and C6 to illustrate the principle of first-order noise shaping implemented by the second analog integrator.

[0148] During the sampling phase of the Nth cycle, the difference between the first integral signal and the first feedback signal is stored in capacitors C1' and C2', and the total charge is denoted as C. 1’，2’ V out1 (N), the difference between the current input signal and the second feedback signal is stored in capacitors C5 and C6, and the total charge is denoted as C. 5，6 V in (N). During the Nth cycle of operation, capacitors C3' and C4' store the voltage signals transferred during the (N-1)th cycle of operation, and the total charge is denoted as C. 3’，4’ V out (N-1), the charge on capacitors C1' and C2' becomes C after a delay. 1’，2’ V out1 (N-1), the charge on capacitors C5 and C6 becomes C after a delay. 5，6 V in (N-1). During the Nth cycle of operation, according to the law of conservation of charge, the charge stored in the capacitor is transferred and redistributed. This charge transfer equation can be expressed as:

[0149] C 3’，4’ V out (N)=C 1’，2’ V out1 (N-1)+C 5，6 V in (N-1)+C 3’，4’ V out (N-1) (9)

[0150] Performing a z-transform on it, we get:

[0151] C 3’，4’ V out (z)=C 1’，2’ V out1 (z)z -1 +C 5，6 V in (z)z -1 +C 3′，4′ V out (z)z -1 (10)

[0152] In this embodiment, the ratio of capacitors C1' and C5 can be set to, for example, 0.4 to 0.6. For example, setting the ratio of capacitors C1' and C5 to 0.5, and making a simple transformation, the transfer function of the second analog integrator can be obtained:

[0153]

[0154] In this embodiment, for example, by setting the ratio of capacitors C5 and C3' to 0.5, the input signal can be reduced to 0.5 times its original size, while simultaneously performing first-order noise shaping on the input signal. It should be understood that the values ​​shown above are only for the purpose of facilitating understanding of the technical solutions of this disclosure by those skilled in the art and are not intended to limit the scope of protection of this disclosure. In other embodiments, the ratios of capacitors C5 and C1' and C5 and C3' can be set according to actual needs to achieve different degrees of reduction or amplification of different input signals and to complete first-order noise shaping; this is not a limitation.

[0155] Figure 6 A schematic diagram of the circuit structure of a quantizer for a Σ-Δ modulator according to an embodiment of the present disclosure is shown.

[0156] like Figure 6 As shown, the quantizer mainly includes signal input terminals IN1 and IN2, an integrator 601, a comparator 602, two integrating capacitors Cf, a first passive low-pass filter 603, a second passive low-pass filter 604, and a first feedback port 605. The first passive low-pass filter 603 and the second passive low-pass filter 604 have the same structure and operating principle. In this embodiment, the operation of the passive low-pass filter will be explained using the first passive low-pass filter 603 as an example.

[0157] The first passive low-pass filter 603 includes capacitors C11, C7, and C8, as well as corresponding control switches. For example, The corresponding control capacitor is C7. Corresponding control capacitor C8 ( Figure 6 The dashed "×2" indicates that C7 and C8 each have corresponding control circuits. Capacitor C11 is equivalent to the first capacitor, used to acquire the quantization error signal of the Kth period in the Kth discharge cycle, and generate a filtered quantization error signal accordingly. The filtered quantization error signal is then fed back to the integrator in the (K+1)th sampling cycle. Capacitors C7 and C8 are equivalent to the second and third capacitors, respectively, used to acquire the quantization error signals of odd and even periods, and generate filtered quantization error signals accordingly. The filtered quantization error signals are then fed back to the integrator in the (K+2)th sampling cycle.

[0158] Figure 7 It shows Figure 6Timing diagram of the quantizer circuit during the sampling and discharge cycles. Figure 8 It shows Figure 6 The timing diagram of the passive low-pass filter in the image is shown below. The following will combine... Figure 7 and Figure 8 right Figure 6 The working process of the circuit in the diagram will be explained in detail.

[0159] The quantizer 32 operates in three modes: a reset cycle, a sampling cycle, and a discharge cycle. The reset cycle is similar to the reset phase of the first analog integrator 311, primarily aimed at clearing residual charge from the capacitors to prevent any remaining charge from the previous signal processing from affecting the current signal processing. Typically, the reset cycle occurs only once during signal processing; afterwards, the quantizer 32 operates during the sampling cycle and the discharge cycle. Figure 7 The timing signals φs and φd shown in the figure represent the sampling period and the discharge period, respectively, and they cycle continuously.

[0160] During the Kth sampling period φs, the internal signal is input from signal input ports IN1 and IN2. Simultaneously, the first feedback signal from the first digital-to-analog converter 314 is input from the first feedback port 605. Furthermore, the transfer function is (1-z... -1 The passive low-pass filters (including the first passive low-pass filter 603 and the second passive low-pass filter 604) also feed back the filtered quantization error signal of the (K-1)th cycle (e.g., the filtered quantization error signal of the (K-1)th cycle fed back by capacitors C11 and C12) and the filtered quantization error signal of the (K-2)th cycle (e.g., the filtered quantization error signal of the (K-2)th cycle fed back by capacitors C7 and C9) to the input of the quantizer. These signals are superimposed on capacitor Cs, integrated by integrator 601, and superimposed with the quantization error signal of the (K-1)th cycle stored on capacitor Cf to generate the quantization error signal of the Kth cycle, which is then stored on capacitor Cf. Figure 7 Curve 710 shown represents the output voltage Vout of the integrating capacitor Cf (Vout = Vop - Von), as... Figure 7 As shown, during the sampling period s, the quantization error signal of the Kth period will be stored on the integrating capacitor Cf.

[0161] In the Kth discharge cycle φd, comparator 602 quantizes the quantization error signal of the Kth cycle. The discharge direction can be determined by comparator 602, enabling... or Set 1 ( Figure 6 (As shown in the figure), at this time the integrating capacitor Cf begins to discharge.

[0162] The duty cycle of comparator 602 is as follows Figure 7 As shown in the middle wave 720, comparator 602 performs multiple comparisons during the discharge cycle. During this stage, comparator 602 alternately operates. For each pulse in pulses 721[1], 722[2], 723[3], and 724[n], comparator 602 quantizes the input signal and generates a digital code.

[0163] like Figure 7 As shown, during the discharge process of the integrating capacitor Cf ( Figure 7 The one shown (This represents the discharge time of the integrating capacitor Cf). The absolute value of the output voltage Vout of the integrating capacitor Cf will gradually decrease. Figure 7 (Curve 710 shown in the figure). When comparator 602 detects a reversal in the magnitude relationship between Vop and Von, the discharge ends. Set to 0. At this point, the quantization process ends. The number of comparison cycles before comparator 602 inverts is the quantizer's output. The quantization error is then output as a digital code. During the last half-cycle of comparator 602's clock ( Figure 7 The one shown During the phase, the integrating capacitor Cf is reverse-charged for half a comparison cycle. Figure 7 The 711 process shown in the figure reduces the quantization error signal on capacitor Cf to half of its original value.

[0164] The operating timing of the first passive low-pass filter 603 is as follows: Figure 8 As shown. Figure 8 In and They represent Figure 6 The switch corresponding to capacitor C11 and Work sequence, and These represent the switches corresponding to capacitor C7. and Work sequence, and These represent the switches corresponding to capacitor C8. and The work sequence.

[0165] like Figure 8 As shown, in the Kth discharge cycle, control and Closed (e.g.) Figure 8 The pulse signals 810 and 830 shown in the figure are displayed. Other switches are turned off. At this time, capacitors C11 and C7 respectively collect and hold the quantization error signal of the Kth cycle on the integrating capacitor Cf.

[0166] In the (K+1)th sampling period, control and Closed (e.g.) Figure 8 The pulse signals 820 and 860 shown in the figure are turned off. The other switches are turned off. The quantization error signal of the Kth cycle stored in capacitor C11 is fed back to the input of the quantizer. The quantization error signal of the (K-1)th cycle stored in capacitor C8 is fed back to the input of the quantizer (that is, the quantization error signal stored in capacitor C8 is delayed by one cycle before being fed back to the input of the quantizer).

[0167] In the (K+1)th discharge cycle, control and Closed (e.g.) Figure 8 The pulse signals 811 and 850 shown in the figure are displayed. Other switches are turned off. At this time, capacitors C11 and C8 respectively collect the quantization error signal of the K+1th cycle on the integrating capacitor Cf and hold it.

[0168] In the (K+2)th sampling period, control and Closed (e.g.) Figure 8 The pulse signals 821 and 840 shown in the figure are turned off. The other switches are turned off. The quantization error signal of the (K+1)th cycle stored on capacitor C11 is fed back to the input of the quantizer. The quantization error signal of the Kth cycle stored on capacitor C7 is fed back to the input of the quantizer (that is, the quantization error signal stored on capacitor C7 is fed back to the input of the quantizer after a delay of one cycle).

[0169] In this embodiment of the disclosure, capacitor C11 in the passive low-pass filter directly feeds back the acquired quantization error signal to the input of the quantizer in the next sampling period, while capacitors C7 and C8 work alternately, feeding back the acquired quantization error signal to the input of the quantizer after a one-period delay. Through this method, a transfer function of (1-z) can be formed. -1 A passive low-pass filter.

[0170] The quantizer in the embodiments of this disclosure uses the aforementioned passive low-pass filter structure to feed back the quantization error signal acquired during the discharge cycle to the input of the quantizer, thereby achieving second-order noise shaping. Since the passive low-pass filter is composed of passive components, and its sampled signal is the output signal of the quantizer's discharge cycle (i.e., the quantization error signal), it does not consume additional energy. Therefore, the quantizer in this disclosure enhances the system's noise shaping capability without significantly increasing system power consumption. Because the passive low-pass filter consumes almost no energy, it is more energy-efficient when the required number of effective quantization bits in the Σ-Δ modulator is the same, thus effectively reducing the quantizer's power consumption and consequently reducing the Σ-Δ modulator's power consumption.

[0171] Figure 9A flowchart of a noise shaping method according to an embodiment of the present disclosure is shown.

[0172] like Figure 9 As shown, the noise shaping method includes operations S910 to S930.

[0173] During operation of S910, in the Kth sampling period, the integrator acquires the internal signal, the quantization error signal of the (K-1)th period stored in the integrating capacitor, the filtered quantization error signal of the (K-1)th period fed back by the passive low-pass filter, and the filtered quantization error signal of the (K-2)th period, and generates the quantization error signal of the Kth period accordingly. The quantization error signal of the Kth period is stored in the integrating capacitor and used to weight the internal signal in the (K+1)th sampling period, where K is a positive integer greater than 1.

[0174] During operation of S920, in the Kth discharge cycle, the quantization error signal of the Kth cycle is acquired through a passive low-pass filter, and a filtered quantization error signal is generated accordingly. The filtered quantization error signal is then fed back to the integrator in the K+1th and K+2th sampling cycles.

[0175] When operating the S930, the quantization error signal of the Kth cycle is quantized by a comparator to output a digital code.

[0176] In some embodiments of this disclosure, the above operation S920, which involves acquiring the quantization error signal of the Kth period through a passive low-pass filter and generating a filtered quantization error signal accordingly, and feeding back the filtered quantization error signal to the integrator in the (K+1)th and (K+2)th sampling periods, further includes operations S921 to S922.

[0177] In operation S921, the first capacitor is used to acquire the quantization error signal of the Kth cycle, and a filtered quantization error signal is generated accordingly. The filtered quantization error signal is then fed back to the integrator in the K+1th sampling cycle.

[0178] When operating the S922, the second and third capacitors are used to acquire the quantization error signals of odd and even periods respectively, and a filtered quantization error signal is generated accordingly. The filtered quantization error signal is then fed back to the integrator in the K+2 sampling period.

[0179] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A quantizer for a Σ-Δ modulator, characterized in that, include: An integrator is used to generate the quantization error signal for the Kth period based on the internal signal, the quantization error signal for the (K-1)th period, the filtered quantization error signal for the (K-1)th period, and the filtered quantization error signal for the (K-2)th period; where K is a positive integer greater than 1. An integrating capacitor is used to store the quantization error signal in the Kth period and to weight the internal signal in the (K+1)th sampling period; A passive low-pass filter is used to acquire the quantization error signal of the Kth discharge cycle, generate a filtered quantization error signal accordingly, and feed back the filtered quantization error signal to the integrator in the (K+1)th and (K+2)th sampling cycles. as well as A comparator is used to quantize the quantization error signal of the Kth cycle in the Kth discharge cycle to output a digital code.

2. The quantizer for a Σ-Δ modulator according to claim 1, characterized in that, The passive low-pass filter includes: a first passive low-pass filter and a second passive low-pass filter; wherein, the first passive low-pass filter is coupled to the positive input port and the positive output port of the integrator; and the second passive low-pass filter is coupled to the negative input port and the negative output port of the integrator. The first passive low-pass filter and the second passive low-pass filter include: A first capacitor is used to acquire the quantization error signal of the Kth discharge cycle, generate a filtered quantization error signal accordingly, and feed back the filtered quantization error signal to the integrator in the (K+1)th sampling cycle; and The second and third capacitors are used to acquire quantization error signals for odd and even periods, respectively, and generate filtered quantization error signals accordingly. The filtered quantization error signals are then fed back to the integrator in the (K+2)th sampling period.

3. A Σ-Δ modulator, characterized in that, include: A quantizer, wherein the quantizer is the quantizer described in claim 1 or 2; The front-end section includes a front-end input port and a front-end output port, which are used to receive input signals and output internal signals, respectively, and the front-end section is used to generate the internal signals based on the input signals.

4. The Σ-Δ modulator according to claim 3, characterized in that, The front-end section includes a first analog integrator, a second analog integrator, and a second digital-to-analog converter. The second digital-to-analog converter is coupled between the output port of the quantizer and the second feedback port of the first analog integrator and the third feedback port of the second analog integrator, and is used to convert the digital code output by the quantizer and provide a second feedback signal accordingly. A first analog integrator is used to receive the input signal and the second feedback signal, and generate a first integrated signal accordingly; The second analog integrator is used to receive the input signal, the second feedback signal and the first integral signal, and generate the internal signal accordingly.

5. The Σ-Δ modulator according to claim 3, characterized in that, The front-end section also includes a first digital-to-analog converter, used to convert the digital code output by the quantizer and provide a first feedback signal accordingly; The quantizer further includes a first feedback port, coupled to the positive input port and negative input port of the integrator and the output port of the first digital-to-analog converter, for receiving the first feedback signal; The integrator also integrates the internal signal based on the first feedback signal.

6. The Σ-Δ modulator according to claim 5, characterized in that, The Σ-Δ modulator also includes a digital integrator coupled to the output port of the quantizer, used to integrate the digital code output by the quantizer to provide integrated digital code.

7. The Σ-Δ modulator according to claim 6, characterized in that, The front-end section includes a first analog integrator, a second analog integrator, and a second digital-to-analog converter. The second digital-to-analog converter is coupled between the output port of the digital integrator and the second feedback port of the first analog integrator and the third feedback port of the second analog integrator, and is used to convert the digital code output by the digital integrator and provide a second feedback signal accordingly. A first analog integrator is used to receive the input signal and the second feedback signal, and generate a first integrated signal accordingly; The second analog integrator also includes a fourth feedback port, coupled to the output port of the first digital-to-analog converter, for receiving the first feedback signal; The second analog integrator also generates the internal signal based on the input signal, the first integral signal, the second feedback signal, and the first feedback signal.

8. The Σ-Δ modulator according to claim 4 or 7, characterized in that, The first analog integrator includes four capacitors, wherein: The fourth and fifth capacitors are used to acquire the input signal and the second feedback signal, and to save the difference between the input signal and the second feedback signal; The sixth and seventh capacitors are used to receive the difference between the input signal and the second feedback signal, and to generate the first integral signal accordingly.

9. The Σ-Δ modulator according to claim 4, characterized in that, The second analog integrator includes six capacitors, wherein: The eighth and ninth capacitors are used to acquire the first integrated signal and save the first integrated signal; The tenth and eleventh capacitors are used to acquire the input signal and the second feedback signal, and to save the difference between the input signal and the second feedback signal; The twelfth and thirteenth capacitors are used to receive the first integrated signal and the difference between the input signal and the second feedback signal, and to generate the internal signal accordingly.

10. The Σ-Δ modulator according to claim 7, characterized in that, The second analog integrator includes six capacitors, wherein: The eighth and ninth capacitors are used to acquire the first integrated signal and the first feedback signal, and to save the difference between the first integrated signal and the first feedback signal. The tenth and eleventh capacitors are used to acquire the input signal and the second feedback signal, and to save the difference between the input signal and the second feedback signal; The twelfth and thirteenth capacitors are used to receive the difference between the first integrated signal and the first feedback signal, as well as the difference between the input signal and the second feedback signal, and to generate the internal signal accordingly.

11. A noise shaping method, characterized in that, include: During the Kth sampling period, the integrator acquires the internal signal, the quantization error signal of the (K-1)th period stored on the integrating capacitor, the filtered quantization error signal of the (K-1)th period fed back by the passive low-pass filter, and the filtered quantization error signal of the (K-2)th period, and generates the quantization error signal of the Kth period accordingly; wherein, the quantization error signal of the Kth period is stored on the integrating capacitor to weight the internal signal in the (K+1)th sampling period; where K is a positive integer greater than 1; During the Kth discharge cycle, the quantization error signal of the Kth cycle is acquired through the passive low-pass filter, and a filtered quantization error signal is generated accordingly, so as to feed the filtered quantization error signal back to the integrator in the K+1 sampling cycle and the K+2 sampling cycle. as well as The quantization error signal of the Kth cycle is quantized by a comparator to output a digital code.

12. The noise shaping method according to claim 11, characterized in that, The step of acquiring the quantization error signal of the Kth period through the passive low-pass filter and generating a filtered quantization error signal accordingly, and feeding the filtered quantization error signal back to the integrator in the (K+1)th and (K+2)th sampling periods, includes: The quantization error signal of the Kth period is acquired using the first capacitor, and a filtered quantization error signal is generated accordingly. This filtered quantization error signal is then fed back to the integrator in the (K+1)th sampling period. The second and third capacitors are used to acquire quantization error signals for odd and even periods, respectively, and a filtered quantization error signal is generated accordingly. The filtered quantization error signal is fed back to the integrator in the (K+2)th sampling period.

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