Chip growth array, system, method, apparatus, medium, substrate and device

Abstract

Embodiments of the present disclosure provide a chip growth array, system, method, device, medium, substrate and apparatus. The chip growth array comprises a substrate (1) and a plurality of to-be-transferred chips (2) arranged in an array on the substrate (1); the to-be-transferred chip (2) comprises a first electrode (21) and a second electrode (22); the first electrode (21) and / or the second electrode (22) forms a dam structure, and a transfer adhesive (23) is arranged in the dam structure. The technical scheme provided by the embodiments of the present disclosure forms a dam structure by the first electrode and / or the second electrode of the to-be-transferred chip, and the transfer adhesive is arranged in the dam structure. The first electrode and the second electrode are not provided with the transfer adhesive, and the electrode on the chip can be exposed without setting a degumming process in subsequent chip transfer. Therefore, such a structure design can effectively reduce the complexity of the chip preparation process.

Description

Technical Field

[0001] This disclosure relates to a chip growth array, system, method, apparatus, medium, substrate, and device. Background Technology

[0002] The fabrication size of light-emitting diodes (LEDs) is trending towards miniaturization. For example, micro LED (Micro Light Emitting Diode) technology or mini LED (Mini Light Emitting Diode) technology refers to a high-density array of tiny LEDs integrated on a single substrate. These LEDs have wide applications in displays, visible light communication, and smart portable devices. Due to their small size, low power consumption, and long lifespan, they are attracting increasing attention.

[0003] In LED chip fabrication, substrate removal and transfer are required. After substrate removal, the LED chip is typically mounted on a temporary substrate. Currently, a temporary substrate with laser-applied adhesive is commonly used. The sapphire substrate and the temporary substrate are bonded together using this adhesive, and the LED chip is embedded within it. When the LED chip is subsequently transferred using a laser, adhesive residue remains on the electrodes. This necessitates additional processes to remove this residue and expose the electrodes, increasing the complexity of the LED chip fabrication process. Summary of the Invention

[0004] (a) Technical problems to be solved

[0005] In existing LED chip manufacturing processes, there is a problem of adhesive residue on the electrodes of the LED chip, which requires additional processes to remove the adhesive residue, making the chip manufacturing process complex.

[0006] (II) Technical Solution

[0007] According to various embodiments of this disclosure, a chip growth array, system, method, apparatus, medium, substrate, and device are provided.

[0008] A chip growth array includes: a substrate and a plurality of chips to be transferred arranged in an array on the substrate;

[0009] The chip to be transferred includes a first electrode and a second electrode;

[0010] The first electrode and / or the second electrode are arranged to form a retaining wall structure, and a transfer adhesive is disposed within the retaining wall structure.

[0011] As an optional embodiment of this disclosure, the retaining wall structure has an opening at its edge.

[0012] As an optional implementation of this disclosure, the depth of the opening is less than the thickness of the retaining wall structure.

[0013] As an optional embodiment of this disclosure, the width of the opening is greater than or equal to 1 micrometer and less than or equal to 5 micrometers, along the direction perpendicular to the direction in which the transfer adhesive flows out at the opening.

[0014] As an optional embodiment of this disclosure, the width of the opening is equal to the width of the retaining wall structure, along the direction in which the transfer adhesive flows out at the opening.

[0015] As an optional implementation of this disclosure, the opening includes a first side and a second side disposed opposite to each other;

[0016] The first side is the side where the opening faces the transfer adhesive, and the second side is the side where the opening faces away from the transfer adhesive; the depth of the opening on the first side is less than the depth of the opening on the second side.

[0017] As an optional embodiment of this disclosure, the retaining wall structure includes a first retaining wall structure and a second retaining wall structure; the first electrode surrounds to form the first retaining wall structure, and the second electrode surrounds to form the second retaining wall structure; the first electrode and the second electrode are disposed in the same layer;

[0018] The distance between the surface of the first barrier structure facing away from the substrate and the substrate is equal to the distance between the surface of the second barrier structure facing away from the substrate and the substrate.

[0019] As an optional implementation of this disclosure, the first retaining wall structure is located outside the second retaining wall structure.

[0020] As an optional embodiment of this disclosure, in a direction perpendicular to the substrate, the thickness of the first barrier structure is equal to the thickness of the second barrier structure.

[0021] As an optional embodiment of this disclosure, a passivation layer is provided between the first electrode and the second electrode and the substrate;

[0022] The thickness of the passivation layer located within the retaining wall structure is less than or equal to the thickness of the passivation layer located outside the retaining wall structure.

[0023] As an optional embodiment of this disclosure, the transfer adhesive includes a laser adhesive layer.

[0024] A chip transfer system includes a first transfer substrate, a second transfer substrate, and a chip growth array provided in this disclosure;

[0025] The first transfer substrate is configured to be bonded to the transfer adhesive of the chip growth array;

[0026] The second transfer substrate is configured to carry the chip to be transferred and stripped from the first transfer substrate.

[0027] A chip transfer method for the system provided in this disclosure includes:

[0028] Multiple chips to be transferred are generated in an array on the substrate to form the chip growth array; wherein, the chip to be transferred includes a first electrode and a second electrode; the first electrode and / or the second electrode surrounds a barrier structure, and transfer adhesive is disposed within the barrier structure;

[0029] The substrate is removed, the chip to be transferred is peeled off and transferred from the chip growth array, and the chip to be transferred is fixedly disposed on the first transfer substrate; wherein, the first transfer substrate is bonded to the chip growth array by the transfer adhesive;

[0030] The chip to be transferred, which is disposed on the first transfer substrate, is peeled off and transferred to the second transfer substrate.

[0031] As an optional implementation of this disclosure, the step of generating a plurality of chips to be transferred in an array on the substrate to form the chip growth array includes:

[0032] A first semiconductor layer, a light-emitting layer, and a second semiconductor layer are sequentially grown on the substrate.

[0033] Etch the second semiconductor layer, the light-emitting layer and the first semiconductor layer to form a connection via in the first semiconductor layer;

[0034] A current diffusion layer is formed on a portion of the second semiconductor layer;

[0035] The first semiconductor layer, the light-emitting layer, and the second semiconductor layer are etched to form a plurality of chip dies to be transferred in an array;

[0036] A passivation layer is formed on a portion of the current diffusion layer and the second semiconductor layer;

[0037] The first electrode and the second electrode are formed on the current diffusion layer, the first semiconductor layer connection via, and the passivation layer; wherein the first electrode and / or the second electrode surround the barrier structure.

[0038] The transfer adhesive is formed within the retaining wall structure.

[0039] As an optional implementation of this disclosure, the method further includes: etching the retaining wall structure to form an opening at the edge of the retaining wall structure.

[0040] As an optional embodiment of this disclosure, the method further includes: etching the passivation layer so that the thickness of the passivation layer located within the retaining wall structure is less than the thickness of the passivation layer located outside the retaining wall structure.

[0041] A computer device includes: a memory and one or more processors, the memory storing computer-readable instructions; when executed by the one or more processors, the computer-readable instructions cause the one or more processors to perform the steps of the chip transfer method provided in any embodiment of this disclosure.

[0042] One or more non-volatile computer-readable storage media storing computer-readable instructions, which, when executed by one or more processors, cause the one or more processors to perform the steps of the chip transfer method provided in any embodiment of this disclosure.

[0043] A display substrate includes a plurality of chips to be transferred using a chip transfer system provided in any embodiment of the present disclosure.

[0044] A display device includes a display substrate provided in any embodiment of the present disclosure.

[0045] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure are realized and obtained through the structures particularly pointed out in the description, claims, and drawings, details of one or more embodiments of this disclosure being set forth in the following drawings and description.

[0046] To make the above-described objects, features and advantages of this disclosure more apparent and understandable, optional embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1This is a schematic diagram of the structure of a chip growth array provided in one or more embodiments of the present disclosure;

[0049] Figure 2 for Figure 1 A structural cross-sectional view along AA';

[0050] Figure 3 for Figure 1 Another structural cross-sectional view along AA';

[0051] Figure 4 A schematic diagram of another chip growth array provided in one or more embodiments of this disclosure;

[0052] Figure 5 for Figure 4 A structural cross-sectional view along BB';

[0053] Figure 6 A schematic diagram of another chip growth array provided in one or more embodiments of this disclosure;

[0054] Figure 7 This disclosure provides a schematic diagram of the structure of a chip transfer system according to one or more embodiments;

[0055] Figure 8 This is a flowchart illustrating a chip transfer method provided in one or more embodiments of the present disclosure;

[0056] Figures 9a-9g This is a schematic flowchart illustrating a chip growth array fabrication method provided in one or more embodiments of this disclosure;

[0057] Figure 10 This is an internal structural diagram of a computer device according to one or more embodiments of the present disclosure. Detailed Implementation

[0058] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0059] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0060] The terms "first" and "second," etc., in this disclosure and its claims are used to distinguish different objects, not to describe a specific order of objects. For example, "first camera" and "second camera" are used to distinguish different cameras, not to describe a specific order of cameras.

[0061] In this disclosure, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this disclosure should not be construed as preferred or advantageous over other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner. Furthermore, in the description of the embodiments in this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0062] Figure 1 This is a schematic diagram of a chip growth array provided in an embodiment of the present disclosure, as shown below. Figure 1 As shown, the chip growth array includes a substrate 1 and a plurality of chips 2 to be transferred arranged in an array on the substrate 1. For example, a plurality of chips 2 to be transferred are arranged in rows and columns on the substrate 1. Each chip 2 to be transferred includes a first electrode 21 and a second electrode 22. The first electrode 21 and / or the second electrode 22 form a barrier structure, and a transfer adhesive 23 is disposed within the barrier structure.

[0063] like Figure 1 As shown, the first electrode 21 surrounds a retaining wall structure, which may be, for example, a receiving cavity, in which transfer adhesive 23 may be disposed.

[0064] In related technologies, when fabricating the chip to be transferred, the chip is typically placed on a temporary substrate after the substrate is removed. Currently, a temporary substrate with laser adhesive is commonly used. The sapphire substrate and the temporary substrate are bonded and fixed together with the laser adhesive, and the chip to be transferred is embedded in the laser adhesive. When the chip is subsequently transferred using laser, laser adhesive residue remains on the electrodes of the chip. To fully expose the electrodes on the chip, an additional process is usually required to remove the adhesive residue, which increases the complexity of the chip fabrication process.

[0065] The chip growth array provided in this disclosure requires substrate removal and transfer during chip fabrication. Generally, after removing the substrate from the chip growth array, the chip to be transferred is placed on a first transfer substrate. At this time, the transfer adhesive within the barrier structure of the chip to be transferred is configured to bond and fix it to the first transfer substrate. Then, laser transfer technology is used to transfer the chip to be transferred from the first transfer substrate to a second transfer substrate. The first and second electrodes on the chip to be transferred, located on the second transfer substrate, can be directly exposed without the need for adhesive removal, facilitating subsequent electrical connection between the first and second electrodes on the chip to be transferred and the thin-film transistors disposed on the driving substrate.

[0066] Therefore, the technical solution provided in this disclosure forms a barrier structure by surrounding the first electrode and / or the second electrode of the chip to be transferred, and the transfer adhesive is disposed within the barrier structure. In this way, during the fabrication of the chip to be transferred, the transfer adhesive disposed within the barrier structure achieves bonding and fixation between the substrate and the transfer substrate, and no transfer adhesive is disposed on the first and second electrodes of the chip to be transferred. Subsequently, when the chip to be transferred is transferred using laser transfer technology, since the transfer adhesive is disposed within the barrier structure, there is no problem of transfer adhesive residue on the first and second electrodes. Therefore, no additional process is needed to remove adhesive residue, as the electrodes on the chip to be transferred are already exposed. The chip to be transferred, disposed on the second transfer substrate, can be directly peeled off and transferred to the driving substrate. Therefore, this structural design can effectively reduce the complexity of the chip fabrication process.

[0067] In some embodiments, the retaining wall structure has openings at its edges.

[0068] like Figure 1 As shown, for example, an opening 3 is provided at the edge of the retaining wall structure formed by the first electrode 21.

[0069] When fabricating the chip to be transferred, it is necessary to align the side of the chip growth array containing the chip to be transferred with the first transfer substrate. The transfer adhesive within the baffle structure of the chip to be transferred is configured to bond and fix it to the first transfer substrate. The technical solution provided in this disclosure provides an opening at the edge of the baffle structure. This allows excess transfer adhesive within the baffle structure to flow out from the opening when the chip to be transferred is bonded to the first transfer substrate, preventing it from overflowing onto the first and / or second electrodes of the chip.

[0070] In some embodiments, the depth of the opening is less than or equal to the thickness of the retaining wall structure.

[0071] Figure 2 for Figure 1 A structural cross-sectional view along AA', such as Figure 2As shown, the first electrode 21 forms a barrier structure. The x-direction is the direction in which the transfer adhesive flows out at the opening, and the z-direction is perpendicular to the substrate 1. The depth h2 of the opening is less than the thickness h1 of the barrier structure. This design allows excess transfer adhesive within the barrier structure to flow out through the opening while preventing all transfer adhesive from flowing out of the barrier structure.

[0072] In some embodiments, the first electrode may be, for example, a P-type electrode, and the P-type electrode material may be, for example, Ni / Au. The second electrode may be, for example, an N-type electrode, and the N-type electrode material may be, for example, Ti / Al / Ni / Au.

[0073] Figure 3 for Figure 1 Another structural cross-sectional view along AA', such as Figure 3 As shown, the first electrode 21 forms a barrier structure. Along the x-direction, the direction in which the transfer adhesive flows out at the opening, the opening includes a first side and a second side arranged opposite to each other. The first side is the side where the opening faces the transfer adhesive 23, and the second side is the side where the opening faces away from the transfer adhesive 23. In the z-direction, perpendicular to the substrate 1, the depth h3 of the opening on the first side is less than the depth h4 of the opening on the second side. That is, at the opening, the depth of the opening gradually increases along the x-direction, the direction in which the transfer adhesive 23 flows out. This is equivalent to forming a ramp structure at the bottom of the opening, facilitating the smooth flow of the transfer adhesive from the opening.

[0074] Optionally, such as Figure 2 and Figure 3 As shown, a chip-level structure 24 is also disposed on the substrate 1, between the first electrode 21 and the substrate 1. For example, the chip-level structure 24 can be configured as an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, a current diffusion layer, and a passivation layer stacked sequentially. The first electrode is electrically connected to the P-type semiconductor layer through the current diffusion layer, and the second electrode is electrically connected to the N-type semiconductor layer.

[0075] In some embodiments, the light-emitting layer can be a quantum well layer, for example, a multiple quantum well (MQW) layer. For example, the material of the light-emitting layer can be gallium nitride (GaN). This disclosure does not limit the scope of the embodiments.

[0076] In some embodiments, such as Figure 1 As shown, Figure 1The structure has x-direction and y-direction, which are perpendicular to each other and parallel to the substrate 1. The transfer adhesive flows out from the opening, with the x-direction being the direction of adhesive flow at the opening. Along the y-direction, i.e., along the direction perpendicular to the adhesive flow at the opening, the width W of the opening 3 is greater than or equal to 1 micrometer and less than or equal to 5 micrometers. This design allows excess transfer adhesive within the barrier structure to flow out through the opening, while preventing all transfer adhesive within the barrier structure from flowing out completely.

[0077] In some embodiments, the width of the opening is the same as the width of the retaining wall structure, along the direction in which the transfer adhesive flows out at the opening. For example... Figure 1 As shown, along the x-direction in which the transfer adhesive flows out at the opening, the width of the opening 3 is the same as the width of the first electrode 21 of the retaining wall structure in the x-direction.

[0078] In some embodiments, such as Figure 1 As shown, the first electrode 21 forms a retaining wall structure, while the second electrode 22 does not. The second electrode 22 is located within the retaining wall structure. That is, the second electrode 22 is located within the retaining wall structure formed by the first electrode 21. This electrode structure design can improve the diversity of the chip structure design to be transferred and can meet the structural design requirements of various chip electrodes.

[0079] In some embodiments, the barrier structure includes a first barrier structure and a second barrier structure. A first electrode surrounds and forms the first barrier structure, and a second electrode surrounds and forms the second barrier structure. The first electrode and the second electrode are disposed in the same layer. The distance between the surface of the first barrier structure facing away from the substrate and the substrate is equal to the distance between the surface of the second barrier structure facing away from the substrate and the substrate.

[0080] Figure 4 This is a schematic diagram of another chip growth array provided in an embodiment of the present disclosure, such as... Figure 4 As shown, optionally, a plurality of chips 2 to be transferred are arranged in rows and columns on the substrate 1. Each chip 2 to be transferred includes a first electrode 21 and a second electrode 22. The first electrode 21 is surrounded by a first barrier structure, and the second electrode 22 is also surrounded by a second barrier structure. Transfer adhesive 23 is disposed within the first barrier structure formed by the first electrode 21 and within the second barrier structure formed by the second electrode 22. The first barrier structure is located outside the second barrier structure. In the technical solution provided by the embodiments of this disclosure, the first electrode and the second electrode are respectively surrounded by barrier structures, and transfer adhesive is disposed within each of the barrier structures formed by the first electrode and the second electrode.

[0081] Figure 5 for Figure 4 A structural cross-sectional view along BB', such as Figure 5 As shown, the first electrode 21 and the second electrode 22 are disposed in the same layer. The z-direction is perpendicular to the substrate 1. In the z-direction, the distance h5 between the surface of the first barrier structure facing away from the substrate and the substrate is equal to the distance h6 between the surface of the second barrier structure facing away from the substrate and the substrate. This ensures that when the transfer adhesive disposed within the first barrier structure and the transfer adhesive disposed within the second barrier structure are respectively fixedly connected to the first transfer substrate, the distance between the surface of the first barrier structure facing away from the substrate and the substrate is equal to the distance between the surface of the second barrier structure facing away from the substrate and the substrate. This prevents the transfer adhesive from flowing out due to differences in the distances between the first barrier structure, the second barrier structure, and the first transfer substrate. Therefore, when the distance between the surface of the first barrier structure away from the substrate and the substrate is the same as the distance between the surface of the second barrier structure away from the substrate and the substrate, the distance between the first barrier structure, the second barrier structure and the first transfer substrate is the same. In this way, the transfer adhesive provided in the first barrier structure and the second barrier structure can achieve a fixed connection with the first transfer substrate, and the transfer adhesive in the first barrier structure or the second barrier structure can be prevented from flowing out.

[0082] In some embodiments, the first retaining wall structure is located outside the second retaining wall structure.

[0083] like Figure 4 As shown, the first electrode 21 is surrounded by a first barrier structure, and the second electrode 22 is also surrounded by a second barrier structure, with the first barrier structure located outside the second barrier structure. This structural design increases the diversity of the chip structure design to be transferred.

[0084] In some embodiments, the thickness of the first retaining wall structure is equal to the thickness of the second retaining wall structure.

[0085] like Figure 5 As shown, in the z-direction perpendicular to substrate 1, the thickness of the first barrier structure is equal to the thickness of the second barrier structure. This ensures that the distances between the first and second barrier structures and the first transfer substrate are the same, preventing adhesive leakage due to different distances between them. This structural design also increases the versatility of the chip structure design to be transferred.

[0086] In some embodiments, such as Figure 5As shown, a passivation layer 29 is disposed between the first electrode 21 and the second electrode 22 and the substrate 1. The thickness of the passivation layer 29 located inside the barrier structure is less than or equal to the thickness of the passivation layer 29 located outside the barrier structure. This increases the amount of transfer adhesive that can be accommodated within the barrier structure, thereby improving the adhesion between the barrier structure and the first transfer substrate.

[0087] Optionally, such as Figure 5 As shown, the substrate 1 is provided with, for example, a first semiconductor layer 25, a light-emitting layer 26, a second semiconductor layer 27 and a passivation layer 29 stacked sequentially.

[0088] In some embodiments, the first semiconductor layer may be a P-type semiconductor layer and the second semiconductor layer may be an N-type semiconductor layer. Alternatively, the first semiconductor layer may be an N-type semiconductor layer and the second semiconductor layer may be a P-type semiconductor layer.

[0089] For example, both the N-type semiconductor layer and the P-type semiconductor layer can be made of gallium nitride (GaN). Of course, the N-type semiconductor layer and the P-type semiconductor layer can also be made of other materials, and this disclosure does not limit this.

[0090] In some embodiments, the light-emitting layer can be a quantum well layer, for example, a multiple quantum well (MQW) layer.

[0091] For example, the material of the light-emitting layer can be gallium nitride (GaN). However, this disclosure does not limit the scope of the embodiments.

[0092] In some embodiments, Figure 6 This is a schematic diagram of another chip growth array provided in an embodiment of the present disclosure, such as... Figure 6 As shown, the first electrode 21 and the second electrode 22 together form a barrier structure, and transfer adhesive 23 is disposed in the barrier structure. This structural design improves the diversity of the chip structure design to be transferred.

[0093] In some embodiments, the transfer adhesive includes a laser adhesive layer. By providing a laser adhesive layer, it is not only easier to bond and fix the chip to be transferred in the chip growth array to the first transfer substrate, but also, when laser transfer technology is used to transfer the chip, the interface of the laser adhesive layer can absorb the laser and vaporize, causing the chip to be transferred, which is bonded to the first transfer substrate, to detach from the first transfer substrate, thus facilitating the transfer of the chip.

[0094] In some embodiments, the substrate material in the chip growth array can be, for example, a sapphire substrate. The main components of the sapphire substrate are one or more of the following: aluminum oxide (Al2O3), silicon carbide (SiC), single-crystal silicon (Si), gallium nitride (GaN), gallium arsenide (GaAs), aluminum nitride (AlN), and zinc oxide (ZnO). Of course, in addition to the materials listed above, the substrate material in the chip growth array can be other materials such as gallium phosphide (GaP), and this disclosure does not limit this to any particular material.

[0095] In some embodiments, the chip to be transferred is a light-emitting diode (LED) chip. This LED chip may be, for example, a Micro LED chip or a Mini LED chip.

[0096] This disclosure also provides a chip transfer system. Figure 7 This is a schematic diagram of the structure of a chip transfer system provided in an embodiment of the present disclosure, such as... Figure 7 As shown, the chip transfer system includes a first transfer substrate 4, a second transfer substrate 5, and a chip growth array provided in this embodiment. The first transfer substrate 4 is configured to adhere to the transfer adhesive 23 of the chip growth array. The second transfer substrate 5 is configured to carry the chip 2 to be transferred and peeled off from the first transfer substrate 4. It has the same or corresponding beneficial effects, which will not be described further here to avoid repetition.

[0097] This disclosure also provides a chip transfer method for the system provided in this disclosure. Figure 8 This is a flowchart illustrating a chip transfer method provided in an embodiment of the present disclosure, as shown below. Figure 8 As shown, the chip transfer method includes the following steps:

[0098] Step 110: Generate multiple chips to be transferred in an array on the substrate to form a chip growth array.

[0099] The chip to be transferred includes a first electrode and a second electrode. The first electrode and / or the second electrode form a barrier structure, and transfer adhesive is disposed within the barrier structure.

[0100] Step 210: Remove the substrate, peel the chip to be transferred from the chip growth array, and fix the chip to be transferred on the first transfer substrate.

[0101] The first transfer substrate is bonded to the chip growth array via transfer adhesive.

[0102] Step 310: Peel off the chip to be transferred from the first transfer substrate to the second transfer substrate.

[0103] Typically, during chip fabrication, substrate removal and transfer are required. After removing the substrate from the chip growth array, the chip to be transferred is placed on a first transfer substrate. The first electrode and / or second electrode of the chip to be transferred on the first transfer substrate are in contact with the first transfer substrate. Then, the chip to be transferred on the first transfer substrate is peeled off and transferred to a second transfer substrate, so that the first electrode and / or second electrode of the chip to be transferred is facing away from the surface of the second transfer substrate. This exposes the first and second electrodes of the chip to be transferred on the second transfer substrate, facilitating subsequent electrical connection between the chip to be transferred on the second transfer substrate and the thin-film transistor on the driving substrate.

[0104] In step 210, specifically, Figure 7 The arrows in the diagram indicate the order in which the chips to be transferred are peeled off and transferred. For example... Figure 7 As shown, the chip to be transferred 2 on the chip growth array is positioned opposite to the first transfer substrate 4. The transfer adhesive 23 within the chip to be transferred 2 is configured to bond and fix it to the first transfer substrate 4, thus bonding and fixing the chip growth array to the first transfer substrate 4. Then, the substrate 1 in the chip growth array is removed, for example, using laser lift-off technology, to separate the substrate 1 from the chip to be transferred 2, thereby removing the substrate 1. Since the transfer adhesive 23 within the chip to be transferred 2 is configured to bond and fix it to the first transfer substrate 4, after the substrate 1 is removed, the chip to be transferred 2 is fixedly positioned on the first transfer substrate 4. At this time, the first electrode 21 on the chip to be transferred 2, positioned on the first transfer substrate 4, is in contact with the first transfer substrate. Because the first electrode 21 and the second electrode ( Figure 7 (Not shown in the image) Both electrodes are located on the same side of the chip to be transferred 2, so the first electrode 21 and the second electrode are not exposed at this time. Since the chip to be transferred 2 on the chip growth array is ultimately to be transferred to the driving substrate and electrically connected to the thin-film transistor on the driving substrate, it is necessary to expose the first electrode 21 and the second electrode to facilitate electrical connection with the thin-film transistor on the driving substrate.

[0105] In step 310, as Figure 7As shown, for example, laser transfer technology can be used to peel and transfer the chip 2 to be transferred from the first transfer substrate 4 to the second transfer substrate 5, so that the first electrode 21 and / or the second electrode on the chip 2 to be transferred are disposed away from the surface of the second transfer substrate 5. This exposes the first electrode 21 and the second electrode of the chip 2 to be transferred disposed on the second transfer substrate 5, facilitating subsequent electrical connection between the chip 2 to be transferred disposed on the second transfer substrate 5 and the thin-film transistor disposed on the driving substrate. For example, a laser scanning galvanometer can be used for precise scanning to control the position where the laser is to be fired. This allows some of the chips 2 to be transferred on the first transfer substrate 4 to fall to a designated position on the second transfer substrate 5, while some chips 2 do not fall. This enables the chips 2 to be transferred to be arranged on the second transfer substrate 5 in a predetermined row and column arrangement. Figure 7 It can be seen that the first electrode 21 and the second electrode of the chip 2 to be transferred, which are disposed on the second transfer substrate 5, are exposed.

[0106] The technical solution provided in this disclosure involves forming a barrier structure by enclosing the first and / or second electrodes of the chip to be transferred, with the transfer adhesive disposed within the barrier structure. During chip fabrication, the transfer adhesive within the barrier structure enables bonding and fixation between the substrate and the transfer substrate, eliminating the need for additional processes to remove adhesive residue. Since the electrodes are already exposed, the chip can be directly peeled off from the second transfer substrate and transferred to the driving substrate. This structural design effectively reduces the complexity of the chip fabrication process.

[0107] In some embodiments, Figures 9a-9g This is a schematic flowchart of a chip growth array fabrication method provided in an embodiment of this disclosure, as shown below. Figures 9a-9g As shown, step 110: Multiple chips to be transferred are generated in an array on the substrate to form a chip growth array, for example including:

[0108] like Figure 9a As shown, a first semiconductor layer 25, a light-emitting layer 26, and a second semiconductor layer 27 are sequentially grown on substrate 1.

[0109] like Figure 9b As shown, the second semiconductor layer 27, the light-emitting layer 26 and the first semiconductor layer 25 are etched to form the first semiconductor layer connection via 6.

[0110] like Figure 9c As shown, a current diffusion layer 28 is formed on a portion of the second semiconductor layer 27.

[0111] like Figure 9d As shown, the first semiconductor layer 25, the light-emitting layer 26, and the second semiconductor layer 27 are etched to form a plurality of chip dies 7 to be transferred in an array.

[0112] like Figure 9e As shown, a passivation layer 29 is formed on a portion of the current diffusion layer 28 and the second semiconductor layer 27.

[0113] like Figure 9f As shown, a first electrode 21 and a second electrode 22 are formed on the current diffusion layer 28, the first semiconductor layer connecting via 6, and the passivation layer 29; wherein the first electrode 21 and the second electrode 22 surround to form a barrier structure.

[0114] For example, a first electrode 21 is formed on the current diffusion layer 28 and the passivation layer 29, and the first electrode 21 is in contact with the current diffusion layer 28. The current diffusion layer 28 is in contact with the second semiconductor layer 27. A second electrode 22 is formed on the first semiconductor layer connection via 6 and the passivation layer 29, and the second electrode 22 is in contact with the first semiconductor layer 25 through the first semiconductor layer connection via 6.

[0115] like Figure 9g As shown, transfer adhesive 23 is formed within the retaining wall structure.

[0116] In some embodiments, the retaining wall structure may be a retaining wall structure formed by the first electrode or the second electrode.

[0117] The technical solution provided in this disclosure involves forming a barrier structure by enclosing the first and / or second electrodes of the chip to be transferred, with the transfer adhesive disposed within the barrier structure. During chip fabrication, the transfer adhesive within the barrier structure enables bonding and fixation between the substrate and the transfer substrate, eliminating the need for additional processes to remove adhesive residue. Since the electrodes on the chip are already exposed, this structural design effectively reduces the complexity of the chip fabrication process and is simple and easy to implement.

[0118] In some embodiments, the chip transfer method further includes, for example:

[0119] The retaining wall structure is etched to create openings at its edges.

[0120] For example, an opening may be formed at the edge of the retaining wall structure before the transfer adhesive is formed within the retaining wall structure.

[0121] When fabricating the chip to be transferred, it is necessary to align the side of the chip growth array containing the chip to be transferred with the first transfer substrate. The transfer adhesive within the baffle structure of the chip to be transferred is configured to bond and fix it to the first transfer substrate. The technical solution provided in this disclosure, by providing an opening at the edge of the baffle structure, allows excess transfer adhesive within the baffle structure to flow out from the opening when the chip to be transferred is bonded to the first transfer substrate, preventing overflow onto the first and / or second electrodes of the chip. This method is simple and easy to implement.

[0122] In some embodiments, the chip transfer method further includes, for example:

[0123] The passivation layer is etched so that the thickness of the passivation layer inside the retaining wall structure is less than the thickness of the passivation layer outside the retaining wall structure.

[0124] For example, the passivation layer can be etched before the first electrode and the second electrode are formed on the current diffusion layer, the first semiconductor layer connecting via, and the passivation layer, so that the thickness of the passivation layer inside the barrier structure is less than the thickness of the passivation layer outside the barrier structure.

[0125] The technical solution provided in this disclosure involves etching a passivation layer so that the thickness of the passivation layer inside the retaining wall structure is less than the thickness of the passivation layer outside the retaining wall structure. This increases the amount of transfer adhesive that can be accommodated within the retaining wall structure, thereby improving the adhesion between the retaining wall structure and the first transfer substrate.

[0126] It should be understood that, in combination only Figure 8 The illustrative description illustrates the execution order of the steps in the chip transfer method provided in this disclosure, but does not constitute a limitation on the chip transfer method provided in this disclosure. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Furthermore, Figure 8 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0127] This disclosure also provides a computer device, including: a memory and one or more processors, wherein the memory stores computer-readable instructions; when the computer-readable instructions are executed by one or more processors, the one or more processors cause the one or more processors to perform the steps of the chip transfer method provided in this disclosure.

[0128] In some embodiments, the computer device may be a terminal device. Exemplarily, the computer device may be, for example, a chip manufacturing apparatus. Its internal structure diagram may be as follows: Figure 10 As shown. Figure 10 This is an internal structural diagram of a computer device according to one or more embodiments of the present disclosure. The computer device includes a processor, memory, communication interface, database, display screen, and input device connected via a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer-readable instructions. The internal memory provides an environment for the operation of the operating system and computer-readable instructions in the non-volatile storage medium. The communication interface of the computer device is configured to communicate with an external terminal via wired or wireless means; wireless communication can be achieved through Wi-Fi, carrier networks, near-field communication (NFC), or other technologies. When the computer-readable instructions are executed by the processor, they implement the chip transfer method provided in the above embodiments. The display screen of the computer device can be a liquid crystal display screen or an e-ink display screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, a trackball, or a touchpad provided on the casing of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0129] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present disclosure and does not constitute a limitation on the computer device to which the present disclosure is applied. A specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0130] The computer device provided in this embodiment can implement the chip transfer method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described again here.

[0131] This disclosure also provides one or more non-volatile computer-readable storage media storing computer-readable instructions, which, when executed by one or more processors, cause the one or more processors to perform the steps of the chip transfer method provided in this disclosure.

[0132] The computer-readable instructions stored on the computer-readable storage medium provided in this embodiment can implement the chip transfer method provided in the above method embodiment. The implementation principle and technical effect are similar, and will not be described again here.

[0133] Those skilled in the art will understand that implementing all or part of the processes in the above method embodiments can be accomplished by instructing related hardware through computer-readable instructions. These computer-readable instructions can be stored in a non-volatile computer-readable storage medium. When executed, these computer-readable instructions can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this disclosure can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static random access memory (SRAM) and dynamic random access memory (DRAM), etc.

[0134] This disclosure also provides a display substrate, characterized in that it includes a plurality of chips to be transferred using the chip transfer system described in this disclosure. It has the same or corresponding beneficial effects, and to avoid repetition, will not be described again here.

[0135] Optionally, the display substrate is the driving substrate, and multiple thin-film transistors are disposed on the display substrate. The chip to be transferred disposed on the second transfer substrate needs to be stripped and transferred to the display substrate, and the first electrode and the second electrode on the chip to be transferred are electrically connected to the thin-film transistors at the corresponding positions, respectively.

[0136] This disclosure also provides a display device, including the display substrate described in this disclosure. It has the same or corresponding beneficial effects, and to avoid repetition, it will not be described again here.

[0137] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] The above embodiments merely illustrate several implementation methods of this disclosure, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this patent should be determined by the appended claims.

[0139] Industrial applicability

[0140] This disclosure provides a chip growth array, system, method, apparatus, medium, substrate, and device. A barrier structure is formed by surrounding the first and / or second electrodes of the chip to be transferred, and transfer adhesive is disposed within the barrier structure. During chip fabrication, the transfer adhesive within the barrier structure achieves bonding and fixation between the substrate and the transfer substrate, eliminating the need for additional adhesive removal processes. Since the electrodes on the chip are already exposed, this structural design effectively reduces the complexity of the chip fabrication process and has strong industrial applicability.

Claims

1. A chip growth array, characterized in that, The chip growth array comprises: a substrate and a plurality of chips to be transferred arranged in an array on the substrate; the chip to be transferred comprises a first electrode and a second electrode; the first electrode and / or the second electrode surrounds to form a dam structure, and a transfer adhesive is arranged in the dam structure, the substrate and the transfer substrate are bonded and fixed through the transfer adhesive arranged in the dam structure, and the first electrode and the second electrode of the chip to be transferred are not arranged with the transfer adhesive; an opening is arranged at the edge of the dam structure; the depth of the opening is less than the thickness of the dam structure; along the direction perpendicular to the flow direction of the transfer adhesive at the opening, the width of the opening is greater than or equal to 1 micrometer and less than or equal to 5 micrometers; along the flow direction of the transfer adhesive at the opening, the width of the opening is equal to the width of the dam structure; the opening comprises a first side and a second side arranged oppositely; the first side is the side of the opening facing the transfer adhesive, and the second side is the side of the opening away from the transfer adhesive; the depth of the opening at the first side is less than the depth of the opening at the second side; the dam structure comprises a first dam structure and a second dam structure; the first electrode surrounds to form the first dam structure, and the second electrode surrounds to form the second dam structure; the first electrode and the second electrode are arranged in the same layer; the distance between the surface of the first dam structure away from the substrate and the substrate is equal to the distance between the surface of the second dam structure away from the substrate and the substrate; the first dam structure is located outside the second dam structure; in the direction perpendicular to the substrate, the thickness of the first dam structure is equal to the thickness of the second dam structure; a passivation layer is arranged between the first electrode, the second electrode and the substrate; the thickness of the passivation layer in the dam structure is less than or equal to the thickness of the passivation layer outside the dam structure; the transfer adhesive comprises a laser adhesive layer.

2. A chip transfer system characterized by comprising: The chip growth array comprises: a first transfer substrate, a second transfer substrate and the chip growth array as claimed in claim 1; the first transfer substrate is configured to be pasted with the transfer adhesive of the chip growth array, and the transfer adhesive is arranged only in the dam structure and does not contact the first electrode and the second electrode of the chip to be transferred; 3. A chip transfer method for the system of claim 2, characterized by, the second transfer substrate is configured to carry the chip to be transferred peeled off from the first transfer substrate. The chip growth array comprises: generating a plurality of chips to be transferred arranged in an array on the substrate to form the chip growth array; wherein the chip to be transferred comprises a first electrode and a second electrode; the first electrode and / or the second electrode surrounds to form a dam structure, and a transfer adhesive is arranged in the dam structure; removing the substrate, peeling off and transferring the chip to be transferred from the chip growth array, and fixing the chip to be transferred on the first transfer substrate; wherein the first transfer substrate is pasted with the chip growth array through the transfer adhesive; peeling off and transferring the chip to be transferred arranged on the first transfer substrate to the second transfer substrate.

4. The chip transfer method according to claim 3, wherein The generating the plurality of to-be-transferred chips in an array arrangement on the substrate to form the chip growth array comprises: sequentially growing a first semiconductor layer, a light-emitting layer, and a second semiconductor layer on the substrate; etching the second semiconductor layer, the light-emitting layer, and the first semiconductor layer to form a first semiconductor layer connecting through hole; forming a current diffusion layer on part of the second semiconductor layer; etching the first semiconductor layer, the light-emitting layer, and the second semiconductor layer to form a plurality of to-be-transferred chip grains in an array arrangement; forming a passivation layer on part of the current diffusion layer and the second semiconductor layer; forming the first electrode and the second electrode on the current diffusion layer, the first semiconductor layer connecting through hole, and the passivation layer; wherein the first electrode and / or the second electrode forms the barrier wall structure; forming the transfer adhesive in the barrier wall structure.

5. The chip transfer method according to claim 4, wherein The method further comprises: etching the barrier wall structure to form an opening at an edge of the barrier wall structure.

6. The chip transfer method according to claim 4, wherein The method further comprises: etching the passivation layer so that a thickness of the passivation layer located in the barrier wall structure is less than a thickness of the passivation layer located outside the barrier wall structure.

7. A computer device comprising: a memory and one or more processors, the memory having computer readable instructions stored therein; the computer readable instructions, when executed by the one or more processors, cause the one or more processors to perform the steps of the chip transfer method of any one of claims 3-6.

8. One or more non-transitory computer readable storage media having computer readable instructions stored therein, the computer readable instructions, when executed by one or more processors, cause the one or more processors to perform the steps of the chip transfer method of any one of claims 3-6.

9. A display substrate, comprising: a plurality of to-be-transferred chips transferred by the chip transfer system of claim 2.

10. A display device, characterized by comprising: a display substrate as claimed in claim 9. a display substrate as claimed in claim 9.

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