Array substrate and display device

Abstract

An array substrate and a display device, the array substrate comprising a display area and a peripheral area surrounding the display area, the array substrate further comprising a gate material layer (300) and a source-drain material layer (400) sequentially stacked on a base substrate (100), the array substrate further comprising a drive signal line, the drive signal line comprising a first sub-signal line and a second sub-signal line, the first sub-signal line being arranged in the gate material layer (300) and extending from the peripheral area to the display area, the second sub-signal line being arranged in the source-drain material layer (400) and at least located in the display area, the first sub-signal line and the second sub-signal line being electrically connected through a via.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] OLED (Organic Light Emitting Diode) display technology is recognized by the industry as the third generation display technology for its advantages such as light weight, self-luminescence, wide viewing angle, fast response speed, low brightness and low power consumption. It has been widely used in the field of high-performance displays.

[0003] In AMOLED display products, the output line of the GOA circuit is overloaded due to the long signal line. On the one hand, the larger the load, the greater the power consumption of the display panel; on the other hand, the larger the load, the greater the load requires the GOA circuit to have a stronger load capacity, so the output tube size needs to be longer, which is not conducive to the realization of a narrow frame, thus placing higher requirements on the signal line design. Summary of the invention

[0004] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide an array substrate and a display device.

[0005] According to one aspect of the present disclosure, there is provided an array substrate having a display area and a peripheral area surrounding the display area, the array substrate further comprising:

[0006] substrate substrate;

[0007] A gate material layer is provided on one side of the base substrate;

[0008] A source-drain electrode material layer, disposed on a side of the gate material layer away from the substrate;

[0009] The array substrate also includes a driving signal line, which includes a first sub-signal line and a second sub-signal line. The first sub-signal line is arranged in the gate material layer and extends from the peripheral area to the display area. The second sub-signal line is arranged in the source and drain material layer and is at least located in the display area. The first sub-signal line and the second sub-signal line are electrically connected through a via.

[0010] In an exemplary embodiment of the present disclosure, the source-drain material layer includes:

[0011] A first source-drain material sublayer is provided on a side of the gate material layer away from the substrate;

[0012] A second source-drain material sublayer, disposed on a side of the second source-drain material sublayer away from the first source-drain material sublayer;

[0013] Wherein, the second sub-signal line is arranged in the first source-drain material sub-layer or the second source-drain material sub-layer.

[0014] In an exemplary embodiment of the present disclosure, the driving signal line includes a gate driving signal line, the first sub-signal line includes a first sub-gate driving line, the second sub-signal line includes a second sub-gate driving line, the first sub-gate driving line is arranged in the gate material layer and extends from the peripheral area to the display area, the second sub-gate driving line is arranged in the first source and drain material sub-layer or the second source and drain material sub-layer and is at least located in the display area, and the first sub-gate driving line and the second sub-gate driving line are electrically connected through a via.

[0015] In an exemplary embodiment of the present disclosure, the driving signal line includes an enable signal line, the first sub-signal line includes a first sub-enable signal line, the second sub-signal line includes a second sub-enable signal line, the first sub-enable signal line is arranged in the gate material layer and extends from the peripheral area to the display area, the second sub-enable signal line is arranged in the first source and drain material sub-layer or the second source and drain material sub-layer and is at least located in the display area, and the first sub-enable signal line and the second sub-enable signal line are electrically connected through a via.

[0016] In an exemplary embodiment of the present disclosure, the driving signal line includes a reset signal line, the first sub-signal line includes a first sub-reset signal line, the second sub-signal line includes a second sub-reset signal line, the first sub-reset signal line is arranged in the gate material layer and extends from the peripheral area to the display area, the second sub-reset signal line is arranged in the first source and drain material sub-layer or the second source and drain material sub-layer and is at least located in the display area, and the first sub-reset signal line and the second sub-reset signal line are electrically connected through a via.

[0017] In an exemplary embodiment of the present disclosure, the first sub-signal line and the second sub-signal line extend in the same direction, or extend in different directions.

[0018] In an exemplary embodiment of the present disclosure, the array substrate also includes a power line, and the power line includes a first sub-power line and a second sub-power line, the first sub-power line is arranged in the first source and drain material sub-layer, and the second sub-power line is arranged in the second source and drain material sub-layer, and the first sub-power line and the second sub-power line are electrically connected through a via.

[0019] In an exemplary embodiment of the present disclosure, the second sub-signal line and the second sub-power line are both located in the second source-drain material sub-layer, and the second sub-signal line and the second sub-power line extend in the same direction and are arranged in another direction.

[0020] In an exemplary embodiment of the present disclosure, the first sub-signal line extends along a first direction, the first sub-power line extends along a second direction, the second sub-signal line and the second sub-power line both extend along the first direction and are arranged along the second direction, and the first direction and the second direction intersect.

[0021] In an exemplary embodiment of the present disclosure, projections of the first sub-signal line and the second sub-signal line on the base substrate overlap.

[0022] In an exemplary embodiment of the present disclosure, the second sub-signal line is also located in the peripheral area, and the first sub-signal line and the second sub-signal line are electrically connected through a via in the peripheral area.

[0023] In an exemplary embodiment of the present disclosure, a line width of the second sub-signal line is greater than a line width of the first sub-signal line.

[0024] In an exemplary embodiment of the present disclosure, a line width of the second sub-signal line is greater than or equal to 5 μm.

[0025] In an exemplary embodiment of the present disclosure, the array substrate includes a GOA driving circuit, and the first sub-signal line is connected to an output end of the GOA driving circuit.

[0026] In an exemplary embodiment of the present disclosure, the gate material layer includes a first gate material layer and a second gate material layer stacked together and a gate insulating layer located between the first gate material layer and the second gate material layer, and the first sub-signal line is located in the first gate material layer or the second gate material layer.

[0027] According to another aspect of the present disclosure, a display device is provided, comprising the array substrate described above.

[0028] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0030] Figure 1 It is a schematic diagram of a 7T1C pixel circuit structure;

[0031] Figure 2 for Figure 1A timing diagram of each node in a driving method of a pixel driving circuit;

[0032] Figure 3 is a structural layout of the array substrate in this embodiment;

[0033] Figure 4 for Figure 3 Schematic diagram of the structure of the active layer;

[0034] Figure 5 for Figure 3 A schematic structural diagram of the first gate material layer;

[0035] Figure 6 for Figure 4 and Figure 5 Schematic diagram of the stacked structure;

[0036] Figure 7 for Figure 3 A schematic structural diagram of the second gate material layer;

[0037] Figure 8 for Figure 6 and Figure 7 Schematic diagram of the stacked structure;

[0038] Fig. 9 for Figure 3 A schematic structural diagram of the first source and drain material sublayer;

[0039] Fig.10 for Figure 8 and Fig. 9 Schematic diagram of the stacked structure;

[0040] Fig.11 for Figure 3 A schematic structural diagram of the second source and drain material sublayer;

[0041] Fig.12 for Fig.10 and Fig.11 Schematic diagram of the stacked structure;

[0042] Fig.13 for Figure 3 and Fig.12 Schematic diagram of the cross section along the AA direction;

[0043] Fig.14 is a circuit diagram of a GOA driving circuit;

[0044] Fig.15 for Fig.14 A structural layout of the GOA driving circuit shown;

[0045] Fig.16 for Fig.15 Schematic diagram of the cross section along the BB direction.

[0046] Description of reference numerals:

[0047] 100, substrate; 200, active layer; 201, gate insulating layer; 300, gate material layer; 310, first gate material layer; 320, second gate material layer; 301, interlayer dielectric layer; 400, source and drain material layer; 410, first source and drain material sublayer; 401, insulating layer; 402, planar layer; 420, second source and drain material sublayer; 51, first sub-gate drive line; 52, second sub-gate drive line; 61, first sub-enable signal line; 62, second sub-enable signal line; 71, first sub-reset signal line; 72, second sub-reset signal line; 80, connecting portion; 81, first sub-power line; 82, second sub-power line; DETAILED DESCRIPTION

[0048] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0049] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0050] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0051] The embodiment of the present disclosure provides an array substrate having a display area and a peripheral area surrounding the display area, the array substrate further comprising a base substrate 100 and a gate material layer 300 and a source-drain material layer 400 sequentially stacked on the base substrate 100. The array substrate further comprises a driving signal line, the driving signal line comprising a first sub-signal line and a second sub-signal line, the first sub-signal line being arranged in the gate material layer 300 and extending from the peripheral area to the display area, the second sub-signal line being arranged in the source-drain material layer 400 and at least located in the display area, and the first sub-signal line and the second sub-signal line being electrically connected through a via.

[0052] The present disclosure divides the driving signal line into two layers, one layer is located at the gate material layer 300, and the other side is located at the source and drain material layer 400. The two layers are connected in parallel, which can reduce the load resistance on the driving signal line, thereby reducing the output power consumption of the driving circuit and reducing the size of the driving circuit. On the other hand, the resistivity of the gate material layer 300 is relatively high, about 0.52Ω / m, and the resistivity of the source and drain material layer 400 is relatively low, about 0.045Ω / m. A signal line with a relatively low resistivity is connected in parallel with a signal line with a relatively high resistivity, which further reduces the overall load resistance of the signal line.

[0053] Among them, the gate material layer refers to the material layer of the gate metal of the driving circuit, which may include a gate pattern, a scan line pattern, etc.; similarly, the source and drain material layer refers to the film layer of the source and drain electrode material of the transistor in the driving circuit, which may include source and drain electrodes or power signal line patterns, or other transfer patterns, etc.

[0054] refer to Figure 1, is a schematic diagram of a 7T1C pixel circuit structure, the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the first electrode of the first transistor T1 is connected to the node N, the second electrode is connected to the initialization signal line Vinit, and the gate is connected to the reset signal line Re; the first electrode of the second transistor T2 is connected to the first electrode of the driving transistor T3, the second electrode is connected to the node N; the gate is connected to the gate driving signal line Gate; the gate of the driving transistor T3 is connected to the node N; the first electrode of the fourth transistor T4 is connected to the data signal line Data, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the gate driving signal line Gate; the first electrode of the fifth transistor T5 is connected to the first power signal line VDD, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the enable signal line EM; the first electrode of the sixth transistor T6 is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal line EM; the first electrode of the seventh transistor T7 is connected to the initialization signal line Vinit, and the second electrode is connected to the second electrode of the sixth transistor T6. The pixel driving circuit can be connected to a light emitting unit OLED to drive the light emitting unit OLED to emit light, and the light emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and the second power line VSS. Among them, the transistors T1-T7 can all be P-type transistors.

[0055] like Figure 2 As shown, Figure 1 A timing diagram of each node in a driving method of a pixel driving circuit. Wherein, Gate represents the timing of the gate driving signal terminal Gate, Re represents the timing of the reset signal terminal Re, EM represents the timing of the enable signal terminal EM, and Data represents the timing of the data signal terminal Data. The driving method of the pixel driving circuit may include a reset stage t1, a compensation stage t2, and a light-emitting stage t3. In the reset stage t1: the reset signal terminal Re outputs a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the initialization signal terminal Vinit inputs an initialization signal to the node N and the second electrode of the sixth transistor T6. In the compensation stage t2: the gate driving signal terminal Gate outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Data outputs a driving signal to write a voltage to the node N. Light-emitting stage t3: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage stored in the capacitor C.

[0056] like Figure 3 As shown, Figure 3 is an exemplary structural layout of the array substrate in this embodiment. Figure 3 The array substrate shown can be formed Figure 1The pixel driving circuit shown in FIG. Figures 4 to 12 The schematic diagrams of each film layer and the stacking diagram of the array substrate are shown in sequence. Referring to the above drawings, the array substrate includes a base substrate 100, an active layer 200 located on one side of the base substrate 100, a first gate material layer 310 located on the side of the active layer 200 away from the base substrate 100, a second gate material layer 320 located on the side of the first gate material layer 310 away from the base substrate 100, a first source-drain material sublayer 410 located on the side of the second gate material layer 320 away from the base substrate 100, and a second source-drain material sublayer 420 located on the side of the first source-drain material sublayer 410 away from the base substrate 100. A gate insulating layer 201 is arranged between the active layer 200 and the first gate material layer 310 and between the first gate material layer 310 and the second gate material layer 320 , a first interlayer dielectric layer 301 is arranged between the second gate material layer 320 and the first source and drain material sublayer 410 , and an insulating layer 401 is arranged between the first source and drain material sublayer 410 and the second source and drain material sublayer 420 .

[0057] The base substrate 100 may be formed of an insulating material. For example, the base substrate 100 may include a first polyimide (PI) layer, a first silicon oxide (SiO) layer, an amorphous silicon layer, a second polyimide (PI) layer, and a second silicon oxide layer arranged in sequence. The original material for forming the active layer may be a semiconductor. During the manufacturing process of the array substrate, the active layer may be conductorized by using the first conductive layer as a mask, thereby converting the semiconductor structure outside the transistor channel region into a conductive structure.

[0058] The first source-drain material sublayer 410 and the second source-drain material sublayer 420 can be formed by at least one metal layer. For example, the first source-drain material sublayer 410 and the second source-drain material sublayer 420 can be any one or more metal materials such as magnesium, silver, copper, aluminum, molybdenum, etc., or any two or more alloy materials of the above. It can be a single-layer structure or a stacked structure. For example, the first source-drain material sublayer 410 and the second source-drain material sublayer 420 can be formed by stacking a first titanium layer, an aluminum layer, and a second titanium layer in sequence. The gate insulating layer provided between the first gate material layer 310 and the active layer 200 and between the first gate material layer 310 and the second gate material layer 320 can be a silicon oxide layer, and the interlayer dielectric layer between the second gate material layer 320 and the first source-drain material sublayer 410 and the insulating layer between the first source-drain material sublayer 410 and the second source-drain material sublayer 420 can be a silicon nitride layer. Similarly, the gate material layer may also be a single metal material or an alloy material, and may be a single layer or a stacked layer structure, which will not be described in detail here.

[0059] In one embodiment, the array substrate further includes a gate drive signal line, which can be used to provide Figure 1 The gate drive signal Gate in the reference circuit is used to provide a gate drive signal to the driving transistor. Figure 5 , Figure 6 , Fig.11 and Fig.12 , the gate drive signal line includes a first sub-gate drive line 51 and a second sub-gate drive line 52. The first sub-gate drive line 51 is arranged in the first gate material layer 310 and extends from the peripheral area to the display area. One end located in the peripheral area is connected to the drive chip or the GOA drive circuit to receive the drive signal. The second sub-gate drive line 52 is arranged in the first source and drain material sublayer 410 or the second source and drain material sublayer 420 and is at least located in the display area. Since the first sub-gate drive line 51 and the second sub-gate drive line 52 are located in different layers, the two are electrically connected through vias. Connecting the two layers of gate drive lines in parallel can reduce the load resistance on the gate drive signal line, thereby reducing the output power consumption of the drive circuit. The first sub-gate drive line 51 and the second sub-gate drive line 52 can extend in the same direction or in different directions.

[0060] In this embodiment, the array substrate further includes a power line, which can be used to provide Figure 1 In one embodiment, the power supply terminal signal VDD in the capacitor C is used to provide a power supply signal to the first electrode of the capacitor C. Figure 9-12 The power line includes a first sub-power line 81 and a second sub-power line 82. The first sub-power line 81 is arranged in the first source-drain material sub-layer 410, and the second sub-power line 82 is arranged in the second source-drain material sub-layer 420. Since the first sub-power line 81 and the second sub-power line 82 are located in different layers, they are electrically connected through vias. The power lines are arranged in two source-drain material layers and connected in parallel, which can reduce the IR Drop of the power lines. Figure 3 and Fig.12 As shown, in this embodiment, the first sub-power line 81 extends in the longitudinal direction, and the second sub-power line 82 extends in the transverse direction. The two intersect in a grid shape, which can increase the transmission path of the power signal and minimize the IR Drop of the power line. Figure 3 and Fig.12 The AA section where the first sub-power line 81 and the second sub-power line 82 are electrically connected can be referred to. Fig.13, the first sub-power line 81 and the second sub-power line 82 can be electrically connected through a via hole penetrating the insulating layer 401. When other film layers, such as the flat layer 402, are included between the first source-drain material sub-layer 410 and the second source-drain material sub-layer 420, the via hole also needs to penetrate other film layers. In addition, in this embodiment, the projection of the second sub-power line 82 extending laterally on the substrate overlaps with the projection of the initialization signal line located on the second gate material layer 320 on the substrate, which can reduce the space occupied by the wiring and further improve the panel transmittance. Since both the power signal and the initialization signal are constant signals, the overlap of the projections has little effect on the signal stability.

[0061] When the second sub-gate drive line 52 and the second sub-power line 82 are both located in the second source-drain material sub-layer 420, it should be ensured that the two do not intersect, that is, the two need to extend in the same direction and be arranged in another direction. As shown in the figure, the second sub-gate drive line 52 also extends in the horizontal direction and is arranged with the second sub-power line 82 in the longitudinal direction. In other embodiments, when the second sub-power line 82 extends in other directions, the second sub-gate drive line 52 also needs to maintain the same extension direction as the second sub-power line 82.

[0062] In some other embodiments, when the second source-drain material sublayer 420 is not provided with the second sub-power line 82, the extension direction of the second sub-gate driving line 52 is not limited by the second sub-power line 82, for example, the first sub-gate driving line 51 extends along the first direction, and the second sub-gate driving line 52 extends along the second direction. Alternatively, the first sub-gate driving line 51 extends along the first direction, and the second sub-gate driving line 52 crosses horizontally and vertically to form a grid. Alternatively, in other embodiments, when the second sub-gate driving line 52 is located in the first source-drain material sublayer 410, the second sub-gate driving line 52 and the first sub-power line 81 do not intersect.

[0063] Furthermore, if Figure 5 , Figure 6 , Fig.11 and Fig.12 , as shown, the first sub-gate driving line 51 and the second sub-gate driving line 52 both extend in the horizontal direction, and their projections on the base substrate 100 are substantially overlapped, thereby preventing the second sub-gate driving line 52 from overlapping with other signal lines and increasing parasitic capacitance. In addition, the projections of the first sub-gate driving line 51 and the second sub-gate driving line 52 on the base substrate 100 do not completely overlap, as shown in the M area in the figure, which is a position where the projection of the first sub-gate driving line 51 is not covered by the projection of the second sub-gate driving line 52. This position is exposed to reduce the impact on the gate potential of the driving transistor.

[0064] In one embodiment, the array substrate further includes an enable signal line, which can be used to provide Figure 1The enable signal EM in . Figure 5 , Figure 6 , Fig.11 and Fig.12 , the enable signal line includes a first sub-enable signal line 61 and a second sub-enable signal line 62. The first sub-enable signal line 61 is arranged in the first gate material layer 310 and extends from the peripheral area to the display area. One end located in the peripheral area is connected to the driving chip or the GOA driving circuit to receive the driving signal. The second sub-enable signal line 62 is arranged in the first source and drain material sublayer 410 or the second source and drain material sublayer 420 and is at least located in the display area. Since the first sub-enable signal line 61 and the second sub-enable signal line 62 are located in different layers, the two are electrically connected through vias. Connecting the two layers of enable signal lines in parallel can reduce the load resistance on the enable signal line, thereby reducing the output power consumption of the drive circuit. The first sub-enable signal line 61 and the second sub-enable signal line 62 can extend in the same direction or in different directions.

[0065] When the second sub-enable signal line 62 and the second sub-power line 82 are both located in the second source-drain material sub-layer 420, it should be ensured that the two do not intersect, that is, the two need to extend in the same direction and be arranged in another direction. As shown in the figure, the second sub-enable signal line 62 also extends in the horizontal direction and is arranged with the second sub-power line 82 in the longitudinal direction. In other embodiments, when the second sub-power line 82 extends in other directions, the second sub-enable signal line 62 also needs to maintain the same extension direction as the second sub-power line 82.

[0066] In some other embodiments, when the second source-drain material sublayer 420 is not provided with the second sub-power supply line 82, the extension direction of the second sub-enable signal line 62 is not limited by the second sub-power supply line 82, for example, the first sub-enable signal line 61 extends along the first direction, and the second sub-enable signal line 62 extends along the second direction. Alternatively, the first sub-enable signal line 61 extends along the first direction, and the second sub-enable signal line 62 crosses horizontally and vertically to form a grid. Alternatively, in other embodiments, when the second sub-enable signal line 62 is located in the first source-drain material sublayer 410, it should be ensured that the second sub-enable signal line 62 and the first sub-power supply line 81 do not intersect.

[0067] Further, in some embodiments, the first sub-enabling signal line 61 and the second sub-enabling signal line 62 both extend in the lateral direction, and their projections on the base substrate 100 overlap, thereby preventing the second sub-enabling signal line 62 from overlapping with other signal lines and increasing parasitic capacitance. In the embodiment shown in the figure, the projections of the first sub-enabling signal line 61 and the second sub-enabling signal line 62 on the base substrate 100 do not completely overlap, in order to prevent the second sub-enabling signal line 62 from being too close to other conductive structures of the layer. It can be understood that, on the basis of ensuring sufficient layout space, the overlapping of the projections of the two is a more optimized design.

[0068] At the same time, the array substrate of this embodiment includes both enable signal lines and gate drive signal lines. Therefore, the first sub-enable signal line 61 and the first sub-gate drive line 51 located in the same layer should not intersect, that is, extend in the same direction. For example, as shown in the figure, the first sub-enable signal line 61 and the first sub-gate drive line 51 are both located in the first gate material layer 310, both extend in the horizontal direction, and the two are arranged at intervals in the longitudinal direction. Correspondingly, when the second sub-enable signal line 62 and the second sub-gate drive line 52 are also located in the same layer, the two should also not intersect, that is, extend in the same direction. For example, as shown in the figure, the second sub-enable signal line 62 and the second sub-gate drive line 52 are both located in the second source and drain material sublayer 420, both extend in the horizontal direction, and the two are arranged at intervals in the longitudinal direction.

[0069] In one embodiment, the array substrate further includes a reset signal line, which can be used to provide Figure 1 The reset signal Reset in the reference Figure 5 , Figure 6 , Fig.11 and Fig.12 , the reset signal line includes a first sub-reset signal line 71 and a second sub-reset signal line 72. The first sub-reset signal line 71 is arranged in the first gate material layer 310 and extends from the peripheral area to the display area. One end located in the peripheral area is connected to the driving chip or the GOA driving circuit to receive the driving signal. The second sub-reset signal line 72 is arranged in the first source and drain material sub-layer 410 or the second source and drain material sub-layer 420 and is at least located in the display area. Since the first sub-reset signal line 71 and the second sub-reset signal line 72 are located in different layers, the two are electrically connected through a via. Connecting the two layers of reset signal lines in parallel can reduce the load resistance on the reset signal line, thereby reducing the output power consumption of the driving circuit. The first sub-reset signal line 71 and the second sub-reset signal line 72 can extend in the same direction or in different directions.

[0070] When the second sub-reset signal line 72 and the second sub-power line 82 are both located in the second source-drain material sub-layer 420, it should be ensured that the two do not intersect, that is, the two need to extend in the same direction and be arranged in another direction. As shown in the figure, the second sub-reset signal line 72 also extends in the horizontal direction and is arranged with the second sub-power line 82 in the longitudinal direction. In other embodiments, when the second sub-power line 82 extends in other directions, the second sub-reset signal line 72 also needs to maintain the same extension direction as the second sub-power line 82.

[0071] In some other embodiments, when the second source-drain material sub-layer 420 is not provided with the second sub-power supply line 82, the extension direction of the second sub-reset signal line 72 is not limited by the second sub-power supply line 82, for example, the first sub-reset signal line 71 extends along the first direction, and the second sub-reset signal line 72 extends along the second direction. Alternatively, the first sub-reset signal line 71 extends along the first direction, and the second sub-reset signal line 72 crosses horizontally and vertically to form a grid. Alternatively, in other embodiments, when the second sub-reset signal line 72 is located in the first source-drain material sub-layer 410, it should be ensured that the second sub-reset signal line 72 and the first sub-power supply line 81 do not intersect.

[0072] Furthermore, the first sub-reset signal line 71 and the second sub-reset signal line 72 both extend in the lateral direction, and their projections on the base substrate 100 overlap, thereby preventing the second sub-reset signal line 72 from overlapping with other signal lines to increase parasitic capacitance.

[0073] At the same time, the array substrate of this embodiment includes an enable signal line, a gate drive signal line and a reset signal line at the same time. Therefore, the first sub-enable signal line 61, the first sub-gate drive line 51, and the first sub-reset signal line 71 located in the same layer should not intersect, that is, extend in the same direction. As shown in the figure, the first sub-enable signal line 61, the first sub-gate drive line 51, and the first sub-reset signal line 71 are all located in the first gate material layer 310, all extend in the horizontal direction, and the three are arranged at intervals in the longitudinal direction. Correspondingly, when the second sub-enable signal line 62, the second sub-gate drive line 52, and the second sub-reset signal line 72 are also located in the same layer, the three should also not intersect, that is, extend in the same direction. As shown in the figure, the second sub-enable signal line 62, the second sub-gate drive line 52, and the second sub-reset signal line 72 are all located in the second source and drain material sublayer 420, all extend in the horizontal direction, and the two are arranged at intervals in the longitudinal direction.

[0074] refer to Fig.15The array substrate may further include a flat layer 402, which is disposed between the first source-drain material sublayer 410 and the second source-drain material sublayer 420, and is located on the side of the insulating layer 401 away from the first source-drain material sublayer 410, thereby increasing the spacing between the first source-drain material sublayer 410 and the second source-drain material sublayer 420, and helping to reduce the signal crosstalk between the criss-crossed data lines and power lines. Since the flat layer is usually made of organic material, its thickness is greater than that of inorganic layers such as the interlayer dielectric layer 301 and the insulating layer 401, and can further alleviate the influence of signal crosstalk.

[0075] In the present disclosure, since the drive signal line is arranged in two layers, the wiring space becomes larger, and the load resistance can be further reduced by increasing the line width of the signal line. Specifically, the first sub-signal line is arranged in the first gate material layer 310, and the second sub-drive signal line is located in the first source and drain material sub-layer 410 or the second source and drain material sub-layer 420. Since the resistivity of the first source and drain material sub-layer 410 or the second source and drain material sub-layer 420 is relatively low relative to the first gate material layer 310, the line width of the second sub-signal line can be increased, for example, the line width of the second sub-signal line can be made greater than the line width of the first sub-signal line, so as to further reduce the overall load resistance of the drive signal line. In a specific embodiment, the line width of the first sub-signal line is set to about 3μm, and the line width of the second sub-signal line is set to be greater than or equal to 5μm, thereby greatly reducing the load resistance of the GOA circuit.

[0076] It should be noted that, in this embodiment, the gate material layer includes a first gate material layer 310 and a second gate material layer 320, the first sub-enable signal line 61, the first sub-gate drive signal line 51 and the first sub-reset signal line 71 are all located in the first gate material layer 310, and the first gate material layer 310 is also provided with an electrode plate 91 of a capacitor (refer to Figure 6 ), the second gate material layer 320 is used to set another electrode plate 92 of the capacitor and other conductive connecting parts (reference Figure 7 ). In other embodiments, the first sub-enable signal line 61, the first sub-gate drive signal line 51 and the first sub-reset signal line 71 may also be arranged in the second gate material layer 320. Alternatively, the three signal lines may be distributed in two gate material layers. Of course, the gate material layer may be arranged in only one layer, and the three signal lines are all located in the gate material layer.

[0077] In other embodiments, the second sub-signal line of the present disclosure may also be located in other film layers with lower load resistance. For example, in an LTPO backplane (Low Temperature Polycrystalline Oxide, i.e., two TFT devices, LTPS and Oxide, are integrated in the same pixel, Oxide is a bottom gate structure, and LTPS is a top gate structure), the backplane also includes a third gate material layer disposed between the second gate material layer 320 and the first source and drain material sublayer 410, and other conductive film layers such as a shielding layer disposed between the poly semiconductor active layer and the substrate. When the second sub-signal line is located in these conductive film layers, the overall load resistance of the driving signal line can also be reduced.

[0078] Furthermore, in some embodiments, a third sub-signal line may be set on other conductive layers (for example, a third gate material layer, a shielding layer, etc.), and the first sub-signal line, the second sub-signal line and the third sub-signal line respectively located in the three conductive layers may be connected in parallel through transfer holes, which can also reduce the overall load resistance of the driving signal line.

[0079] In the present disclosure, the enable signal, gate drive signal and reset signal required in the pixel drive circuit can be provided by the GOA drive circuit located in the peripheral area. The GOA drive circuit can realize row scanning and reduce the manufacturing cost of the array substrate.

[0080] refer to Fig.14, is a circuit diagram of a GOA driving circuit in this embodiment, and the shift register circuit may include: a first switch unit T1, a second switch unit T2, a third switch unit T3, a fourth switch unit T4, a fifth switch unit T5, a sixth switch unit T6, a seventh switch unit T7, an eighth switch unit T8, a first capacitor C1, and a second capacitor C2. The control end of the first switch unit T1 is connected to the clock signal end CK, the first end is connected to the input signal end, and the second end is connected to the first node N1; the control end of the third switch unit T3 is connected to the clock signal end CK, the first end is connected to the power supply end VL, and the second end is connected to the second node N2; the control end of the second switch unit T2 is connected to the first node N1, the clock signal end CK, and the second end is connected to the second node N2; the control end of the sixth switch unit T6 is connected to the second node N2, the first end is connected to the power supply signal end VH; the control end of the seventh switch unit T7 is connected to the clock signal end CB, and the first end is connected to the sixth switch unit T6 The second end of the eighth switch unit T8 is connected to the power supply terminal VL, and the first end is connected to the first node N1; the control end of the fifth switch unit T5 is connected to the second end of the eighth switch unit T8, the first end is connected to the clock signal terminal CB, and the second end is connected to the output terminal OUT; the control end of the fourth switch unit T4 is connected to the second node N2, the first end is connected to the power supply terminal VH, and the second end is connected to the output terminal OUT; the first capacitor C1 is connected between the second end of the eighth switch unit T8 and the output terminal OUT; the second capacitor C2 is connected between the power signal terminal VH and the second node N2.

[0081] refer to Fig.15 ,for Fig.14 A layout of the GOA driving circuit shown, wherein the power signal line VH, the clock signal line CK, and the clock signal line CB are all arranged in the second source and drain material sub-layer 420, one plate of the first capacitor C1 is arranged in the first gate material layer 310, and the other plate is arranged in the second gate material layer 320; one plate of the second capacitor C2 is arranged in the first gate material layer 310, and the other plate is arranged in the second gate material layer 320. In the layout of this embodiment, the output terminal OUT located in the first gate material layer 310 is connected to the first sub-gate driving line 51, so as to output a gate driving signal to the first sub-gate driving line 51. The GOA driving circuit is located in the peripheral area, so the first sub-gate driving line 51 also extends from the peripheral area to the display area. As shown in the figure, the second sub-gate driving line 52 can also extend from the peripheral area to the display area, and the projection of its part located in the peripheral area on the base substrate 100 overlaps with the projection of the part of the first sub-gate driving line 51 in the peripheral area, and the two are electrically connected through a via arranged in the peripheral area. Reference Fig.15 Shows Fig.14In the cross-sectional view taken along the BB direction, since the first gate material layer 310 and the second source-drain material sublayer 420 are separated by the first source-drain material sublayer 410, it is necessary to connect the first sub-gate drive line 51 and the second sub-gate drive line through a conductive connection portion 80 disposed on the first source-drain material sublayer 410, that is, the conductive connection portion 80 and the first sub-gate drive line 51 are connected through a via hole, and the conductive connection portion 80 and the second sub-gate drive line 52 are connected through another via hole.

[0082] In other embodiments, the vias may be provided at other locations, such as the display area. The number of vias may be one or more, and this application does not specifically limit this. When there are multiple vias, they may be provided on opposite sides of the peripheral area, respectively, to electrically connect the first sub-gate drive line 51 and the second sub-gate drive line 52, while no vias are provided in the display area, so as to reduce the via manufacturing in the display area and improve the resolution.

[0083] Fig.15 and Fig.16 In the figure, a layout structure between a GOA driving circuit and a pixel circuit is illustrated by taking the gate drive line as an example. The GOA is Gate GOA. It can be understood by those skilled in the art that the reset signal line of the next-level sub-pixel can be connected to the gate drive line of the previous-level sub-pixel, so that the gate drive signal of the previous-level sub-pixel can be used as the reset signal of the next-level sub-pixel, thereby avoiding the introduction of a dedicated signal line for the reset signal, and effectively reducing the wiring space. Therefore, it can be connected that the output end of the Gate GOA driving circuit is also connected to the first sub-reset signal line 71, and then connected to the second sub-reset signal line 72 through a via hole, so as to transmit the reset signal to each pixel unit. In addition, the GOA driving circuit can also include an output end capable of outputting an enable signal, which is connected to the first sub-enable signal line 61 of the pixel circuit, and then connected to the second sub-enable signal line 62 through a via hole, so as to transmit the enable signal to each pixel unit, that is, the GOA is EM GOA. It should be noted that Gate GOA and EM GOA can be an integral GOA or two independent GOAs, and this application does not specifically limit this.

[0084] It should be understood that Fig.13 The shift register unit provided can be used with Figure 1 The pixel driving circuit is used in combination with the display panel, and the shift register unit provided in this exemplary embodiment can also be used in combination with other pixel driving circuits and applied to the display panel, or the pixel driving circuit provided in this exemplary embodiment can also be used with other shift register units and applied to the display panel. The present disclosure does not limit the shift register unit and the pixel driving circuit.

[0085] The embodiment of the present invention further provides a display device, which includes the array substrate of the above embodiment. Since the display device includes the above array substrate, it has the same beneficial effects, and the present invention will not be repeated here.

[0086] The present invention does not impose any specific restrictions on the applicability of the display device, which can be any product or component with a flexible display function, such as a television, a laptop computer, a tablet computer, a wearable display device, a mobile phone, a car display, a navigation, an e-book, a digital photo frame, an advertising light box, etc.

[0087] It has been verified that the double-layer structure setting of the driving signal line disclosed in the present invention can reduce the load resistance of the GOA circuit to 0.65kΩ. Compared with the single-layer structure, the load of the GOA circuit disclosed in the present invention is reduced to 49% of the single-layer structure, which greatly reduces the output power consumption of the GOA and can reduce the size of the GOA circuit output tube.

[0088] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. An array substrate, comprising a display area and a peripheral area surrounding the display area, wherein: The array substrate further includes: substrate substrate; A gate material layer is provided on one side of the base substrate; A source-drain material layer, the source-drain material layer comprising a first source-drain material sublayer and a second source-drain material sublayer; the first source-drain material sublayer is disposed on a side of the gate material layer away from the substrate; the second source-drain material sublayer is disposed on a side of the first source-drain material sublayer away from the substrate; The array substrate further includes a driving signal line, the driving signal line includes a first sub-signal line and a second sub-signal line, the first sub-signal line is provided in the gate material layer and extends from the peripheral area to the display area, the second sub-signal line is provided in the first source-drain material sub-layer or the second source-drain material sub-layer and is at least located in the display area, and the first sub-signal line and the second sub-signal line are electrically connected in parallel through a via hole to reduce the load resistance of the driving signal line; The array substrate further includes a power line, the power line includes a first sub-power line and a second sub-power line, the first sub-power line is provided in the first source-drain material sub-layer, the second sub-power line is provided in the second source-drain material sub-layer, and the first sub-power line and the second sub-power line are electrically connected through a via; The second sub-signal line and the second sub-power line both extend along the first direction and are arranged along the second direction; the first direction and the second direction intersect; The projection of the second sub-power line on the base substrate overlaps with the projection of the initialization signal line located on the second gate material layer on the base substrate.

2. The array substrate according to claim 1, wherein: The driving signal line includes a gate driving signal line, the first sub-signal line includes a first sub-gate driving line, the second sub-signal line includes a second sub-gate driving line, the first sub-gate driving line is arranged in the gate material layer and extends from the peripheral area to the display area, the second sub-gate driving line is arranged in the first source and drain material sub-layer or the second source and drain material sub-layer and is at least located in the display area, and the first sub-gate driving line and the second sub-gate driving line are electrically connected through a via.

3. The array substrate according to claim 1, wherein: The driving signal line includes an enable signal line, the first sub-signal line includes a first sub-enable signal line, the second sub-signal line includes a second sub-enable signal line, the first sub-enable signal line is arranged in the gate material layer and extends from the peripheral area to the display area, the second sub-enable signal line is arranged in the first source and drain material sub-layer or the second source and drain material sub-layer and is at least located in the display area, and the first sub-enable signal line and the second sub-enable signal line are electrically connected through a via.

4. The array substrate according to claim 1, wherein: The driving signal line includes a reset signal line, the first sub-signal line includes a first sub-reset signal line, the second sub-signal line includes a second sub-reset signal line, the first sub-reset signal line is arranged in the gate material layer and extends from the peripheral area to the display area, the second sub-reset signal line is arranged in the first source and drain material sub-layer or the second source and drain material sub-layer and is at least located in the display area, and the first sub-reset signal line and the second sub-reset signal line are electrically connected through a via.

5. The array substrate according to any one of claims 1 to 4, wherein: The first sub-signal line and the second sub-signal line extend in the same direction or in different directions.

6. The array substrate according to claim 1, wherein: The second sub-signal line is also located in the peripheral region, and the first sub-signal line and the second sub-signal line are electrically connected through a via in the peripheral region.

7. The array substrate according to claim 1, wherein: The line width of the second sub-signal line is greater than the line width of the first sub-signal line.

8. The array substrate according to claim 1, wherein: The array substrate further includes: An interlayer dielectric layer, disposed between the second gate material layer and the first source and drain material sublayer; an insulating layer, disposed between the first source-drain material sublayer and the second source-drain material sublayer; and a planar layer, disposed between the first source-drain material sublayer and the second source-drain material sublayer and located on a side of the insulating layer away from the first source-drain material sublayer.

9. The array substrate according to claim 1, wherein: The array substrate includes a GOA driving circuit, and the first sub-signal line is connected to an output end of the GOA driving circuit.

10. The array substrate according to claim 1, wherein: The gate material layer includes a first gate material layer and a second gate material layer which are stacked and a gate insulating layer located between the first gate material layer and the second gate material layer. The first sub-signal line is located in the first gate material layer or the second gate material layer.

11. A display device, wherein: The invention comprises the array substrate according to any one of claims 1 to 10.

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