Display substrate and method for preparing the same

Abstract

The present disclosure provides a display substrate and a preparation method thereof, wherein the display substrate comprises a substrate and a pixel circuit layer formed on the substrate, the pixel circuit layer comprises a plurality of pixel driving circuits, the plurality of pixel driving circuits are arranged in an array along a first direction and a second direction, the first direction being perpendicular to the second direction, wherein the substrate comprises a groove extending along the first direction, the groove having a bottom surface and a side surface, the surface of the substrate comprises the bottom surface and the side surface of the groove, and a top surface between adjacent grooves, the bottom surface of the groove is substantially parallel to the top surface between adjacent grooves, the side surface of the groove forms a first angle with the bottom surface of the groove and the top surface between adjacent grooves, and a portion of each pixel driving circuit is formed on the side surface of the groove.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a method for preparing the same. Background Art

[0002] With the development of display technology, high-resolution OLED or QLED displays are being used more and more widely, and people have also put forward higher requirements for the resolution of OLED or QLED displays. At present, the resolution of OLED or QLED displays is mainly improved by reasonably arranging the pixels of OLED or QLED displays or sharing pixels. However, due to the complex pixel structure of OLED or QLED displays, improving the resolution only by reasonably arranging the pixels or sharing the pixels may still not achieve the desired resolution. Summary of the invention

[0003] An embodiment of the present disclosure provides a display substrate, comprising a substrate and a pixel circuit layer formed on the substrate, the pixel circuit layer comprising a plurality of pixel driving circuits, the plurality of pixel driving circuits being arranged in an array along a first direction and a second direction, the first direction being perpendicular to the second direction, wherein the substrate has a groove extending along the first direction, the groove having a bottom surface and a side surface, the surface of the substrate comprising the bottom surface and the side surface of the groove, and a top surface between adjacent grooves, the bottom surface of the groove being substantially parallel to the top surface between adjacent grooves, the side surface of the groove forming a first angle with the bottom surface of the groove and the top surface between adjacent grooves, and a portion of each pixel driving circuit being formed on the side surface of the groove.

[0004] In some embodiments, the pixel driving circuit includes a driving subcircuit formed on a side surface of the groove.

[0005] In some embodiments, the pixel driving circuit includes a storage subcircuit formed on a side surface of the groove.

[0006] In some embodiments, the pixel driving circuit includes a data writing sub-circuit formed on a side surface of the groove.

[0007] In some embodiments, the pixel driving circuit includes a light emission control subcircuit formed on the top surface between adjacent grooves.

[0008] In some embodiments, the pixel driving circuit includes a reset subcircuit formed on a bottom surface of the groove.

[0009] In some embodiments, the pixel driving circuit includes a signal line extending along the first direction.

[0010] In some embodiments, the pixel driving circuit includes a signal line extending along the second direction, the signal line including a first portion that is less than or equal to a first distance from a first bending line where a bottom surface and a side surface of the groove intersect, a second portion that is less than or equal to a second distance from a second bending line where a side surface of the groove intersects a top surface between adjacent grooves, and a third portion that is greater than the first distance from the first bending line and greater than the second distance from the second bending line, in a direction parallel to the first bending line, a width of the first portion is greater than a width of the third portion, and in a direction parallel to the second bending line, a width of the second portion is greater than a width of the third portion.

[0011] In some embodiments, the pixel driving circuit includes a signal line extending along the second direction, the signal line including a first portion that is less than or equal to a first distance from a first bending line intersecting a bottom surface and a side surface of the groove, a second portion that is less than or equal to a second distance from a second bending line intersecting a side surface of the groove and a top surface between adjacent grooves, and a third portion that is greater than the first distance from the first bending line and greater than the second distance from the second bending line, in a direction away from the bottom surface and the side surface of the groove, the thickness of the first portion is greater than the thickness of the third portion, and in a direction away from the side surface of the groove and the top surface between adjacent grooves, the thickness of the second portion is greater than the thickness of the third portion.

[0012] In some embodiments, the display substrate further includes: a flexible material layer formed between the substrate and the pixel circuit layer, a first stress relief structure being provided in a portion of the flexible material layer at a distance less than or equal to a first predetermined distance from a first bending line where a bottom surface and a side surface of the groove intersect each other, and a second stress relief structure being provided in a portion of the flexible material layer at a distance less than or equal to a second predetermined distance from a second bending line where a side surface of the groove intersects a top surface between adjacent grooves, each of the first stress relief structure and the second stress relief structure comprising a plurality of trapezoidal blocks arranged at intervals, a size of each trapezoidal block in the first stress relief structure at an end away from the substrate being smaller than a size of an end close to the substrate, and a size of each trapezoidal block in the second stress relief structure at an end close to the substrate being smaller than a size of an end away from the substrate.

[0013] In some embodiments, the side surface and the bottom surface of the groove are connected by a first arc surface, and the side surface of the groove and the top surface between adjacent grooves are connected by a second arc surface.

[0014] In some implementations, in the second direction, adjacent pixel driving circuits are arranged in a mirror-image manner.

[0015] In some embodiments, the pixel driving circuit includes a driving subcircuit, a data writing subcircuit, a light emitting control subcircuit, a reset subcircuit and a storage subcircuit, wherein the driving subcircuit, the data writing subcircuit and the storage subcircuit are formed on the side surfaces of the groove, the light emitting control subcircuit is formed on the top surface between adjacent grooves, and the reset subcircuit is formed on the bottom surface of the groove.

[0016] The driving subcircuit includes a first transistor, the data writing subcircuit includes a second transistor and a third transistor, the storage subcircuit includes a storage capacitor, the light emitting control subcircuit includes a fourth transistor and a fifth transistor, and the reset subcircuit includes a sixth transistor.

[0017] The gate of the first transistor is connected to the first electrode of the second transistor, the first electrode of the storage capacitor and the first electrode of the sixth transistor, the first electrode of the first transistor is connected to the first electrode of the fourth transistor and the first electrode of the third transistor, and the second electrode of the first transistor is connected to the second electrode of the second transistor and the second electrode of the fifth transistor.

[0018] The gate of the second transistor and the gate of the third transistor are both connected to the scan signal line, the second electrode of the third transistor is connected to the data signal line, and the second electrode of the storage capacitor is connected to the first power line.

[0019] The second electrode of the fourth transistor is connected to the first power line, and the gates of the fourth transistor and the fifth transistor are both connected to the light emitting control line.

[0020] The first electrode of the fifth transistor is connected to the anode of the light emitting element.

[0021] A gate electrode of the sixth transistor is connected to a reset control line, and a second electrode of the sixth transistor is connected to a reset signal line.

[0022] In some embodiments, in the second direction, adjacent pixel driving circuits share the reset signal line.

[0023] In some embodiments, the reset control line, the reset signal line, the scan signal line, and the light emitting control line extend along the first direction, and the data line and the first power line include portions extending along the second direction.

[0024] In some embodiments, the scanning signal line, the reset control line, the light emitting control line, the first electrode of the storage capacitor, and the gate of each transistor are formed in the same layer in a first sublayer of the pixel circuit layer, the reset signal line and the second electrode of the storage capacitor are formed in the same layer in a second sublayer of the pixel circuit layer, and the data line, the first power line, and the first electrode and the second electrode of each transistor are formed in the same layer in a third sublayer of the pixel circuit layer.

[0025] In some embodiments, the light emitting element is a quantum dot light emitting diode.

[0026] The present disclosure provides a method for preparing a display substrate, comprising:

[0027] Forming a substrate, the substrate having a groove extending along a first direction, the groove having a bottom surface and a side surface, the surface of the substrate including the bottom surface and the side surface of the groove, and a top surface between adjacent grooves, the bottom surface of the groove and the top surface between adjacent grooves are substantially parallel, and the side surface of the groove forms a first angle with the bottom surface of the groove and the top surface between adjacent grooves;

[0028] A pixel circuit layer including a plurality of pixel driving circuits is formed on the substrate, wherein the plurality of pixel driving circuits are arranged in an array along a first direction and a second direction, wherein the first direction is perpendicular to the second direction,

[0029] A portion of each pixel driving circuit is formed on a side surface of the groove.

[0030] In some embodiments, forming the substrate includes:

[0031] The substrate is formed in a preformed mold using a flexible material.

[0032] In some embodiments, forming a pixel circuit layer including a plurality of pixel driving circuits on the substrate includes:

[0033] forming a layer of flexible material on the glass sheet;

[0034] forming the plurality of pixel driving circuits on the flexible material layer;

[0035] peeling the flexible material layer and the plurality of pixel driving circuits formed thereon from the glass plate;

[0036] The flexible material layer and the plurality of pixel driving circuits formed thereon are attached to the substrate.

[0037] In some embodiments, forming the plurality of pixel driving circuits on the flexible material layer includes:

[0038] A signal line extending along the first direction and a signal line extending along the second direction are formed, and a first portion and a second portion of the signal line extending along the second direction are widened and thickened, wherein:

[0039] After the flexible material layer and the multiple pixel driving circuits formed thereon are adhered to the substrate, the first portion is less than or equal to a first distance from a first bending line where the bottom surface and the side surface of the groove intersect, and the second portion is less than or equal to a second distance from a second bending line where the side surface of the groove intersects with the top surface between adjacent grooves.

[0040] In some embodiments, the preparation method further comprises:

[0041] Before forming the flexible material layer on the glass plate, forming a sacrificial material layer on the glass plate;

[0042] The sacrificial material layer is patterned to form a first stress relief structure and a second stress relief structure, each of the first stress relief structure and the second stress relief structure comprises a plurality of trapezoidal blocks arranged at intervals, a dimension of an end of each trapezoidal block of the first stress relief structure away from the glass plate is smaller than a dimension of an end thereof close to the glass plate, and a dimension of an end of each trapezoidal block of the second stress relief structure close to the glass plate is smaller than a dimension of an end thereof away from the glass plate, wherein:

[0043] After the flexible material layer is formed on the glass plate, the first stress relief structure and the second stress relief structure are embedded in the flexible material layer.

[0044] When the flexible material layer and the plurality of pixel driving circuits formed thereon are peeled off from the glass plate, the first stress relief structure and the second stress relief structure are peeled off from the glass plate together with the flexible material layer.

[0045] After the flexible material layer and the multiple pixel driving circuits formed thereon are adhered to the substrate, the first stress relief structure is less than or equal to a first predetermined distance from a first bending line where the bottom surface and the side surface of the groove intersect, and the second stress relief structure is less than or equal to a second predetermined distance from a second bending line where the side surface of the groove intersects with the top surface between adjacent grooves. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A schematic structural diagram of a display substrate according to an embodiment of the present disclosure is shown;

[0047] Figure 2 A schematic diagram of a pixel in a display substrate according to an embodiment of the present disclosure is shown;

[0048] Figure 3 A schematic diagram showing the tiling of the flexible material layer and the stress relief structure in the display substrate of the embodiment of the present disclosure is shown;

[0049] Figure 4 A schematic diagram of the substrate structure in a display substrate according to an embodiment of the present disclosure is shown;

[0050] Figure 5 A circuit diagram showing a pixel driving circuit in a display substrate according to an embodiment of the present disclosure is shown;

[0051] Figure 6 Shows Figure 5 A schematic diagram of the layout of the pixel driving circuit shown;

[0052] Figure 7 Shows Figure 5 A schematic diagram of a hierarchical layout of a pixel driving circuit is shown;

[0053] Figure 8 A schematic diagram showing a pixel driving circuit layout and pixel arrangement in a display substrate according to an embodiment of the present disclosure;

[0054] Fig. 9 A flow chart showing a method for preparing a display substrate according to an embodiment of the present disclosure is shown;

[0055] Fig.10 A schematic diagram showing a process of forming a pixel circuit layer on a substrate in a method for preparing a display substrate according to an embodiment of the present disclosure;

[0056] Fig.11 Another schematic diagram of a process of forming a pixel circuit layer on a substrate in a method for preparing a display substrate according to an embodiment of the present disclosure is shown;

[0057] Fig.12 Another flow chart showing a method for preparing a display substrate according to an embodiment of the present disclosure;

[0058] Fig.13 A schematic diagram of the preparation process of the display substrate according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0059] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0060] The present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the accompanying drawings.

[0061] Many specific details of the present disclosure are described below, such as component structures, materials, dimensions, processing techniques, and technologies, in order to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may be implemented without following these specific details.

[0062] In the present disclosure, the first direction and the second direction are interchangeable, and the “first pole” and the “second pole” of each transistor are interchangeable.

[0063] The present disclosure provides a display substrate, such as Figure 1 , Figure 2 As shown, the display substrate includes a substrate 1 and a pixel circuit layer 2 formed on the substrate 1, the pixel circuit layer 2 includes a plurality of pixel driving circuits, and the plurality of pixel driving circuits are arranged in an array along a first direction (X direction) and a second direction (Y direction), the first direction being perpendicular to the second direction, wherein the substrate 1 has a groove 3 extending along the first direction, the groove 3 having a bottom surface 31 and a side surface 32, the surface of the substrate 1 includes the bottom surface 31 and the side surface 32 of the groove 3, and a top surface 4 between adjacent grooves, the bottom surface 31 of the groove 3 is substantially parallel to the top surface 4 between adjacent grooves, the side surface 32 of the groove 3 forms a first angle α with the bottom surface 31 of the groove 3 and the top surface 4 between adjacent grooves, and a portion of each pixel driving circuit is formed on the side surface 32 of the groove 3.

[0064] In the embodiment of the present disclosure, the first angle α formed between the side surface 32 of the groove 3 and the bottom surface 31 of the groove 3 and the top surface 4 between adjacent grooves may mean that the angle formed between the side surface 32 of the groove 3 and the bottom surface 31 of the groove 3 inside the groove 3 is equal to the first angle α, and the angle formed between the side surface 32 of the groove 3 and the top surface 4 between adjacent grooves outside the groove 3 is equal to the first angle α, such as Figure 1 shown.

[0065] The material of the substrate 1 may include, but is not limited to, flexible organic materials such as polyimide (PI), polydimethylsiloxane (PDMS), polymethyl methacrylate (PMMA), or polyvinyl chloride (PVC).

[0066] In some embodiments, Figure 1As shown, the display substrate of the embodiment of the present disclosure may also include: a planarization layer 5 formed on a side of the pixel circuit layer 2 away from the substrate 1; a pixel defining layer 6 formed on a side of the planarization layer 5 away from the pixel circuit layer 2, and an anode 7 of a light-emitting element corresponding to the multiple pixel driving circuits (for example, one-to-one), wherein an opening area of ​​the pixel defining layer 6 exposes the anode 7 of the light-emitting element.

[0067] It should be understood that the anode 7 of the light emitting element can be connected to the pixel driving circuit in the pixel circuit layer 2 through the via hole in the planarization layer 5 .

[0068] The light emitting element may be, for example, an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED).

[0069] like Figure 2 As shown, in the display substrate of the embodiment of the present disclosure, the pixel circuit layer 2 includes a folding area 8, and the folding area 8 corresponds to the side surface 32 of the groove 3, that is, part of the folding area 8 of the pixel circuit layer 2 is formed on the side surface 32 of the groove. Obviously, the area of ​​the orthographic projection of the folding area 8 on the substrate 1 is greatly reduced compared with the area of ​​the folding area 8.

[0070] Specifically, a portion of each pixel driving circuit in the pixel circuit layer 2 is located in the folding area 8, formed on the side surface 32 of the groove 3, so that the area of ​​the positive projection of each pixel driving circuit in the pixel circuit layer 2 on the substrate 1 is greatly reduced compared to the layout area of ​​the pixel driving circuit. In this way, on the basis of ensuring the performance of the display substrate, the density of the anode 7 of the light-emitting element on the display substrate of the embodiment of the present disclosure can be increased accordingly, thereby achieving a higher pixel density.

[0071] It should be understood that in order to make the area of ​​the orthographic projection of the folding region 8 on the substrate 1 smaller than the area of ​​the folding region 8, the first angle α in the embodiment of the present disclosure may be greater than or equal to 90° and less than 180°.

[0072] In some embodiments, in order to meet the layout requirements of each pixel driving circuit in the pixel circuit layer 2 and make the area of ​​the positive projection of each pixel driving circuit in the pixel circuit layer 2 on the substrate 1 smaller, the first angle α can be greater than or equal to 90° and less than or equal to 105°.

[0073] In order to reasonably layout the pixel driving circuit and effectively improve the pixel density, each pixel driving circuit in the pixel circuit layer 2 can be arranged in a groove area AA, and in each of the groove areas AA, the sum of the areas of the bottom surface 31 of the groove 3 and the top surface 4 between adjacent grooves is equal to the area of ​​the side surface 32 of the groove 3 or half of it.

[0074] For example, Figure 1 As shown, in a direction perpendicular to the extension direction of the groove 3 (e.g., the second direction), in each groove area AA, the sum of the width W1 of the bottom surface portion of the groove 3 and the width W2 of the top surface portion between adjacent grooves is equal to the width W3 of the side surface 32 of the groove 3, or is half of the width W3 of the side surface 32 of the groove 3.

[0075] It should be understood that the larger the area of ​​the side surface 32 of the groove 3 is, the larger the portion of the pixel driving circuit that can be laid out on the side surface 32 of the groove 3 is, so that the area of ​​the positive projection of the pixel driving circuit on the substrate 1 is reduced more compared to the layout area of ​​the pixel driving circuit, and the highest possible pixel density can be achieved.

[0076] In some embodiments, the pixel driving circuit in the pixel circuit layer 2 may include multiple signal lines. In order to ensure the performance of the signal lines, each signal line may extend along the first direction as much as possible. If it is unavoidable that there are signal lines extending along the second direction, the first portion P1 of the signal line whose distance from the first bending line L1 where the bottom surface 31 of the groove 3 intersects with the side surface 32 can be less than or equal to the first distance d1, and the second portion P2 of the signal line whose distance from the second bending line L2 where the side surface 32 of the groove 3 intersects with the top surface 4 between adjacent grooves is less than or equal to the second distance d2 can be widened and / or thickened to avoid the signal line from breaking when passing through the first bending line L1 and the second bending line L2.

[0077] Specifically, the signal line extending along the second direction may include a first portion P1 whose distance from the first bending line L1 where the bottom surface 31 of the groove 3 intersects with the side surface 32 is less than or equal to the first distance d1, a second portion P2 whose distance from the second bending line L2 where the side surface 32 of the groove 3 intersects with the top surface 4 between adjacent grooves is less than or equal to the second distance d2, and a third portion whose distance from the first bending line L1 is greater than the first distance d1 and whose distance from the second bending line L2 is greater than the second distance d2. In a direction parallel to the first bending line L1, the width of the first portion P1 may be greater than the width of the third portion, and in a direction parallel to the second bending line L2, the width of the second portion P2 may be greater than the width of the third portion, which will be specifically shown later ( Figure 6).

[0078] Alternatively, in a direction away from the bottom surface 31 and the side surface 32 of the groove 3, the thickness of the first portion P1 may be greater than the thickness of the third portion, and in a direction away from the side surface 32 of the groove 3 and the top surface 4 between adjacent grooves, the thickness of the second portion P2 may be greater than the thickness of the third portion. Figure 1 shown.

[0079] It should be understood that the first distance d1 and the second distance d2 may be the same or different, and those skilled in the art may select the values ​​of the first distance d1 and the second distance d2 as needed, which may help avoid the signal line from breaking when passing through the first bending line L1 and the second bending line L2.

[0080] In addition, a stress relief structure may be added at the first bending line L1 and the second bending line L2 to prevent the signal line from breaking when passing through the first bending line L1 and the second bending line L2.

[0081] In some embodiments, Figure 3 As shown, the display substrate may further include: a flexible material layer 9 formed between the substrate 1 and the pixel circuit layer 2, a first stress relief structure F1 may be provided in a portion of the flexible material layer 9 where the distance from the first bending line L1 where the bottom surface 31 and the side surface 32 of the groove 3 intersect is less than or equal to the first predetermined distance d1', a second stress relief structure F2 may be provided in a portion of the flexible material layer 9 where the distance from the second bending line L2 where the side surface 32 of the groove 3 intersects with the top surface 4 between adjacent grooves is less than or equal to the second predetermined distance d2', each of the first stress relief structure F1 and the second stress relief structure F2 may include a plurality of trapezoidal blocks arranged at intervals, a size of each trapezoidal block in the first stress relief structure F1 at an end away from the substrate 1 may be smaller than a size of an end close to the substrate 1, and a size of each trapezoidal block in the second stress relief structure F2 at an end close to the substrate 1 is smaller than a size of an end away from the substrate 1.

[0082] It should be understood that the first predetermined distance d1' and the second predetermined distance d2' may be the same or different, and those skilled in the art may select the values ​​of the first predetermined distance d1' and the second predetermined distance d2' as needed, which may help avoid the signal line from breaking when passing through the first bending line L1 and the second bending line L2.

[0083] For ease of description and illustration, Figure 3Only the flattening schematic diagram of the flexible material layer 9 and the pixel circuit layer 2 is shown. Figure 3 As shown, each trapezoidal block in the first stress relief structure F1 is a regular trapezoid, and each trapezoidal block in the second stress relief structure F2 is an inverted trapezoid.

[0084] The material of the flexible material layer 9 includes, but is not limited to, for example, polyimide (PI), polydimethylsiloxane (PDMS), polymethyl methacrylate (PMMA), or polyvinyl chloride (PVC), ultra-thin glass, or a laminate of the above organic materials and inorganic materials such as silicon oxide, silicon nitride, etc.

[0085] In some embodiments, the thickness of the flexible material layer 9 may be 5 μm to 50 μm.

[0086] The first stress relief structure F1 and the second stress relief structure F2 may be made of sacrificial materials such as photoresist and aluminum, for example, so as to be formed by a patterning process (such as dry etching, wet etching, etc.).

[0087] Due to the setting of the first stress relief structure F1, when the signal line passes through the first bending line L1, the stress of the signal line on the side close to the first stress relief structure F1 and the side far from the first stress relief structure F1 is balanced, thereby preventing the signal line from breaking when passing through the first bending line L1. Similarly, due to the setting of the second stress relief structure F2, when the signal line passes through the second bending line L2, the stress of the signal line on the side close to the second stress relief structure F2 and the side far from the second stress relief structure F2 is balanced, thereby preventing the signal line from breaking when passing through the second bending line L2.

[0088] In some embodiments, the shape of the groove 3 at the first bending line L1 and the second bending line L2 may be modified to avoid the signal line from being broken when passing through the corresponding positions.

[0089] For example, Figure 4 As shown, the side surface 32 and the bottom surface 31 of the groove 3 can be connected via the first arc surface ARC1, and the side surface 32 of the groove 3 and the top surface 4 between adjacent grooves can be connected via the second arc surface ARC2. Obviously, the risk of the signal line breaking when passing through the first arc surface ARC1 and the second arc surface ARC2 is low.

[0090] It should be understood that the first arc surface ARC1 and the second arc surface ARC2 can be, but are not limited to, circular arc surfaces or elliptical arc surfaces. The present disclosure does not make specific limitations on this. It only needs to reduce or avoid the risk of breakage of the signal line when passing through the first arc surface ARC1 and the second arc surface ARC2.

[0091] In the embodiment of the present disclosure, the pixel driving circuit may include a driving subcircuit, a storage subcircuit, a data writing subcircuit, a light-emitting control subcircuit and a reset subcircuit. Generally, the driving subcircuit and the storage subcircuit require a larger area for layout. Therefore, in order to achieve a higher pixel density, the driving subcircuit and / or the storage subcircuit may be laid out on the side surface 32 of the groove 3. In order to further improve the pixel density, the data writing subcircuit that has a close connection relationship with the driving subcircuit may also be laid out on the side surface 32 of the groove 3. For the light-emitting control subcircuit, since the light-emitting control subcircuit is connected to the light-emitting element, in order to facilitate the connection between the light-emitting control subcircuit and the light-emitting element, the light-emitting control subcircuit may be laid out on the top surface 4 between adjacent grooves. In addition, the reset subcircuit may be laid out on the bottom surface 31 of the groove 3.

[0092] It should be understood that the layout of the pixel driving circuit may not be limited to the above layout. For example, no sub-circuit may be arranged on the bottom surface 31 of the groove 3. However, since there is a connection relationship between adjacent pixel driving circuits, a connection structure between adjacent pixel circuits (such as connecting electrodes, connecting lines, etc.) may be arranged on the bottom surface 31 of the groove 3.

[0093] In some embodiments, to facilitate overall layout and reduce process difficulty, the area of ​​the bottom surface 31 of the groove 3 occupied by each pixel driving circuit may be substantially equal, and the area of ​​the top surface 4 between adjacent grooves occupied by each pixel driving circuit may be substantially equal.

[0094] like Figure 5As shown, in the embodiment of the present disclosure, the driving subcircuit may include a first transistor M1, the storage subcircuit may include a storage capacitor C1, the data writing subcircuit may include a second transistor M2 and a third transistor M3, the light emitting control subcircuit may include a fourth transistor M4 and a fifth transistor M5, and the reset subcircuit may include a sixth transistor M6. The gate of the first transistor M1 is connected to the first electrode of the second transistor M2, the first electrode of the storage capacitor C1, and the first electrode of the sixth transistor M6, the first electrode of the first transistor M1 is connected to the first electrode of the fourth transistor M4 and the first electrode of the third transistor M3, and the second electrode of the first transistor M1 is connected to the second electrode of the second transistor M2 and the second electrode of the fifth transistor M5. The gate of the second transistor M2 and the gate of the third transistor M3 are both connected to the scan signal line, and the second electrode of the third transistor M3 is connected to the data signal line. The second electrode of the storage capacitor C1 is connected to the first power line VDD. The second electrode of the fourth transistor M4 is connected to the first power line VDD, and the gates of the fourth transistor M4 and the fifth transistor M5 are both connected to the light emitting control line. The first electrode of the fifth transistor M5 is connected to the anode of the light emitting element (such as OLED or QLED). A gate electrode of the sixth transistor M6 is connected to a reset control line, and a second electrode of the sixth transistor M6 is connected to a reset signal line Vint.

[0095] For the convenience of description, in the embodiment of the present disclosure, the first direction (X direction) is the row direction and the second direction (Y direction) is the column direction. That is, the groove 3 is extended along the row direction.

[0096] The pixel driving circuits in the same row may be connected to the same scanning signal line, the same light-emitting control line, and the same reset control line, and the pixel driving circuits in the same column may be connected to the same data signal line. For example, in each pixel driving circuit in the nth row, the gate of the second transistor M2 and the gate of the third transistor M3 are both connected to the scanning signal line Gn, the gate of the fourth transistor M4 and the gate of the fifth transistor M5 are both connected to the light-emitting control line EMn, and the gate of the sixth transistor M6 is connected to the reset control line Ren; in each pixel driving circuit in the n+1th row, the gate of the second transistor M2 and the gate of the third transistor M3 are both connected to the scanning signal line Gn+1, the gate of the fourth transistor M4 and the gate of the fifth transistor M5 are both connected to the light-emitting control line EMn+1, and the gate of the sixth transistor M6 is connected to the reset control line Ren+1; in each pixel driving circuit in the mth column, the second electrode of the third transistor M3 is connected to the data signal line Datam.

[0097] In some embodiments, the pixel driving circuit may further include a seventh transistor M7, a first electrode of which may be connected to the first electrode of the fifth transistor M5 and the anode of the light-emitting element. In each pixel driving circuit of the nth row, a gate of the seventh transistor M7 may be connected to a reset control line Ren-1 of a pixel driving circuit in the previous row; in each pixel driving circuit of the n+1th row, a gate of the seventh transistor M7 may be connected to a reset control line Ren of a pixel driving circuit in the previous row.

[0098] It should be understood that in each row of pixel driving circuits, the gate of the seventh transistor M7 can also be connected to the reset control line of the pixel driving circuit in the next row. For example, in each pixel driving circuit in the nth row, the gate of the seventh transistor M7 can also be connected to the reset control line Ren+1 of the pixel driving circuit in the next row. This is not shown and described in detail in the present disclosure.

[0099] In the embodiment of the present disclosure, when the groove 3 extends along the row direction, the pixel driving circuits of adjacent rows in the same column can be arranged in a mirror image, such as Figure 5 As shown, the overall layout is further facilitated and the process difficulty is reduced.

[0100] Furthermore, adjacent pixel driving circuits in the same column (row) may share a reset signal line Vint, such as Figure 5 As shown, to reduce wiring, etc.

[0101] Figure 6 Shows Figure 5 The layout diagram of the pixel driving circuit is shown in FIG. Figure 6 As shown, the first transistor M1, the second transistor M2, the third transistor M3 and the storage capacitor C can be arranged on the side surface 32 of the groove 3, the fourth transistor M4, the fifth transistor M5 and the seventh transistor M7 can be arranged on the top surface 4 between adjacent grooves, and the sixth transistor M6 can be arranged on the bottom surface 31 of the groove 3.

[0102] Figure 6 In the example shown, adjacent pixel driving circuits in the same column (row) are arranged in a mirror image and share a reset signal line Vint.

[0103] In addition, when the groove 3 extends along the row direction, Figure 6As shown, the reset control line (e.g., Ren-1, Ren, Ren+1), the reset signal line Vint, the scan signal line (e.g., Gn, Gn+1), the light emitting control line (e.g., EMn, EMn+1), etc. can all be extended along the first direction (i.e., the row direction) to avoid breaking when passing through the first bending line L1 and the second bending line L2; the data line (e.g., Datam) and the first power line VDD may include portions extending along the second direction, but the portions of the data line and the power line VDD extending along the second direction and passing through the first bending line L1 and the second bending line L2 can be widened in a direction parallel to the first bending line L1 and the second bending line L2 (e.g., Figure 6 ), and / or, thickening in a direction away from its forming surface (e.g., the bottom surface 31 of the groove 3, the side surface 32 of the groove 3, or the top surface 4 between adjacent grooves) (e.g., Figure 1 As shown) to prevent the data line and the power line VDD from being broken when passing through the first bending line L1 and the second bending line L2.

[0104] Figure 7 Shows Figure 5 Schematic diagram of the hierarchical layout of the pixel driving circuit shown.

[0105] like Figure 7 As shown, Figure 5 In the pixel driving circuit shown, the reset control line (for example, Ren-1, Ren, Ren+1), the scanning signal line (for example, Gn, Gn+1), the light emitting control line (for example, EMn, EMn+1), the first electrode of the storage capacitor C1, and the gates of each transistor (including the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7) can be formed in the same layer on the first sub-layer Metal 1, the reset signal line Vint and the second electrode of the storage capacitor C1 can be formed in the same layer on the second sub-layer Metal 2, the data line (for example, Datam), the first power line VDD, and the first electrode and the second electrode of each transistor (including the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7) can be formed in the same layer on the third sub-layer Metal 3, so as to reduce the process steps and reduce the process difficulty.

[0106] In addition, active layers of the transistors (including the first transistor M1 , the second transistor M2 , the third transistor M3 , the fourth transistor M4 , the fifth transistor M5 , the sixth transistor M6 , and the seventh transistor M7 ) may be formed in the same layer on the fourth sub-layer ACT.

[0107] It should be understood that, as needed, an insulating layer and / or a dielectric layer may be formed between the first sublayer, the second sublayer, the third sublayer and the fourth sublayer, and vias may be formed in the insulating layer and / or the dielectric layer, so that different sublayers can be connected through the vias in the insulating layer and / or the dielectric layer.

[0108] It should be understood that in the embodiment of the present disclosure, the groove 3 can extend along the column direction. In this case, adjacent (column) pixel driving circuits in the same row can be mirrored, and adjacent (column) pixel driving circuits in the same row can share the reset signal line Vint to facilitate the overall layout, reduce the process difficulty, and reduce wiring.

[0109] In addition, when the groove 3 extends along the column direction, the signal line that crosses the extending direction of the groove 3 at right angles may not be the data line and the power line VDD, but the portion of the signal line extending perpendicular to the extending direction of the groove 3 that passes through the first bending line L1 and the second bending line L2 may also be widened and / or thickened to avoid breakage of the signal line.

[0110] A person skilled in the art should be able to derive an embodiment in which the groove 3 extends along the column direction according to the embodiment of the present disclosure, so the present disclosure will no longer show and describe in detail the embodiment in which the groove 3 extends along the column direction.

[0111] In the embodiment of the present disclosure, not only the portion of the signal line passing through the first bending line L1 and the second bending line L2 can be widened and / or thickened, but if other structures in the pixel driving circuit (such as electrodes, etc.) also include portions passing through the first bending line L1 and the second bending line L2, they can also be widened and / or thickened to avoid breakage, which will not be shown and described in detail in the present disclosure.

[0112] Figure 8 A schematic diagram showing a pixel driving circuit layout and pixel arrangement in a display substrate according to an embodiment of the present disclosure is shown.

[0113] like Figure 8 As shown, the folding area 8 of the pixel driving circuit layout hardly affects the pixel arrangement, and the multiple pixel driving circuits can correspond to the diamond-shaped pixel arrangement to achieve higher resolution.

[0114] The diamond-shaped pixel arrangement is a typical high-resolution pixel arrangement, which will not be described in detail in this disclosure.

[0115] also, Figure 8The schematic diagram shows a via hole VIA in the planarization layer 5 , and the anode 7 of the light-emitting element can be connected to the pixel driving circuit in the pixel circuit layer 2 through the via hole VIA.

[0116] The present disclosure also provides a method for preparing the above-mentioned display substrate. Fig. 9 As shown, the preparation method includes the steps of: S1, forming a substrate 1, the substrate 1 having a groove 3 extending along a first direction, the groove 3 having a bottom surface 31 and a side surface 32, the surface of the substrate 1 including the bottom surface 31 and the side surface 32 of the groove 3, and a top surface 4 between adjacent grooves, the bottom surface 31 of the groove 3 is substantially parallel to the top surface 4 between adjacent grooves, and the side surface 32 of the groove 3 forms a first angle α with the bottom surface 31 of the groove 3 and the top surface 4 between adjacent grooves; S2, forming a pixel circuit layer 2 including a plurality of pixel driving circuits on the substrate 1, the plurality of pixel driving circuits are arranged in an array along a first direction and a second direction, the first direction being perpendicular to the second direction, wherein a portion of each pixel driving circuit is formed on the side surface 32 of the groove 3.

[0117] In some embodiments, the step S1 may include: forming the substrate 1 in a prefabricated mold using a flexible material.

[0118] The flexible material may include, but is not limited to, flexible organic materials such as polyimide (PI), polydimethylsiloxane (PDMS), polymethyl methacrylate (PMMA), or polyvinyl chloride (PVC).

[0119] In some embodiments, Fig.10 As shown, the step S2 may include the following steps: S21, forming a flexible material layer 9 on a glass plate; S22, forming the plurality of pixel driving circuits on the flexible material layer 9; S23, peeling the flexible material layer 9 and the plurality of pixel driving circuits formed thereon from the glass plate; S24, attaching the flexible material layer 9 and the plurality of pixel driving circuits formed thereon to the substrate 1.

[0120] The material of the flexible material layer 9 includes, but is not limited to, for example, polyimide (PI), polydimethylsiloxane (PDMS), polymethyl methacrylate (PMMA), or polyvinyl chloride (PVC), ultra-thin glass, or a laminate of the above organic materials and inorganic materials such as silicon oxide, silicon nitride, etc. The thickness of the flexible material layer can be 5 μm to 50 μm.

[0121] In some embodiments, the step S22 may include: forming a signal line extending along the first direction and a signal line extending along the second direction, and widening and thickening a first portion P1 and a second portion P2 of the signal line extending along the second direction, wherein, after the step S24, the first portion P1 is less than or equal to a first distance d1 from a first bending line L1 where the bottom surface 31 of the groove 3 intersects with the side surface 32, and the second portion P2 is less than or equal to a second distance d2 from a second bending line L2 where the side surface 32 of the groove 3 intersects with the top surface 4 between adjacent grooves.

[0122] It should be understood that the first distance d1 and the second distance d2 may be the same or different, and those skilled in the art may select the values ​​of the first distance d1 and the second distance d2 as needed, which may help avoid the signal line from breaking when passing through the first bending line L1 and the second bending line L2.

[0123] In some embodiments, the step S22 may include: forming a reset control line (e.g., Ren-1, Ren, Ren+1), a scan signal line (e.g., Gn, Gn+1), a light emitting control line (e.g., EMn, EMn+1), a first electrode of a storage capacitor C1, and a gate of each transistor (including a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7) in the same layer in the first sub-layer Metal1 through the same patterning process; forming a reset signal line Vint and a second electrode of the storage capacitor C1 in the same layer in the second sub-layer Metal2 through the same patterning process; and forming a data line (e.g., Datam), a first power line VDD, and a first electrode and a second electrode of each transistor (including a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7) in the same layer in the third sub-layer Metal3 through the same patterning process.

[0124] In some embodiments, the step S22 may also include: forming an active layer of each transistor (including a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7) on the same layer of the fourth sublayer ACT through the same patterning process.

[0125] It should be understood that, as needed, an insulating layer and / or a dielectric layer may be formed between the first sublayer, the second sublayer, the third sublayer and the fourth sublayer, and vias may be formed in the insulating layer and / or the dielectric layer, so that different sublayers can be connected through the vias in the insulating layer and / or the dielectric layer.

[0126] In some embodiments, the step S23 may include: peeling the flexible material layer 9 and the plurality of pixel driving circuits formed thereon from the glass plate by using a laser lift off (LLO) technique.

[0127] Specifically, an infrared laser can be used to scan the interface between the flexible material layer 9 and the glass plate from the side of the glass plate away from the flexible material layer 9, and the flexible material layer 9 absorbs heat and deforms. Accompanied by the ablation caused by the infrared laser, the bonding between the flexible material layer 9 and the glass plate is destroyed, thereby achieving the peeling of the flexible material layer 9 and the multiple pixel driving circuits formed thereon from the glass plate.

[0128] In some embodiments, the step S24 may include: attaching the flexible material layer 9 and the plurality of pixel driving circuits formed thereon to the substrate 1 by mechanical embossing, electrostatic adsorption, or the like.

[0129] In some embodiments, Fig.11 As shown, the preparation method may further include the step: S20, before the step S21, forming a sacrificial material layer on the glass plate, and patterning the sacrificial material layer to form a first stress relief structure F1 and a second stress relief structure F2, each of the first stress relief structure F1 and the second stress relief structure F2 includes a plurality of trapezoidal blocks arranged at intervals, a size of an end of each trapezoidal block in the first stress relief structure F1 away from the glass plate is smaller than a size of an end thereof close to the glass plate, and a size of each trapezoidal block in the second stress relief structure F2 close to the glass plate is smaller than a size of an end thereof away from the glass plate.

[0130] In this case, in the step S21, the flexible material layer 9 is formed on the side of the glass plate where the first stress relief structure F1 and the second stress relief structure F2 are formed, so that the first stress relief structure F1 and the second stress relief structure F2 are embedded in the flexible material layer 9, in the step S23, the first stress relief structure F1 and the second stress relief structure F2 are peeled off the glass plate together with the flexible material layer 9, in the step S24, the first stress relief structure F1 and the second stress relief structure F2 are attached to the substrate 1 together with the flexible material layer 9, and then, the first stress relief structure F1 is less than or equal to a first predetermined distance d1' from a first bending line L2 where the bottom surface 31 and the side surface 32 of the groove 3 intersect, and the second stress relief structure F2 is less than or equal to a second predetermined distance d2' from a second bending line L2 where the side surface 32 of the groove 3 intersects with the top surface 4 between adjacent grooves.

[0131] It should be understood that the first predetermined distance d1' and the second predetermined distance d2' may be the same or different, and those skilled in the art may select the values ​​of the first predetermined distance d1' and the second predetermined distance d2' as needed, which may help avoid the signal line from breaking when passing through the first bending line L1 and the second bending line L2.

[0132] The sacrificial material layer may be made of sacrificial materials such as photoresist and aluminum, so as to form the first stress relief structure F1 and the second stress relief structure F2 through a patterning process (such as dry etching, wet etching, etc.).

[0133] In some embodiments, Fig.12 As shown, the preparation method also includes the steps of: S3, forming a planarization layer 5 on the side of the pixel circuit layer 2 away from the substrate 1; S4, forming an anode 7 of the light-emitting element on the planarization layer 5; and S5, forming a pixel defining layer 6 on the side of the pixel circuit layer 2 and the anode 7 away from the substrate 1, wherein the opening area of ​​the pixel defining layer 6 exposes the anode 7 of the light-emitting element.

[0134] It should be understood that the anode 7 of the light-emitting element can be connected to the pixel driving circuit in the pixel circuit layer 2 through the via in the planarization layer 5. The planarization layer 5 can be formed by spin coating, inkjet printing, 3D printing and other processes. The via in the planarization layer 5 can be formed by photolithography or mask etching after the planarization layer 5 is formed, or the planarization layer 5 with vias can be directly formed by printing.

[0135] Fig.13A schematic diagram of the preparation process of the display substrate according to an embodiment of the present disclosure is shown.

[0136] like Fig.13 As shown, the pixel circuit layer 2 is first formed on the glass plate GS, and the pixel circuit layer 2 is peeled off the glass plate GS; then the pixel circuit layer 2 is attached to the substrate 1, and a planarization layer 5 is formed on the pixel circuit layer 2; then, an anode 7 of a light-emitting element corresponding to a plurality of pixel driving circuits in the pixel circuit layer 2 (for example, one-to-one correspondence) is formed on a side of the planarization layer 5 away from the pixel circuit layer 2, wherein the anode 7 of the light-emitting element can be connected to the pixel driving circuit in the pixel circuit layer 2 through a via hole in the planarization layer 5; and then the pixel defining layer 6 is formed, wherein the opening area of ​​the pixel defining layer 6 exposes the anode 7 of the light-emitting element.

[0137] It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the article, method, or process including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such articles, methods, or processes. In the absence of more restrictions, the elements limited by the statement "comprise one..." do not exclude the existence of other identical elements in the article, method, or process including the element.

[0138] The embodiments of the present disclosure do not describe all the details of the present disclosure in detail, and the present disclosure is not limited to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. The embodiments selected and specifically described in the present disclosure are only for better explaining the principles and practical applications of the present disclosure, so that those skilled in the art can make good use of the present disclosure and modifications based on the present disclosure. The present disclosure is only limited by the full scope of the claims and equivalents.

Claims

1. A display substrate, comprising a substrate and a pixel circuit layer formed on the substrate, wherein the pixel circuit layer comprises a plurality of pixel driving circuits, and the plurality of pixel driving circuits are arranged in an array along a first direction and a second direction, wherein the first direction is perpendicular to the second direction, The substrate has a groove extending in a first direction, the groove has a bottom surface and a side surface, the surface of the substrate includes the bottom surface and the side surface of the groove, and a top surface between adjacent grooves, the bottom surface of the groove is substantially parallel to the top surface between adjacent grooves, the side surface of the groove forms a first angle with the bottom surface of the groove and the top surface between adjacent grooves, a part of each pixel driving circuit is formed on the side surface of the groove, The pixel driving circuit includes at least one of a driving sub-circuit, a storage sub-circuit and a data writing sub-circuit formed on a side surface of the groove.

2. The display substrate according to claim 1, wherein: The pixel driving circuit includes a light emission control subcircuit formed on the top surface between adjacent grooves.

3. The display substrate according to claim 1, wherein: The pixel driving circuit includes a reset subcircuit formed on a bottom surface of the groove.

4. The display substrate according to claim 1, wherein: The pixel driving circuit includes a signal line extending along the first direction.

5. The display substrate according to claim 1, wherein: The pixel driving circuit includes a signal line extending along the second direction, the signal line including a first portion which is less than or equal to a first distance from a first bending line where a bottom surface and a side surface of the groove intersect, a second portion which is less than or equal to a second distance from a second bending line where a side surface of the groove intersects a top surface between adjacent grooves, and a third portion which is greater than the first distance from the first bending line and greater than the second distance from the second bending line, in a direction parallel to the first bending line, a width of the first portion is greater than a width of the third portion, and in a direction parallel to the second bending line, a width of the second portion is greater than a width of the third portion.

6. The display substrate according to claim 1, wherein: The pixel driving circuit includes a signal line extending along the second direction, the signal line including a first portion which is less than or equal to a first distance from a first bending line intersecting a bottom surface and a side surface of the groove, a second portion which is less than or equal to a second distance from a second bending line intersecting a side surface of the groove and a top surface between adjacent grooves, and a third portion which is greater than the first distance from the first bending line and greater than the second distance from the second bending line, in a direction away from the bottom surface and the side surface of the groove, a thickness of the first portion is greater than a thickness of the third portion, and in a direction away from the side surface of the groove and a top surface between adjacent grooves, a thickness of the second portion is greater than a thickness of the third portion.

7. The display substrate according to claim 1, further comprising: A flexible material layer is formed between the substrate and the pixel circuit layer, a first stress relief structure is arranged in a portion of the flexible material layer at a distance less than or equal to a first predetermined distance from a first bending line where a bottom surface and a side surface of the groove intersect each other, and a second stress relief structure is arranged in a portion of the flexible material layer at a distance less than or equal to a second predetermined distance from a second bending line where a side surface of the groove intersects a top surface between adjacent grooves, each of the first stress relief structure and the second stress relief structure comprises a plurality of trapezoidal blocks arranged at intervals, a size of each trapezoidal block in the first stress relief structure at an end away from the substrate is smaller than a size of the end close to the substrate, and a size of each trapezoidal block in the second stress relief structure at an end close to the substrate is smaller than a size of the end away from the substrate.

8. The display substrate according to claim 1, wherein: The side surface and the bottom surface of the groove are connected via a first arc surface, and the side surface of the groove and the top surface between adjacent grooves are connected via a second arc surface.

9. The display substrate according to claim 1, wherein: In the second direction, adjacent pixel driving circuits are arranged in a mirror image.

10. The display substrate according to claim 1, wherein: The pixel driving circuit includes a driving subcircuit, a data writing subcircuit, a light emitting control subcircuit, a reset subcircuit and a storage subcircuit, wherein the driving subcircuit, the data writing subcircuit and the storage subcircuit are formed on the side surfaces of the groove, the light emitting control subcircuit is formed on the top surface between adjacent grooves, and the reset subcircuit is formed on the bottom surface of the groove. The driving subcircuit includes a first transistor, the data writing subcircuit includes a second transistor and a third transistor, the storage subcircuit includes a storage capacitor, the light emitting control subcircuit includes a fourth transistor and a fifth transistor, and the reset subcircuit includes a sixth transistor. The gate of the first transistor is connected to the first electrode of the second transistor, the first electrode of the storage capacitor and the first electrode of the sixth transistor, the first electrode of the first transistor is connected to the first electrode of the fourth transistor and the first electrode of the third transistor, and the second electrode of the first transistor is connected to the second electrode of the second transistor and the second electrode of the fifth transistor. The gate of the second transistor and the gate of the third transistor are both connected to the scan signal line, the second electrode of the third transistor is connected to the data line, and the second electrode of the storage capacitor is connected to the first power line. The second electrode of the fourth transistor is connected to the first power line, and the gates of the fourth transistor and the fifth transistor are both connected to the light emitting control line. The first electrode of the fifth transistor is connected to the anode of the light emitting element. A gate electrode of the sixth transistor is connected to a reset control line, and a second electrode of the sixth transistor is connected to a reset signal line.

11. The display substrate according to claim 10, wherein: In the second direction, adjacent pixel driving circuits share the reset signal line.

12. The display substrate according to claim 10, wherein: The reset control line, the reset signal line, the scan signal line, and the light emitting control line extend along the first direction, and the data line and the first power line include portions extending along the second direction.

13. The display substrate according to claim 10, wherein: The scanning signal line, the reset control line, the light emitting control line, the first electrode of the storage capacitor, and the gate of each transistor are formed in the same layer in the first sublayer of the pixel circuit layer, the reset signal line and the second electrode of the storage capacitor are formed in the same layer in the second sublayer of the pixel circuit layer, and the data line, the first power line, and the first electrode and the second electrode of each transistor are formed in the same layer in the third sublayer of the pixel circuit layer.

14. The display substrate according to claim 10, wherein: The light emitting element is a quantum dot light emitting diode.

15. A method for preparing a display substrate, comprising: Forming a substrate, the substrate having a groove extending along a first direction, the groove having a bottom surface and a side surface, the surface of the substrate including the bottom surface and the side surface of the groove, and a top surface between adjacent grooves, the bottom surface of the groove and the top surface between adjacent grooves are substantially parallel, and the side surface of the groove forms a first angle with the bottom surface of the groove and the top surface between adjacent grooves; A pixel circuit layer including a plurality of pixel driving circuits is formed on the substrate, wherein the plurality of pixel driving circuits are arranged in an array along a first direction and a second direction, wherein the first direction is perpendicular to the second direction, A portion of each pixel driving circuit is formed on a side surface of the groove, The pixel driving circuit includes at least one of a driving sub-circuit, a storage sub-circuit and a data writing sub-circuit formed on a side surface of the groove.

16. The preparation method according to claim 15, wherein: Forming the substrate comprises: The substrate is formed in a preformed mold using a flexible material.

17. The preparation method according to claim 15, wherein: Forming a pixel circuit layer including a plurality of pixel driving circuits on the substrate comprises: forming a layer of flexible material on the glass sheet; forming the plurality of pixel driving circuits on the flexible material layer; peeling the flexible material layer and the plurality of pixel driving circuits formed thereon from the glass plate; The flexible material layer and the plurality of pixel driving circuits formed thereon are attached to the substrate.

18. The preparation method according to claim 17, wherein: Forming the plurality of pixel driving circuits on the flexible material layer comprises: A signal line extending along the first direction and a signal line extending along the second direction are formed, and a first portion and a second portion of the signal line extending along the second direction are widened and thickened, wherein: After the flexible material layer and the multiple pixel driving circuits formed thereon are adhered to the substrate, the first portion is less than or equal to a first distance from a first bending line where the bottom surface and the side surface of the groove intersect, and the second portion is less than or equal to a second distance from a second bending line where the side surface of the groove intersects with the top surface between adjacent grooves.

19. The preparation method according to claim 17, further comprising: Before forming the flexible material layer on the glass plate, forming a sacrificial material layer on the glass plate; The sacrificial material layer is patterned to form a first stress relief structure and a second stress relief structure, each of the first stress relief structure and the second stress relief structure comprises a plurality of trapezoidal blocks arranged at intervals, a dimension of an end of each trapezoidal block of the first stress relief structure away from the glass plate is smaller than a dimension of an end thereof close to the glass plate, and a dimension of an end of each trapezoidal block of the second stress relief structure close to the glass plate is smaller than a dimension of an end thereof away from the glass plate, wherein: After the flexible material layer is formed on the glass plate, the first stress relief structure and the second stress relief structure are embedded in the flexible material layer. When the flexible material layer and the plurality of pixel driving circuits formed thereon are peeled off from the glass plate, the first stress relief structure and the second stress relief structure are peeled off from the glass plate together with the flexible material layer. After the flexible material layer and the multiple pixel driving circuits formed thereon are adhered to the substrate, the first stress relief structure is less than or equal to a first predetermined distance from a first bending line where the bottom surface and the side surface of the groove intersect, and the second stress relief structure is less than or equal to a second predetermined distance from a second bending line where the side surface of the groove intersects with the top surface between adjacent grooves.

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