A digital signal processing device

Abstract

The present disclosure provides a digital signal processing device, the digital signal processing device has a double network port, the double network port includes a first network port connected with a rear device and a second network port connected with a host computer, and the digital signal processing device comprises: a DSP master chip; a communication module connected with the DSP chip; a network port switching unit connected with the communication module and the double network port respectively, and the network port switching unit is configured to connect the DSP master chip with the first network port or the second network port when the DSP chip is in a corresponding working state. The digital signal processing device in the present disclosure realizes the connection with the corresponding device through the setting of the double network port, and in combination with the setting of the network port switching unit, the corresponding communication connection path can be switched during data acquisition and export, so that the system provided with the digital signal processing device can realize efficient export of original data and reduce the power consumption of the system.

Description

Technical Field

[0001] This disclosure relates to the field of digital signal processing technology, and more particularly to a digital signal processing apparatus. Background Technology

[0002] Among related technologies, deep-sea mooring communication systems have functions such as receiving, collecting, processing, and communicating underwater acoustic signals. They are widely used in the field of marine monitoring, and can be used to collect the navigation dynamics of enemy surface and underwater ships, as well as receive and respond to commands from friendly forces, which is of great significance to national defense security.

[0003] The electrical components of a deep-sea moored communication system are sealed inside a watertight compartment. When operating underwater, the system is battery-powered and remains in an autonomous state for extended periods. Therefore, reducing system power consumption and extending the system's operating time are urgent issues that the industry needs to address. When the system is recovered to shore, the raw data collected needs to be exported. Due to the large size of the watertight compartment, opening it to read the data is extremely difficult. Therefore, exporting the raw data without opening the watertight compartment is another challenge. The digital signal processing board within the electrical components is a core component of the deep-sea moored communication system, and its function determines the system's power consumption and data transmission methods. However, existing digital signal processing boards cannot solve these problems. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a digital signal processing apparatus.

[0006] This disclosure provides a digital signal processing device, which has dual network ports, including a first network port for communication connection with downstream devices and a second network port for communication connection with a host computer. The digital signal processing device includes:

[0007] DSP main control chip;

[0008] The communication module is connected to the DSP main control chip.

[0009] A network port switching unit is connected to the communication module and the dual network ports respectively. The network port switching unit is configured to connect the DSP main control chip to the first network port or the second network port when the DSP main control chip is in the corresponding working state.

[0010] According to some embodiments of this disclosure, the DSP main control chip includes a MAC layer, the communication module includes a physical layer chip, and the physical layer chip communicates with the MAC layer through an MII interface.

[0011] According to some embodiments of this disclosure, the network port switching unit includes two monostable relays, each of which is electrically connected to the first network port and the second network port respectively;

[0012] The two monostable relays are respectively connected to the physical layer chip for communication. One of the two monostable relays is connected to the signal transmission pin of the physical layer chip, and the other of the two monostable relays is connected to the signal reception pin of the physical layer chip.

[0013] According to some embodiments of this disclosure, the digital signal processing device further includes a quartz crystal resonator, which is communicatively connected to the physical layer chip.

[0014] According to some embodiments of this disclosure, the network port switching unit includes:

[0015] The first monostable relay has its first pin connected to the first input / output pin of the DSP main control chip, its second and seventh pins connected to the first network port, its third and sixth pins connected to the communication module, its fourth and fifth pins connected to the second network port, and its eighth pin connected to the second input / output pin of the DSP main control chip.

[0016] The second monostable relay has its first pin connected to the first input / output pin of the DSP main control chip, its second and seventh pins connected to the first network port, its third and sixth pins connected to the communication module, its fourth and fifth pins connected to the second network port, and its eighth pin connected to the second input / output pin of the DSP main control chip.

[0017] Specifically, when the DSP main control chip controls the first input / output pin to output a low level and the second input / output pin to output a low level, the first monostable relay and the second monostable relay are in a reset hold state, and the DSP main control chip is connected to the first network port for network signal reception and transmission; when the DSP main control chip controls the first input / output pin to output a high level and the second input / output pin to output a low level, the first monostable relay and the second monostable relay are in an activated state, and the DSP main control chip is connected to the second network port for network signal reception and transmission.

[0018] According to some embodiments of this disclosure, the digital signal processing apparatus further includes an FPGA control chip, which is communicatively connected to the DSP main control chip via a UPP interface, an EMIIF interface, and / or an IO interface.

[0019] According to some embodiments of this disclosure, the digital signal processing device further includes FPGA peripheral circuitry, the FPGA peripheral circuitry includes a power management chip, the FPGA control chip includes an output port, and the FPGA control chip supplies power to the power management chip through the output port.

[0020] According to some embodiments of this disclosure, the digital signal processing apparatus further includes a power supply circuit and a power control interface that are electrically connected to the DSP main control chip, and the DSP main control chip is connected to the FPGA control chip through the power control interface.

[0021] According to some embodiments of this disclosure, the digital signal processing apparatus further includes a non-volatile memory and a double-rate synchronous dynamic random access memory electrically connected to the DSP main control chip;

[0022] The digital signal processing device also includes a SATA serial hardware driver interface and an ADC data sampler electrically connected to the DSP main control chip.

[0023] According to some embodiments of this disclosure, the digital signal processing apparatus further includes an asynchronous transceiver, a clock, a sensor, DSP peripheral circuitry, and a JTAG interface, all electrically connected to the DSP main control chip.

[0024] Beneficial effects:

[0025] The digital signal processing device provided in this embodiment connects to the corresponding device by setting up dual network ports, and the network port switching unit can switch the corresponding communication connection path during data acquisition and export, thereby ensuring that the system equipped with the digital signal processing device can achieve efficient export of raw data and reduce the power consumption of the system.

[0026] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0028] Figure 1 A schematic diagram of the structure of a digital signal processing apparatus according to an exemplary embodiment is shown;

[0029] Figure 2 A structural diagram of a digital signal processing apparatus of an exemplary embodiment is shown;

[0030] Figure 3 A schematic diagram illustrating the working principle of a monostable relay in an exemplary embodiment is shown.

[0031] Figure 4 A schematic diagram of the structure of a digital signal processing apparatus according to an exemplary embodiment is shown;

[0032] Figure 5 A schematic diagram of the structure of a digital signal processing apparatus of an exemplary embodiment is shown. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0034] In related technologies, the electrical components of deep-sea mooring communication systems are sealed inside a watertight compartment. When operating underwater, these systems are battery-powered and remain in an autonomous state for extended periods. Therefore, reducing system power consumption and extending the operating time are urgent issues that the industry needs to address. When the system is recovered to shore, the raw data collected needs to be exported. Due to the large size of the watertight compartment, opening it to read the data is extremely difficult. Therefore, exporting the raw data without opening the watertight compartment is another challenge. However, the limited functionality of the digital signal processing board in the electrical components prevents the deep-sea mooring communication system from efficiently exporting raw data and reducing its power consumption.

[0035] This disclosure provides a digital signal processing device that connects to corresponding devices by setting up dual network ports, and by combining a network port switching unit to switch the corresponding communication connection path during data acquisition and export, thereby ensuring that the system equipped with the digital signal processing device can achieve efficient export of raw data and reduce the power consumption of the system.

[0036] This disclosure provides a digital signal processing apparatus, such as... Figure 1 As shown, Figure 1 A schematic diagram of a digital signal processing device is shown according to an exemplary embodiment. The digital signal processing device has dual network ports, including a first network port for communication connection with downstream devices and a second network port for communication connection with a host computer. By providing dual network ports, the digital signal processing device can achieve communication connections with corresponding devices. In this exemplary embodiment, the digital signal processing device includes:

[0037] DSP main control chip 100;

[0038] The communication module 300 is connected to the DSP main control chip 100.

[0039] The network port switching unit 200 is connected to the communication module 300 and the dual network port 400 respectively. The network port switching unit 200 is configured to connect the DSP main control chip 100 to the first network port of the dual network port 400 or to the second network port of the dual network port 400 when the DSP main control chip 100 is in the corresponding working state.

[0040] Considering that the digital signal processing device is a core component of the deep-sea mooring communication system, and to ensure that the system equipped with this digital signal processing device has a better communication connection in different operating states, the digital signal processing device in this exemplary embodiment is equipped with dual network ports. The first network port communicates with the downstream device, and the second network port communicates with the host computer. For example, when the system uses the digital signal processing device in this exemplary embodiment, in the first operating state, the device can communicate with the downstream device through its first network port, allowing control of the downstream device to perform data acquisition; in the second operating state, the device can communicate with the host computer and other devices through its second network port, allowing the acquired data to be exported to the host computer and other devices.

[0041] In this exemplary embodiment, the digital signal processing device can be applied to systems such as deep-sea mooring communication systems. By employing this digital signal processing device in a deep-sea mooring communication system, the communication needs of the system during underwater operation and the need to retrieve raw data from shore can be met, specifically through the dual network ports (e.g., two 10 / 100M adaptive network interfaces) of the digital signal processing device. During underwater operation, the digital signal processing device processes the collected raw data in real time and transmits the calculation results through the first network port to the downstream equipment inside the watertight compartment of the deep-sea mooring communication system. The downstream equipment encodes and sends out communication signals based on the calculation results. During shore operation, the deep-sea mooring communication system communicates with a host computer outside the watertight compartment through the second network port to export the raw data for depth analysis.

[0042] In some exemplary embodiments, the DSP main control chip includes a MAC layer, and the communication module includes a physical layer chip. The physical layer chip communicates with the MAC layer through an MII interface. The communication connection between the MAC layer of the DSP main control chip and the MII interface of the physical layer chip of the communication module improves data transmission efficiency.

[0043] In this exemplary embodiment, considering that the digital signal processing device not only needs to reduce system power consumption but also needs to ensure high data transmission efficiency, a MAC layer is designed in the DSP main control chip. For example, the DSP main control chip includes a TMS320C6748 processor, which has a 10 / 100Mbps Ethernet MAC layer and supports both MII and RMII media-independent interfaces. The communication module can be an Ethernet communication module. For example, this Ethernet communication module includes a physical layer chip LNA8710A. In this exemplary embodiment, the digital signal processing device uses the low-power physical layer chip LNA8710A as its core in the communication module to achieve network communication with the Ethernet MAC layer of the TMS320C6748 processor through the MII interface.

[0044] In some exemplary embodiments, the network port switching unit in this exemplary embodiment uses monostable relays to control the switching between the two network ports. For example, the network port switching unit includes two monostable relays. Each monostable relay is electrically connected to the first network port and the second network port, respectively; the two monostable relays are communicatively connected to the physical layer chip, one of the two monostable relays is connected to the signal transmit pin of the physical layer chip, and the other of the two monostable relays is connected to the signal receive pin of the physical layer chip. For example, as... Figure 2 As shown, when the DSP main control chip 100 uses a TMS320C6748 processor and the communication module 300 uses a physical layer chip LNA8710A, the Ethernet MAC layer of the TMS320C6748 processor is connected to the physical layer chip LNA8710A of the communication module 300 through the MII interface; the signal transmission pin of the physical layer chip LNA8710A in the communication module 300 is connected to the first monostable relay 201, and the signal receiving pin of the physical layer chip LNA8710A is connected to the second monostable relay 202; each monostable relay is electrically connected to the first network port 401 and the second network port 402 respectively.

[0045] In this exemplary embodiment, the digital signal processing device can optimize system energy consumption by controlling the switching of monostable relays, thereby making the system more energy-efficient. For example, in a deep-sea moored communication system, the digital signal processing device, installed after it, enables two-way 10 / 100M network communication based on the monostable relays used in the device. This effectively reduces the power consumption of the digital signal processing device, thereby reducing the overall system power consumption and increasing the underwater operating time of the deep-sea moored communication system.

[0046] In this exemplary embodiment, the digital signal processing device further includes a quartz crystal resonator 500, which is communicatively connected to the physical layer chip of the communication module 300. For example, when the communication module 300 uses the physical layer chip LNA8710A, the LAN8710A chip can be externally connected to a high-precision 25MHz quartz crystal resonator 500 to provide a reference frequency for data transmission. Its internal phase-locked loop can be configured via software to multiply the frequency to the required reference frequency using corresponding registers.

[0047] In some exemplary embodiments, considering that two monostable relays can be connected to the physical layer chip of the communication module, switching control of the first network port and the second network port connected to the DSP main control chip can be achieved. The monostable relay structure is as follows: Figure 3 As shown, when the first pin A is low and the eighth pin H is in any state, the third pin C and the second pin B are connected, and the sixth pin F and the seventh pin G are connected. At this time, the monostable relay is in the reset holding state. When the first pin A is high and the eighth pin H is low, the third pin C and the fourth pin D are connected, and the sixth pin F and the fifth pin E are connected. At this time, the monostable relay is in the operating state.

[0048] In this exemplary embodiment, the network port switching unit includes: a first monostable relay and a second monostable relay. For example... Figure 4 As shown, Figure 4 An exemplary embodiment of a network switching function block diagram is shown. The first pin A1 of the first monostable relay is connected to the first input / output pin IO1 of the DSP main control chip; the second pin B1 and the seventh pin G1 of the first monostable relay 201 are both connected to the first network port 401; the third pin C1 and the sixth pin F1 of the first monostable relay 201 are both connected to the communication module 300; the fourth pin D1 and the fifth pin E1 of the first monostable relay are both connected to the second network port 401; and the eighth pin H1 of the first monostable relay 201 is connected to the second input / output pin IO2 of the DSP main control chip 100; the first pin of the second monostable relay... A2 is connected to the first input / output pin IO1 of the DSP main control chip 100; the second pin B2 and the seventh pin G2 of the second monostable relay 201 are both connected to the first network port 401; the third pin C2 and the sixth pin F2 of the second monostable relay 202 are both connected to the communication module 300; the fourth pin D2 and the fifth pin E2 of the second monostable relay 202 are both connected to the second network port 402; and the eighth pin H2 of the second monostable relay 202 is connected to the second input / output pin IO2 of the DSP main control chip 100. The communication module 300 is connected to the DSP main control chip 100.

[0049] When the DSP main control chip 100 controls the first input / output pin IO1 to output a low level and the second input / output pin IO2 to output a low level, the first monostable relay 201 and the second monostable relay 202 are in a reset holding state, and the DSP main control chip 100 is connected to the first network port 401 to receive and transmit signals over the network; when the DSP main control chip 100 controls the first input / output pin IO1 to output a high level and the second input / output pin IO2 to output a low level, the first monostable relay 201 and the second monostable relay 202 are in an activated state, and the DSP main control chip 100 is connected to the second network port 402 to receive and transmit signals over the network.

[0050] based on Figure 4 The network switching function structure is shown. In this exemplary embodiment, after the digital signal processing device is used in the deep-sea mooring communication system, when the DSP main control chip 100 controls the first input / output pin IO1 to output a low level and the second input / output pin IO2 to output a low level, the first monostable relay 201 and the second monostable relay 202 are in a reset holding state, and the signal receiving pin and signal transmitting pin of the communication module 300 are connected to the first network port. At this time, the downstream devices of the deep-sea mooring communication system communicate and complete data interaction. When the DSP main control chip controls the first input / output pin IO1 to output a high level and the second input / output pin IO2 to output a low level, the first monostable relay 201 and the second monostable relay 202 are in an active state, and the signal receiving pin and signal transmitting pin of the communication module 300 are connected to the second network port. At this time, the deep-sea mooring communication system communicates with the host computer outside the watertight compartment to export the raw data collected inside the watertight compartment, perform program updates, parameter configurations, etc.

[0051] In this exemplary embodiment, when the two monostable relays are switched to the first network port 401 to communicate with the downstream equipment inside the watertight compartment, the first and eighth pins of the two monostable relays are pulled low by the DSP main control chip, and the two monostable relays are in a physical reset holding state, and the monostable relays do not consume power. When the two monostable relays are switched to the second network port 402 to communicate with the host computer outside the watertight compartment, the first and eighth pins of the two monostable relays are pulled high and low by the DSP main control chip, respectively, and the two monostable relays are in an active state. The power consumption of each monostable relay is 100mW. However, at this time, the deep-sea mooring communication system is on shore and powered by external power, so the power consumption factor is not considered.

[0052] In some exemplary embodiments, such as Figure 5As shown, the digital signal processing device also includes an FPGA control chip. The FPGA control chip communicates with the DSP main control chip through a UPP interface, an EMIIF interface, and / or an IO (Input / Output) interface. In this exemplary embodiment, the DSP main control chip serves as the core management module of the digital signal processing device. The DSP main control chip can be designed using a TMS320C6748 processor to implement functions such as signal processing, system control and scheduling, data transmission, data storage control, and external communication. This processor has a floating-point data operation capability of 2.746 MFLOPS and rich peripheral resources, including a UPP (Universal Phone Processor) interface, a UART interface, an EMIFA interface, an SPI (Serial Peripheral Interface), an I2C (Inter-Integrated Circuit) interface, and a MAC interface. The peripheral circuit of the DSP main control chip includes 64MB of Nor Flash for storing programs and 256MB of DDR SDRAM (Double Data Rate SDRAM) for data caching.

[0053] In some exemplary embodiments, such as Figure 5 As shown, the digital signal processing device also includes FPGA peripheral circuitry, which includes a power management chip. The FPGA control chip includes an output port, and the FPGA control chip supplies power to the power management chip through the output port.

[0054] As the peripheral device timing control and data transmission center of the system, the FPGA is mainly responsible for implementing functions such as high-speed A / D acquisition, signal preprocessing, digital I / O (Input / Output) control, interface expansion, and interfacing with DSPs. Signal preprocessing primarily involves digital bandpass filtering of the acquired signal, with a bandwidth of 300Hz–600Hz and an order of 64. The bandwidth and order can be adjusted according to actual needs. For example, the FPGA can be an XC6SLX45 in an FG484 package as the logic implementation platform. The device resources are as follows:

[0055] 1) 6822 slices, 43661 logic cells, 54476 triggers;

[0056] 2) Supports up to 400K distributed RAM for 58 DSP48A1 chips and 2088Kb of Block RAM;

[0057] 3) Supports up to 320 IOs (for 19mm×19mm CSG484 package).

[0058] Data interaction and sharing between the FPGA peripheral circuit and the DSP main control chip are achieved through the EMIF bus and the UPP interface. The EMIF can be used for register setting and access, and the UPP can be used for large data transmission, thus not occupying the external bus of the DSP main control chip. The DSP main control chip can directly obtain A / D acquisition data from the FPGA.

[0059] In some exemplary embodiments, such as Figure 5 As shown, the digital signal processing device also includes a power supply circuit and a power control interface that are electrically connected to the DSP main control chip. The DSP main control chip is connected to the FPGA control chip through the power control interface.

[0060] In some exemplary embodiments, such as Figure 5 As shown, the digital signal processing device also includes a non-volatile memory and a double-rate synchronous dynamic random access memory electrically connected to the DSP main control chip; the digital signal processing device also includes a SATA serial hardware driver interface and an ADC data sampler electrically connected to the DSP main control chip.

[0061] In this exemplary embodiment, the DSP main control chip controls the FPGA's input / output pins to power on the power management chip of the peripheral module. As the system's algorithm processing unit, the DSP main control chip receives ADC (analog-to-digital converter) sampling interrupts, performs real-time algorithm processing on the saved ADC raw sampling data, and sends it to the back-end processor in the watertight compartment or uploads it to the host computer via TCP / IP network protocol according to the agreed protocol.

[0062] In some exemplary embodiments, such as Figure 5 As shown, the digital signal processing device also includes an asynchronous transceiver, a clock, a sensor, DSP peripheral circuits, and a JTAG interface, all of which are electrically connected to the DSP main control chip.

[0063] The digital signal processing device disclosed herein achieves dual-port communication functionality by incorporating a monostable relay into its Ethernet communication circuit. This provides ultra-low power consumption and reduces the complexity of the dual-port communication circuit. When this digital signal processing device is used in a deep-sea communication mooring system, the system is powered by a battery within its watertight compartment during autonomous underwater operation, thus placing stringent power consumption requirements. The monostable relay, in its reset state, offers zero power consumption. By controlling the monostable relay to its reset state when the deep-sea mooring communication system uses Ethernet communication underwater, the overall system power consumption can be effectively reduced, increasing the system's underwater operating time.

[0064] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0065] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0066] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0067] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0068] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0069] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A digital signal processing device, characterized in that, The digital signal processing device has dual network ports, including a first network port for communication connection with downstream devices and a second network port for communication connection with a host computer. The digital signal processing device includes: DSP main control chip; The communication module is connected to the DSP main control chip. A network port switching unit is connected to the communication module and the dual network ports respectively. The network port switching unit is configured to connect the DSP main control chip to the first network port or the second network port of the dual network ports when the DSP main control chip is in the corresponding working state. The DSP main control chip includes a MAC layer, and the communication module includes a physical layer chip. The physical layer chip communicates with the MAC layer through a MII interface. The network port switching unit includes two monostable relays, each of which is electrically connected to the first network port and the second network port respectively; The two monostable relays are respectively connected to the physical layer chip for communication. One of the two monostable relays is connected to the signal transmission pin of the physical layer chip, and the other of the two monostable relays is connected to the signal reception pin of the physical layer chip. The digital signal processing device further includes a quartz crystal resonator, which is communicatively connected to the physical layer chip. The network port switching unit includes: The first monostable relay has its first pin connected to the first input / output pin of the DSP main control chip, its second and seventh pins connected to the first network port, its third and sixth pins connected to the communication module, its fourth and fifth pins connected to the second network port, and its eighth pin connected to the second input / output pin of the DSP main control chip. The second monostable relay has its first pin connected to the first input / output pin of the DSP main control chip, its second and seventh pins connected to the first network port, its third and sixth pins connected to the communication module, its fourth and fifth pins connected to the second network port, and its eighth pin connected to the second input / output pin of the DSP main control chip. Specifically, when the DSP main control chip controls the first input / output pin to output a low level and the second input / output pin to output a low level, the first monostable relay and the second monostable relay are in a reset hold state, and the DSP main control chip is connected to the first network port for network signal reception and transmission; when the DSP main control chip controls the first input / output pin to output a high level and the second input / output pin to output a low level, the first monostable relay and the second monostable relay are in an activated state, and the DSP main control chip is connected to the second network port for network signal reception and transmission.

2. The digital signal processing apparatus according to claim 1, characterized in that, The digital signal processing device further includes an FPGA control chip, which is connected to the DSP main control chip via a UPP interface, an EMIIF interface, and / or an IO interface.

3. The digital signal processing apparatus according to claim 2, characterized in that, The digital signal processing device further includes FPGA peripheral circuitry, which includes a power management chip. The FPGA control chip includes an output port, and the FPGA control chip supplies power to the power management chip through the output port.

4. The digital signal processing apparatus according to claim 3, characterized in that, The digital signal processing device further includes a power supply circuit and a power control interface that are electrically connected to the DSP main control chip, and the DSP main control chip is connected to the FPGA control chip through the power control interface.

5. The digital signal processing apparatus according to claim 1, characterized in that, The digital signal processing device also includes a non-volatile memory and a double-rate synchronous dynamic random access memory electrically connected to the DSP main control chip. The digital signal processing device also includes a SATA serial hardware driver interface and an ADC data sampler electrically connected to the DSP main control chip.

6. The digital signal processing apparatus according to claim 1, characterized in that, The digital signal processing device also includes an asynchronous transceiver, a clock, a sensor, DSP peripheral circuitry, and a JTAG interface, all electrically connected to the DSP main control chip.

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